Thermometer decoder 40

Discrete quantities of information are represented in digital system by binary codes. A binary code of n bits is capable of representing up to 2ⁿ distinct element of coded information.

A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2ⁿ unique output lines. If the n-bit coded information has unused combinations, the decoder may have fewer than 2ⁿ outputs.

Binary-to-thermometer decoder accomplishes the equivalence of elements from binary code. The Tab. 4.1 shows truth table of a 4-to-16 line decoder. The circuit of the 4-to-16 bits binary-to-thermometer decoder will be realized. Finally, the Boolean function between the binary-input and thermometer-output are described in tab. 4.2.

Decimal d c b a ^{A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15}

A0

(

a+b+c+d

)

^A1

(

b+c+d

)

^A2

(

a•b+c+d

)

^A3

(

c +d

)

A4

( ( (

a+b

)

•c

)

+d

)

^A5

(

b•c+d

)

^A6

(

a•b•c+d

)

^A7 d

A8

( (

a+b+c

)

•d

)

^A9

( (

b+c

)

•d

)

^A10

( (

a•b+c

)

•d

)

^A11

(

c •d

)

A12

(

a•b+c+d

)

^A13

(

b•c•d

)

^A14

(

a•b•c•d

)

^A15 1

Table 4.2 Boolean functions between the binary-input and thermometer-output

From the Fig. 4.2, the system block diagram reveals that one kind of 8-bit thermometer decoder is essential. The 8-bit thermometer decoder is divided into tow 4-bit thermometer decoder. Row-column selection decoding is a simple method to supply high speed transformation [6]. In high speed realization, the adopted decoder can limit the clock rate of the D/A converter.

4.2.2 Randomizer

Thus, a remaining problem is to develop high resolution DAC’s that achieve such low levels of harmonic distortion. In the past, random element matching techniques have been successfully applied to de-correlate the DAC noise from the input signal in various DAC topologies.. For most digital input values, there are many possible input codes to the bank of randomizer that nominally yield the desired analog output value. Thus, the DAC noise arising from errors introduced by the randomizer can be “scrambled” by randomly selecting one of the appropriate codes for each digital input value. Although DAC’s based on this approach have been shown experimentally [23], and through quantitative analysis [19] to achieve excellent SFDR’s.

Fig. 4.3 (a) shows a 2^M bit input and 2^M bit output randomizer. The random control bit is common to a random generator. Fig. 4.3 (b) shows 8-bit input and output MUX with 3-bit selection. The random generator controls the selection of the element in the MSB part so that the harmonics caused by mismatch can be attenuated. A perfect synchronization of the control signals at the DAC, so the random generator is controlled with the clock, thus well-designed synchronized driver is used in entire circuit. Fig 4.4 shows the circuit of random generator.

Figure 4.3 (a) A 2^M bit input and 2^M bit output randomizer (b) 8-bit input and output MUX with 3-bit selection.

Figure4.4 Random generator

4.2.3 High speed latch

The dynamic performance degradation of a current-steering DAC can be caused by several reasons associated with current source switching. Some important issues that have been identified to cause dynamic limitations are:

Imperfect synchronization of the control signals at the switches.

Drain-voltage variations of the current-source transistors caused by the fact that both switch transistors are simultaneously in the off state.

Coupling of the control signals through the C^gd of the switches to the output.

To minimize the three effects, a well-designed synchronized driver is used. The high speed, low glitch latch is illustrated in Fig. 4.5(a). It provides two complementary signals needed at the input of the current switches.

In the conventional latch, both switches will be off for a short period. As a result, the capacitance at the drain of the current source transistor will be charged and then the current source will turn off. To recover the normal operation, the current source must progress through the linear region and back into saturation. Hence, turning off the current source not

only slows down the speed but also increases glitch at the output. To solve the problem, the function of this latch is designed to shift down the crossing point of the differential signals used for driving the switches of the current cell.

The latch used here is a rise/fall time based driver. In order to obtain instantaneous change for output node with falling input, extra PMOS transistors (M1 and M2) are placed in parallel with each other cross-coupled at the top of the circuit. When the transitions of input signals (high  low or low  high) occur, the transistors M3-M10 will immediately change their states. However, the crossed-coupled PMOS transistors M1 and M2 will hold their states for a short period. After these transistors change their states, the charging speed will be increased. Thus, the combination of the (µn / µp) scaled PMOS transistors and the PMOS positive feedback loop results in the rise time that is much faster than the fall time of the driver circuit. Due to the use of two additional inverters at the output of the driver and properly sizing the transistors of the whole latch, a lower crossing point can be realized. Fig. 2 (b) shows the voltage waveforms of the differential outputs, Q and Q . This latch not only performs the final synchronization of the signals used for switching different current cells but also reduces the delay between the different digital decoders.

D CK

D

Q Q

(a)

Q

Q

(b)

Figure.4.5 (a) Dynamic latch schematic diagram (b) Output signals

4.3 Current Cell

To generate the accurate current, several concerns should be taken into account. First, the size of the current sources should be properly designed to reduce the mismatch error between different current sources due to the fabrication. Second, the finite output impedance of each current source is designed large enough to get a good static performance. Finally, a bias circuit used to generate the bias current of current source is also required. The design considerations and circuit implementation of each circuit is described in next subsections.

4.3.1 Implementation of Switch Unit Current Cell

The PMOS current source has two advantages. PMOS devices built in n-well are thus shielded from the substrate. PMOS has less flicker noise than NMOS. The circuit schematic of the cascode switch current cell is shown in Fig. 4.6(a). The output impedance of the current cell which is ro_cas +ro_cs⋅

(

¹+gm_cas⋅ro_cas

)

is very large. Beside, this design utilizes Gain-Boosting

to increase the output impedance (

cas ocas

A gm r× ) in current-voltage feedback in Fig 4.6(b).

The output impedance is A times the size of the cascode without Gain-Boosting. In the following content, we will continue to find out what size of current source transistor should be used. If we want to decide the size of the current cell, we need INL_yield, process parameter

(Aβ and AVT), and gate overdrive voltage (VGS-VT) . We also need to consider DAC specification, including INL and SFDR [1]

Q _Q

out o

R ≈ Agmr R

Figure.4.6 (a) The circuit schematic of the cascode current cell (b) Gain-Boosting

Using the mismatch model derived in [14], the minimum area requirement for the LSB

And the square-law model W/L ratio can then expressed as:

( )

²

2

_{L S B}

G S T

W I

L β V V

=

−

(4.2)

In this way, we can find out the size of the current cell.

4.3.2 Reference Current Generation

Fig. 4.7 shows the biasing scheme for the cascode current sources. An external resistor, R, is used to generate the reference current. The NMOS sections of the biasing circuits are labeled as “global biasing” while the PMOS sections are labeled as “local biasing.” The cascode current mirror in the current cell can be used to reduce short-channel effects and increase the output impedance, but it will limit the signal swing. In order to reduce this limitation, a wide-swing cascode current mirror bias scheme is shown in “local biasing” of Fig. 4.7. The transistors M6 is gain-boosting

Figure 4.7 The circuit schematic of the bias circuit

4.4 Layout

The layout of the DAC plays an important role since the random mismatch of current source due to process variation will degrade the accuracy of the DAC significantly. Thus we should pay mode attention to the floor plan of the DAC and special layout technique should be used, like [6] , [8] and [10] . Fig. 4.8 shows “balanced ring” technique of this work for reduction of quadratic errors. We utilize this technology to divide the unit of the current cell into four groups, each group is two rings. To compensate for symmetrical and graded errors caused by temperature, process, and electrical gradients, special switching schemes should be implemented.

Figure. 4.8 “Balanced ring” technique of this work for reduction of quadratic errors.

(a) (1,8) rings (b) (2,7) rings (c) (3,6) rings (d) (4,5) rings

Original "balanced-ring" technology may be unable to reach match because the ones that assign are not perfect enough. So we need to utilize and calculate the way distribute the position of the current source cell again. We first consider a quadratic error oriented to the main axes of array. The origin of the coordinate system is location at the common boundary of four subschemes. The systematic error is described by

2

A constant offset to all unary sources does not affect the linearity, and thus the quadratic error is cancelled.

We now consider a quadratic error with its axes rotated with respect to the array. The error is oriented along the axes x’ and y’ in Fig. 4.9 and is described by

2

After transformation, this yields

Figure 4.9 Orientation of the axes X’ and Y’. Rotation of the quadratic error compared error compared to the main axes of the current source array.

The sum of terms in x² and y² is constant over each unary source, as seen above. Once again, a constant offset to all unary sources does not affect the linearity. We still need to need to

show that the sum of terms in xy is constant over each source. Let us consider the xiyi

products row by row. All sources have exactly two elements in each row, one in each half.

Each row i contribute a term xiyi and a term - xiyi to sum. Due to this symmetry, all terms in xy are cancelled. This type of quadratic error is cancelled also.

D D D D D D D D D D D D D D D D D D D

Figure.4.10 Selection sequence for MSB part of input code for improved “balanced-ring”

technique

In this design a floor plan of current cell matrix called improved “Balanced-ring” is used, as shown in Fig. 4.10. In the improved “balanced-ring” technique, the array is subdivided into rings as shown by rings 1 to 8. First, we add up the quadratic errors of the cells within each ring. Then, starting from the ring 1 and 8, we determine how many of the ring 2 and 7 and ring 3 and 6 and ring 4 and 5 are required to cancel the error in ring 1 and ring 6. It turns out that eight rings will do the job as shown in Fig. 4.8.Due to systematic and quadratic effects, the parameters of the transistors vary depending on their location in the current source array. A good switching sequence switches the sources so that the errors do not accumulate, is seen in Fig. 4.9. Now in each step we select the cells from counterpart rings in a way that avoids accumulation of quadratic errors, as described above. Of course all these selections also obey the procedure.

Dummy cells and bias circuits can be placed in the “d” cell matrix. But additional rows or columns of dummy current source will not cause significant area increase of the current cell matrix.

Fig. 4.11 (a) shows A 12-bit 250MHz current-steering segmented architecture DAC without the partial random element matching. The digital part of the DAC is placed on the left and the current cell matrix is placed on the right. Fig. 4.11 (b) shows A 12-bit 250MHz current-steering segmented architecture DAC with the partial random element matching. The current source is placed on the middle and the digital part of the DAC is placed on both sides.

To minimize the systematic error introduced by the voltage drop in the ground lines of the current-source transistors, wide sheets of metal have been used. Special care has been taken to realize a symmetrical interconnection array in order not to degree the matching performance.

The power domains were separated into three parts: analog, digital and guard ring to avoid the analog section disturbed by the transient current of logic switching. The pins for ground and

output were assigned more than one because of reducing the IR drop effect and parasitic inductance. In the current source array, dummy cells were adopted to lower the edge effect and can be treated as decoupling capacitor on the sensitive bias nodes. They are created by dummy transistor with body, source and drain all connected.

The chip will be fabricated with TSMC 0.18 µm mixed signal technology. The final layout was shown in the Fig. 4.11. These numbers in the graph means the pin orientation in the package. The active die size has 1.788 µm² and 1.838 µm² .

(a) (b) Figure.4.11 The final layout

4.5 Summary

A 12-bit 250-MSamples/s current–steering CMOS D/A converter with the partial random element matching show that with designed in this chapter. The architecture is shown first. Then, the design consideration and circuit diagram of each sub-block is described in each section. Finally, the layout concern and the switching scheme of current cell matrix have also been discussed. Since the DAC has been designed, the simulation and result of this DAC should also be presented to test the performance. This will be done in the next chapter.

Chapter5

Simulation Result and Measurement

This current DAC has been designed and laid out by using the TSMC 0.18 µm CMOS Mixed-Signal process with one poly and six metals. In this chapter, we present simulation resultant and the testing environment. The measured results are presented in this chapter, too.

5.1 Simulation results

First a 12-bit 500-MSample/s D/A converter without partial random element matching, is 67.59 dB for signal frequencies up to 195.8 MHz. The major target specification for SFDR of this paper, a 12-bit 250-MSample/s D/A converter with partial random element matching, is 60 dB for signal frequencies up to 170 MHz. An additional design goal was to derive maximum benefit from this relatively advanced technology.

A simulate sine wave spectrum for (a) Fs = 500 MHz and Fsig = 1.46 MHz (b) Fs

= 500 MHz and Fsig = 195.8 MHz without partial random element matching is shown in Fig. 5.1. Fig. 5.2 shows the SFDR of input frequency between 0.488 MHz and 245.6 MHz without partial random element matching at the sample rate 500 MHz.

The differential nonlinearity (DNL) and integral nonlinearity (INL) without partial random element matching are shown in the Fig 5.3. A simulate sine wave spectrum for (a) Fs = 250 MHz and Fsig = 0.244 MHz (b) Fs = 250 MHz and Fsig = 100.83 MHz with partial random element matching is shown in Fig. 5.4. Fig. 5.5 shows the SFDR

of input frequency between 0.244 MHz and 122.8 MHz at the sample rate 250 MHz MHz. The differential nonlinearity (DNL) and integral nonlinearity (INL) without partial random element matching are shown in the Fig 5.6. The total simulation result of this DAC is summarized in Table 5-1.

Figure.5.1 Sine wave spectrum for (a) Fs = 500 MHz and Fsig = 1.46 MHz (b) Fs = 500 MHz and Fsig = 195.8 MHz without partial random element matching

Figure5.2 The SFDR of input frequency between 0.488 MHz and 245.6 MHz at the sample rate 500 MHz without partial random element matching

Figure5.3 The differential nonlinearity (DNL) and integral nonlinearity (INL) without partial random element matching

(a) (b)

Figure.5.4 Sine wave spectrum for (a) Fs = 250 MHz and Fsig = 0.244 MHz (b) Fs = 250 MHz and Fsig = 100.83 MHz with partial random element matching

Figure 5.5 The SFDR of input frequency between 0.244 MHz and 122.8 MHz at the sample rate 250 MHz with partial random element matching

Figure 5.6 The differential nonlinearity (DNL) and integral nonlinearity (INL) with partial random element matching

Table 5-1 The total simulation results of this DAC

Sampling Frequency 500 MHz 250 MHz

DNL < 0.8 LSB < 0.5 LSB Spectrum Analyzer to get spectrum performance. The Voltage transient output signals

are measured by Agilent 34401 Digital Multi-meter. Two precise power supplies are used to generate both analog and digital supply.

9V Battery LM317 adjustable regulators shown in Fig. 5.8. The capacitor C1 is used to improve the ripple rejection and capacitor C2 is the input bypass capacitor. The resistor R1 is the fixed resistor and resistor R2 is the precise variable resistor. The inductance L1 and the capacitor C3, C4, C5 and C6 is a low-pass filter. The output voltage of the Fig.

5.8 can be expressed as

Where IADJ is the DC current that flows out of the adjustment terminal ADJ of the regulator. By the way, the resistor R1 can use the low temperature coefficient of the metal film resistor to get the stable output voltage.

Fig. 5.8 Power supply regulator

5.3 Measurement Results

The sample rate is set to 100 MHz at input frequency 2 MHz, 5.17 MHz, 12.83 MHz, 20.67 MHz and 29.15 MHz, respectively. A measured sine wave spectrum for Fs = 20 MHz and Fsig = 1 MHz is shown in Fig. 5.9. A measured sine wave spectrum for Fs = 100 MHz and Fsig = 2 MHz and 9.8758 MHz is shown in Fig. 5.10 and Fig.

5.11. A measured sine wave spectrum for Fs = 200 MHz and Fsig = 19.81 MHz is shown in Fig. 5.12. Fig. 5.13 shows the SFDR of input frequency between 2 MHz and 29.15 MHz at the sample rate 100 MHz. The differential nonlinearity (DNL) and integral nonlinearity (INL) are shown in the Fig 5.13. The total measured result of this DAC is summarized in Table 5-2 and the die microphotograph is shown in Fig. 5.14.

Figure.5.9 Sine wave spectrum for Fs = 20 MHz and Fsig = 1 MHz

Figure.5.10 Sine wave spectrum for Fs = 100 MHz and Fsig = 2 MHz

Figure.5.11 Sine wave spectrum for Fs = 100 MHz and Fsig = 9.8758 MHz

Figure.5.12 Sine wave spectrum for Fs = 200 MHz and Fsig = 19.81 MHz

Figure 5.13 The SFDR of input frequency between 3 MHz and 34.33 MHz at the sample rate100 MHz

Figure 5.14 The differential nonlinearity (DNL) and integral nonlinearity (INL)

Figure 5.15 The die microphotograph

Table 5-2 The total measurement results of this DAC

Process

TSMC 0.18 µm CMOS Mixed-Signal

Supply Voltage

Digital supply 1.8V Analog supply 3.3V

Sampling Frequency 100 MHz

DNL < 5 LSB

INL < 9 LSB

SFDR(Fin = 2 MHz) 46 dB @ CLK = 100 MHz

Power Dissipation 125 mW

Active Area 1.778 mm²

Chapter6

Conclusions and Future Work

In this thesis, the 12-bit 250-MHz DAC is implementation. We propose a new simple random structure and special layout to improve the static and dynamic linearity.

The current source is properly designed to reduce the nonlinearity caused by finite output impedance of current source. To overcome the random error and systematic error, the proper area of current source is selected and special layout technique is used.

A high speed, low crossing point latch is implemented to compensate the error at the DAC output due to switching in the current cells. The DAC is fabricated by 0.18µm 1P6M CMOS Mixed-Signal. Besides, the power dissipation is 125mW. The measure resultant of a 12-bit current-steering D/A converter without the partial random element matching shows that the signal frequency of 9.87 MHz at the update rate of 100 MHz, the SFDR is 37 dB. The differential nonlinearity and integral nonlinearity are below 5 and 9 least significant bits (LSB’s).

The DAC can be improved from several points of view in the future. First, due to lack of considering the parasitic loading effect caused by the layout, the post-layout dynamic performance simulation results will be degraded than the pre-layout simulation at high input frequency. Therefore, the DAC should be designed to keep enough margins to endure the loading effect and the floor plan should be modified to decrease the parasitic loading. Second, after passing through multi-bit registers to sample the input digital data, the MSBs and LSBs are binary-weighted. Third, the clock should be designed carefully because the current DAC operated at high speed.

And pay more attention to routing between circuit block. Finally, we can propose a calibration structure to improve the matching accuracy of the current sources is applied for high-resolution DACs. Because of the lower matching requirement of the current sources, the chip area is smaller and the cost is lower, too.

References

[1] Mikael Gustavsson, J Jacob Wikner and Nianziong Nick Tan, “CMOS Data Converters for communications,” Kluwer Academic Publishers, Boston,2000.

[2] Farzen K., Johns D.A., “A power-efficient architecture for high-speed D/A

[2] Farzen K., Johns D.A., “A power-efficient architecture for high-speed D/A

在文檔中 具有部分隨機匹配的12位元250百萬赫芝電流式互補式金氧化半導體數位類比轉換器 (頁 53-0)