Chapter 1 Introduction
1.2 Organization
control
Figure 1.1 Block diagram of a thermal aware system.
inherently low currents in that region. However, this circuit does not allow strong supply voltage scaling.
Serra-Graells and Huertas [10] introduce an all-MOS implementation exhibiting enough low-voltage capabilities by the use of MOS sub-threshold techniques.
However, in this circuit, the current leaking device in modern deep sub-micron CMOS technology has cause the linearity problem of the PTAT and IOAT signals in high temperature range.
These nonlinearity behaviors are crucial effect to implement a complete thermal management system within a digital circuit since such circuitries require more efforts and costs for after process calibration. Thus, linearity and power issues are the key factors for design a fully integrated temperature sensor in the deep sub micron CMOS technology.
In this thesis, both PTAT and IOAT voltage references are redesigned by utilizing sub-threshold MOSFETs and temperature complementation technique to enhance the linearity and produce a more stable output. The propose design has extend the linear temperature rage of on-chip temperature sensor to -55°C to 170°C which provides a practical solution for modern system-on-chip’s thermal management systems.
1.2 Organization
Chapter 2 begins with the review of the temperature sensing, from mercury-in-glass thermometers to very low power and low cost smart temperature sensors. Then the temperature sensing methods both with bipolar transistors and subthreshold MOSFETs are described. For the low-power consideration, subthreshold MOSFETs
Chapter 1 Introduction are more suitable than bipolar transistors. We also demonstrated the nMOS is better than pMOS for the design.
Chapter 3, first, introduces the MOS PTAT reference circuitry architecture which has been proposed in [11]. Then the new PTAT and IOAT reference circuitry architectures have been proposed. The first version is resistor-based reference circuitry architecture. For the area consideration, the second version, all-MOS reference circuitry architecture, has been proposed. The all-MOS reference circuitry architecture also enhances the compensative mechanism. All the detail design concepts will be described in this Chapter.
In Chapter 4, the simulation and experiment results are introduced. First, the resistor-based reference circuitry architecture has been simulated in TSMC 0.18μm 1P6M CMOS technology. Then, the simulation results of all-MOS version which are simulated with both TSMC 0.18μm and 0.13μm CMOS technology have been shown.
All-MOS version’s layout consideration is also described. Finally, the experiment results and discussion are discussed.
The conclusions and future works of this thesis are given in Chapter 5.
Chapter 2 Temperature Sensing
CHAPTER
2
Temperature Sensing
This Chapter begins with the introduce of smart temperature sensors. Following the brief introduce, the methods of temperature sensing both with bipolar transistors and subthreshold MOSFETs are described. For the low power applications, the n-type subthreshold MOSFETs are more suitable than p-type, this result is demonstrated on a deep-submicron technology. A brief conclusion is made in the end of the Chapter.
2.1 CMOS Smart Temperature Sensors
As time goes by, due to the remarkable market growth portable systems nowadays, the demand for very low power and low cost but high performance temperature sensors is becoming much stronger than ever. To reduce the cost of a system that consists of both a temperature sensor and a computer interface, integration of the temperature sensor and the analog-to-digital converter was attempted. This new system family was called integrated smart temperature sensors. Figure 2.1 shows this system.
The important nowadays applications of smart temperature sensors include: 1) the power consumption control in VLSI chips; 2) the thermal compensation in single-chip systems and micro systems with built-in sensors; 3) the environment temperature monitor in automatic fabrication factories; and 4) the temperature control of consumer electronics. However, temperature sensing with bipolar transistor do not exhibit enough low-power capabilities [12]-[14]. This disadvantage is a very fatal reason for the low power portable applications. Nowadays researches have some solutions for this problem, such as temperature sensing with subthreshold MOSFETs and time-to-digital-converter-based CMOS smart temperature sensors [15].
Smart temperature sensors are needed because the systems in which they are being
Chapter 2 Temperature Sensing
Analog-to-Digital converter Temperature signal
(analog) Temperature signal
(digital)
Figure 2.1 Communication between a temperature sensor and a computer.
applied are getting more and more complex. The future trend for smart temperature sensors will be low power and low cost. Cheaper temperature sensors will also increase the number of applications.
Figure 2.2 shows the block diagram of conventional smart temperature sensor. In the figure, we know the temperature is sensed by two voltage references, PTAT and reference signal (such as bandgap reference or independent-of-absolute-temperature reference). So to improve the linearity of PTAT or to reduce the variance of bandgap reference (or independent-of-absolute-temperature reference) will make the sensor produce a more accurate temperature output. This thesis will force on the topic of how to improve these reference signals.
In order to attain our goal, knowing the principle of PTAT and bandgap reference will be necessary. In the next session, we will introduce how to produce both positive and negative temperature coefficients with bipolar transistors and MOSFETs. Then to combine pTC and nTC, we will get independent-of-absolute-temperature reference.
some improvements will be presented in the following chapters.
PTAT signal
Reference signal
Sigma-delta
modulator Interface bus
Decimation filter
+ control
Figure 2.2 The block diagram of conventional smart temperature sensor.
2.2 Temperature sensing
In this section, the temperature sensing method with both bipolar transistor and subthreshold MOSFETs will be described. In order to convert temperature to a digital value, both a well-defined temperature dependent signal and a temperature independent reference signal are required. There are two voltage that we interesting, one requires a positive temperature coefficient (pTC), and another requires a negative
Chapter 2 Temperature Sensing temperature coefficient (nTC). A quantity which requires a positive temperature coefficient is used to measure the temperature. If two quantities having opposite temperature coefficients (TCs) are added with proper weighting, the result displays a temperature-independent quantity which requires a zero TC. As follow, the two interesting quantities, one requires a negative temperature coefficient and another requires a positive one, are discussed.
(A) Bipolar transistor
(i) Negative temperature coefficient (nTC)
The base-emitter voltage of bipolar transistors exhibits a negative TC. For a bipolar device, temperature dependent. Rewrite Equation (2.1), we can get:
)
Where k is Boltzmann’s constant (1.3807⋅10−23J/K), T the absolute temperature (in Kelvin), and q the electron charge (1.6022⋅10−19C). Because we want to know the TC of the base-emitter voltage, we take the derivative of VBE with respect to T. We can get: mobility of minority carries and n is the intrinsic minority carries i concentration of silicon. The temperature dependence of these quantities is represented as u∝u0⋅Tm , where m is a constant about -3/2, and
Chapter 2 Temperature Sensing
β is a proportionality factor. We take the derivative of I with respect to T to S know its temperature characteristic. We can get:
kT
From Equation (2.7), the temperature coefficient of the base-emitter voltage at a given temperature T is gotten and it is clear negative. For example, with
mV
VBE ≈750 and T =300oK, ∂VBE/∂T ≈−1.5mV/oK. (ii) Positive temperature coefficient (pTC)
When two bipolar transistors operate at two different collector currents I1 and I2, the difference between their base-emitter voltage will be a proportional to absolute temperature quantity. Figure 2.2 is illustrates this idea. As follows, we describe in detail.
2
Chapter 2 Temperature Sensing
Q
Q11 QQ22
V VDDDD
II11 II22
+ + ΔΔVVBE BE -
-Figure 2.3 Generation of PTAT voltage with bipolar transistors.
If the two collector currents have this relation, I1 = pI2, where p is a constant.
From Equation (2.10), we get:
) ln( p q VBE = kT ⋅
Δ (2.11)
Taking the derivative of Equation (2.11) with respect to T, we get:
) ln( p q k T VBE
⋅
∂ = Δ
∂ (2.12)
According to Equation (2.12), we know clear the difference of the base-emitter voltage operated in different collector currents is a PTAT quantity.
(B) Subthreshold MOSFETs
(i) Negative temperature coefficient (nTC)
Previous research [16] has shown the gate-source voltage of an nMOS which operated in weak inversion has a negative temperature coefficient (nTC) and can be modeled as:
) 1 / ( )
( )
(T ≈V T0 +K ⋅ T T0−
VGSn GSn Gn (2.13)
Chapter 2 Temperature Sensing Where
OFFn THn
GSn Tn
Gn K V T V T V
K ≅ + ( 0)− ( 0)− (2.14) Where K is the temperature coefficient for nMOS threshold voltage and Tn T 0 is room temperature (=300 K). The gate-source voltage of a pMOS transistor can also been modeled as:
) 1 / ( )
( )
(T ≈V T0 +K ⋅ T T0−
VGSp GSp Gp (2.15)
Where
OFFp THp
GSp Tp
Gp K V T V T V
K ≅ + ( 0) − ( 0)− (2.16)
In order to verify the linearity of VGS operated in deep sub micron simulations based on both TSMC 0.13μm and 0.18μm technology are conduced, the gate-source voltage of an nMOS diode-connected transistor biased with a 100-nA current and the diode aspect ratio was set to 50/2 are simulated. The same simulations are also done with a pMOS diode-connected transistor. Figure 2.3 shows the simulation prototypes. The results are shown in Figure 2.4 and Figure 2.5. Basing on the results shown in Figure 2.4 and Figure 2.5, we can know that the linearity of nMOS gate-source voltage is better than pMOS source-gate voltage in both TSMC 0.18μm and 0.13μm CMOS technology. Table 2.1 shows the summary. So, if we want to get much better linearity in wider range, for the case, [-55, +170] C0 , the gate-source voltage of an nMOS transistor is the best choice.
nMOS pMOS
Figure 2.4 The simulation prototypes.
Chapter 2 Temperature Sensing
Temperature = −55 to 170 DEG−C
V(T) mV
Temperature VS. NMOS Gate−Source Voltage (TSMC 0.13um CMOS technology)
−40 −20 0 20 40 60 80 100 120 140 160
Temperature = −55 to 170 DEG−C
V(T) mV
Temperature VS. PMOS Gate−Source Voltage (TSMC 0.13um CMOS technology)
Simulation Result Linear Regression
Figure 2.5 The simulation results done in TSMC 0.13μm CMOS technology.
−40 −20 0 20 40 60 80 100 120 140 160
Temperature = −55 to 170 DEG−C
V(T) mV
Temperature VS. NMOS Gate−Source Voltage (TSMC 0.18um CMOS technology)
−40 −20 0 20 40 60 80 100 120 140 160
Temperature = −55 to 170 DEG−C
V(T) mV
Temperature VS. PMOS Gate−Source Voltage (TSMC 0.18um CMOS technology)
Simulation Result Linear Regression
Simulation Result Linear Regression
Figure 2.6 The simulation results done in TSMC 0.18μm CMOS technology.
Chapter 2 Temperature Sensing
Table 2.1 The linearity summary ofVGS.
R-square NMOS PMOS
TSMC 0.13μm CMOS technology 0.99976 0.99214
TSMC 0.18μm CMOS technology 0.99971 0.87315
Above all, a linear negative temperature coefficient voltage based on subthreshold MOSFETs has been presented.
(ii) Positive temperature coefficient (pTC)
The positive temperature coefficient quantity can be gotten in several kinds of MOS PTAT generators. The idea of MOS PTAT generators is like the bipolar transistor PTAT generators. When two MOSFETs operate at two different collector currents I1 and I2, the difference between their gate-source voltage will be a proportional to absolute temperature quantity. Figure 2.5 is illustrates this idea. As follows, we describe in detail.
According to the references [11] and [17], the drain currents of M1 and M2 are given by
Chapter 2 Temperature Sensing
Figure 2.7 Generation of PTAT voltage with subthreshold MOSFETs.
2
Because the source is connected to ground, Equations (2.17) and (2.18) can be derived to
Chapter 2 Temperature Sensing If M1 and M2 are matched, the PTAT voltage can be obtained from the difference in V and G1 VG2: derivative of Equation (2.26) with respect to T, we get:
) q are constants, we get:
)
According to Equation (2.28), we know clear the difference of the gate-source voltage operated in different drain currents is a PTAT quantity.
2.3 Summary
In this Chapter, the history of the temperature sensing is introduced. And we also describe the smart temperature sensor. As time goes by, much cheaper, low power, and high performance temperature sensors will be demanded for many applications. In the section 2.3, we describe how to generate two voltage references which one has a negative temperature coefficient and another is a proportional-to-absolute-temperature with both bipolar transistors and subthreshold MOSFETs. However, for the low power consideration, the bipolar transistor is more difficult to implement. Because the MOSFETs operated in the weak inversion region will have minimal power consumption, subthreshold MOSFETs are more suitable for the low power design.
But when we use subthreshold MOSFETs, we still have many challenges, such as [7]:
¾ The behaviors are more complicated for designers.
¾ Linearity is worse as process scaling down, particularly in high temperature.
Chapter 2 Temperature Sensing
¾ The performance is significantly affected by the variations of manufacture process.
These problems affect the performance significantly. Leakage current has become a serious problem in modern VLSI. It also affects the linearity of PTAT. As to smart temperature sensors, many dynamic offset-cancellation techniques can be used to enhance the performance, such as autozero techniques, chopper techniques, and nested chopper technique. However, for the linearity of PTAT or the variation of the independent-to-absolute-temperature (IOAT), we still can do more efforts to improve their performance.
In next Chapter, PTAT and IOAT of our design will be proposed. Some compensation methods to improve the linearity of PTAT and the variation of IOAT are presented. All the details will be described later. Based in this Chapter’s backgrounds, it is useful for us to get guidelines in our proposed design.
Chapter 3 CMOS Voltage References
CHAPTER
3
CMOS Voltage References
In this Chapter, both proportional-to-absolute-temperature (PTAT) and independent-of-absolute-temperature (IOAT) voltage references are redesigned by utilizing sub-threshold MOSFETs and temperature complementation technique to enhance the linearity and produce a more stable output. The propose design has extend the linear temperature rage of on-chip temperature sensor to -55°C to 170°C which provides a practical solution for modern system-on-chip’s thermal management systems. The design concept of proposed circuit will be described in this Chapter, and the experimental results are presented in Chapter 4.
3.1 Introduction
Various on-chip PTAT and IOAT references have been extensively implemented using parasite BJTs because of the ease of design. In some CMOS process, however, obtaining reliable BJTs is very costly and desirable performance from these parasitic devices is hard to expect. Also, the power consumption of the BJT based references is relatively high and an alternative approach is preferred, especially in low power applications.
Several PTAT and IOAT references based on the subthreshold MOSFETs have been studied and applied in low power low voltage design. As we mention in the Chapter 2, these circuits take the advantages of the MOS transistors operated in weak inversion region in the respects: the power consumption is made minimum due to the inherent low currents in this region. The power issues are overcome by taking the advantage of the MOS transistors operated in weak inversion region. Another issue is the accuracy.
For the PTAT references, linearity is the most important performance index we concern about. For the IOAT references, various must be as low as possible. Some
Chapter 3 CMOS Voltage References Our design concepts are described in detail as follow. And some design issues are also described in following sections.
3.2 CMOS Voltage References
In the Chapter 2, we know the gate-source voltage of an nMOS transistor operated in the weak inversion region has a linear negative temperature coefficient (nTC) and is suit for the design. So if we put PTAT core and the gate-source voltage which operated in weak inversion region (VGS) together, the IOAT voltage reference will be achieved by sum up both out. According to previous researches [8], a PTAT voltage reference circuit based on subthreshold MOSFETs has been developed. Figure 3.1 and figure 3.2 illustrate the condensed scheme of two low-voltage CMOS PTAT references [11]. In these circuits, M1 and M2 operate in weak inversion region, while transistors M3-M8 ensure the current ratio of M1-M2 pair. The transistor Mc which operated in weak inversion region compensates the leakage current to enhance the linearity of PTAT reference. Above all, the PTAT references will be written as:
P U
VPTAT = T ln (3.1) Where UT = k T /q and P is the aspect ratio of M6 to M3.
Figure 3.1 Low-voltage CMOS PTAT references (resistor-based).
Chapter 3 CMOS Voltage References
Figure 3.2 Low-voltage CMOS PTAT references (all-MOS-based).
The proposed circuitry architectures are shown in Fig. 3.3. The design concept is that using current mirror combines positive and negative temperature coefficients.
The first part circuit, M1-M8, Mc, and R1, will produce a PTAT voltage reference.
The slope of PTAT reference is determined by the aspect ratio of M6 and M3. And function of Mc is to compensate the leakage current. The quantity of the PTAT reference is as the same as equation (3.1). The second part of this circuit is made up of M9, R2, and a diode-connected transistor, Mn. A negative temperature coefficient will be produced in the gate-source voltage of Mn. The target of our design is to make two different temperature coefficient sum up, so we use a current mirror to make them sun up in current type. In this architecture, the IOAT voltage can be expressed as:
GSn
In order to get a zero temperature coefficient, we take the derivative of equation (3.2) with respect to temperature (T).
0 According to equations (3.1), (2.13), and (2.14), we can get:
Chapter 3 CMOS Voltage References
Figure 3.3 Resistor-based CMOS PTAT and IOAT references.
0
Where K is the temperature coefficient for nMOS threshold voltage and Tn T is 0 room temperature (=300 K). We rewrite equation as:
)]
Because the right side of equation (3.5) is constant, the ration
3 For the area consideration, we also develop all-MOS PTAT and IOAT voltage reference. Figure 3.4 shows the all-MOS architecture. R1 exchanges with M9, M10, and M11. R2 is exchanges with M14, M15, and M16. Both M11 and M12 are operated in strong inversion conduction region. In order to ensure each current ratio, we add another feedback path M17, M18, M19, and M20. Following equations (3.6), (3.7), (3.8), and (3.9), the details are described:
)
Chapter 3 CMOS Voltage References Figure 3.4 All-MOS CMOS PTAT and IOAT references.
T WhereVTO, β, n, and I stand for the threshold voltage, current factor, subthreshold S slope, and specific current, respectively, as defined in the EKV model [17]. We assume that there is no current the path 1 as shown as follow:
M2 Mc
Chapter 3 CMOS Voltage References
Table 3.1 Ratio List
NMOS PMOS
M7 M8 M10 M11 M3 M4 M5 M6 M9
1 1 N 1 1 1 1 P M
M15 M16 M18 M20 M12 M14 M17 M19
S 1 1 1 1 Q 1 1
The ratios of transistors are shown in Table 3.1and Table 3.2. According to the equations (3.6) to (3.9), we can write: Set the bodies of M10 and M11 connect to ground. Because the gates of M10 and M11 are connected together, we can get:
2
The same idea is applied in the right side of this circuitry.
12
Because the gates of M15 and M16 are connected together, we can get:
2
If all transistors are matched, equation (3.12) and (3.15) can be combined as:
Chapter 3 CMOS Voltage References
Simplify equation (3.16), we can get:
PTAT
K is a design parameter which composed of transistor ratios. Because M, N, S, and Q are ratios, they will make K more accurate when the manufacturing process varies.
In order to get a zero temperature coefficient, we take the derivative of equation (3.18) with respect to temperature (T).
0
According to equation (2.13) and (2.14), we can rewrite equation (3.20) as:
0
From equation (3.21), we can get the design constant K will be:
)] Above all, two PTAT and IOAT reference circuitry architectures are designed. The linearity of PTAT reference is compensated by the transistor, Mc. This compensation technique has been proposed before. Our design is to add a well-defined IOAT
Chapter 3 CMOS Voltage References reference and an efficient current compensation circuit. This Chapter has described the design concepts of two proposed circuits, one is resistor-based PTAT and IOAT reference circuitry architecture and another one is all-MOS-based PTAT and IOAT reference circuitry architecture.
Next session we will discuss the power-supply rejection ratio (PSRR) issue.
3.3 Power Supply Rejection Ratio (PSRR)
From section 3.2, we proposed two PTAT and IOAT reference circuitry architectures and some compensation technique. However, the power supply rejection ratio (PSRR) of these circuits deteriorates sharply in deep-submicro technology. So the analysis of PSRR is necessary for a reference circuit. The PSRR of PTAT reference has been discussed in previous research [18].
The small signal DC gain vptat vdd of this circuit can be derived from the low frequency small signal model shown in Fig. 3.6. Assume go <<gm for all transistors,
The small signal DC gain vptat vdd of this circuit can be derived from the low frequency small signal model shown in Fig. 3.6. Assume go <<gm for all transistors,