Chpater 2 Temperature Sensing
2.3 Summary
q are constants, we get:
)
According to Equation (2.28), we know clear the difference of the gate-source voltage operated in different drain currents is a PTAT quantity.
2.3 Summary
In this Chapter, the history of the temperature sensing is introduced. And we also describe the smart temperature sensor. As time goes by, much cheaper, low power, and high performance temperature sensors will be demanded for many applications. In the section 2.3, we describe how to generate two voltage references which one has a negative temperature coefficient and another is a proportional-to-absolute-temperature with both bipolar transistors and subthreshold MOSFETs. However, for the low power consideration, the bipolar transistor is more difficult to implement. Because the MOSFETs operated in the weak inversion region will have minimal power consumption, subthreshold MOSFETs are more suitable for the low power design.
But when we use subthreshold MOSFETs, we still have many challenges, such as [7]:
¾ The behaviors are more complicated for designers.
¾ Linearity is worse as process scaling down, particularly in high temperature.
Chapter 2 Temperature Sensing
¾ The performance is significantly affected by the variations of manufacture process.
These problems affect the performance significantly. Leakage current has become a serious problem in modern VLSI. It also affects the linearity of PTAT. As to smart temperature sensors, many dynamic offset-cancellation techniques can be used to enhance the performance, such as autozero techniques, chopper techniques, and nested chopper technique. However, for the linearity of PTAT or the variation of the independent-to-absolute-temperature (IOAT), we still can do more efforts to improve their performance.
In next Chapter, PTAT and IOAT of our design will be proposed. Some compensation methods to improve the linearity of PTAT and the variation of IOAT are presented. All the details will be described later. Based in this Chapter’s backgrounds, it is useful for us to get guidelines in our proposed design.
Chapter 3 CMOS Voltage References
CHAPTER
3
CMOS Voltage References
In this Chapter, both proportional-to-absolute-temperature (PTAT) and independent-of-absolute-temperature (IOAT) voltage references are redesigned by utilizing sub-threshold MOSFETs and temperature complementation technique to enhance the linearity and produce a more stable output. The propose design has extend the linear temperature rage of on-chip temperature sensor to -55°C to 170°C which provides a practical solution for modern system-on-chip’s thermal management systems. The design concept of proposed circuit will be described in this Chapter, and the experimental results are presented in Chapter 4.
3.1 Introduction
Various on-chip PTAT and IOAT references have been extensively implemented using parasite BJTs because of the ease of design. In some CMOS process, however, obtaining reliable BJTs is very costly and desirable performance from these parasitic devices is hard to expect. Also, the power consumption of the BJT based references is relatively high and an alternative approach is preferred, especially in low power applications.
Several PTAT and IOAT references based on the subthreshold MOSFETs have been studied and applied in low power low voltage design. As we mention in the Chapter 2, these circuits take the advantages of the MOS transistors operated in weak inversion region in the respects: the power consumption is made minimum due to the inherent low currents in this region. The power issues are overcome by taking the advantage of the MOS transistors operated in weak inversion region. Another issue is the accuracy.
For the PTAT references, linearity is the most important performance index we concern about. For the IOAT references, various must be as low as possible. Some
Chapter 3 CMOS Voltage References Our design concepts are described in detail as follow. And some design issues are also described in following sections.
3.2 CMOS Voltage References
In the Chapter 2, we know the gate-source voltage of an nMOS transistor operated in the weak inversion region has a linear negative temperature coefficient (nTC) and is suit for the design. So if we put PTAT core and the gate-source voltage which operated in weak inversion region (VGS) together, the IOAT voltage reference will be achieved by sum up both out. According to previous researches [8], a PTAT voltage reference circuit based on subthreshold MOSFETs has been developed. Figure 3.1 and figure 3.2 illustrate the condensed scheme of two low-voltage CMOS PTAT references [11]. In these circuits, M1 and M2 operate in weak inversion region, while transistors M3-M8 ensure the current ratio of M1-M2 pair. The transistor Mc which operated in weak inversion region compensates the leakage current to enhance the linearity of PTAT reference. Above all, the PTAT references will be written as:
P U
VPTAT = T ln (3.1) Where UT = k T /q and P is the aspect ratio of M6 to M3.
Figure 3.1 Low-voltage CMOS PTAT references (resistor-based).
Chapter 3 CMOS Voltage References
Figure 3.2 Low-voltage CMOS PTAT references (all-MOS-based).
The proposed circuitry architectures are shown in Fig. 3.3. The design concept is that using current mirror combines positive and negative temperature coefficients.
The first part circuit, M1-M8, Mc, and R1, will produce a PTAT voltage reference.
The slope of PTAT reference is determined by the aspect ratio of M6 and M3. And function of Mc is to compensate the leakage current. The quantity of the PTAT reference is as the same as equation (3.1). The second part of this circuit is made up of M9, R2, and a diode-connected transistor, Mn. A negative temperature coefficient will be produced in the gate-source voltage of Mn. The target of our design is to make two different temperature coefficient sum up, so we use a current mirror to make them sun up in current type. In this architecture, the IOAT voltage can be expressed as:
GSn
In order to get a zero temperature coefficient, we take the derivative of equation (3.2) with respect to temperature (T).
0 According to equations (3.1), (2.13), and (2.14), we can get:
Chapter 3 CMOS Voltage References
Figure 3.3 Resistor-based CMOS PTAT and IOAT references.
0
Where K is the temperature coefficient for nMOS threshold voltage and Tn T is 0 room temperature (=300 K). We rewrite equation as:
)]
Because the right side of equation (3.5) is constant, the ration
3 For the area consideration, we also develop all-MOS PTAT and IOAT voltage reference. Figure 3.4 shows the all-MOS architecture. R1 exchanges with M9, M10, and M11. R2 is exchanges with M14, M15, and M16. Both M11 and M12 are operated in strong inversion conduction region. In order to ensure each current ratio, we add another feedback path M17, M18, M19, and M20. Following equations (3.6), (3.7), (3.8), and (3.9), the details are described:
)
Chapter 3 CMOS Voltage References Figure 3.4 All-MOS CMOS PTAT and IOAT references.
T WhereVTO, β, n, and I stand for the threshold voltage, current factor, subthreshold S slope, and specific current, respectively, as defined in the EKV model [17]. We assume that there is no current the path 1 as shown as follow:
M2 Mc
Chapter 3 CMOS Voltage References
Table 3.1 Ratio List
NMOS PMOS
M7 M8 M10 M11 M3 M4 M5 M6 M9
1 1 N 1 1 1 1 P M
M15 M16 M18 M20 M12 M14 M17 M19
S 1 1 1 1 Q 1 1
The ratios of transistors are shown in Table 3.1and Table 3.2. According to the equations (3.6) to (3.9), we can write: Set the bodies of M10 and M11 connect to ground. Because the gates of M10 and M11 are connected together, we can get:
2
The same idea is applied in the right side of this circuitry.
12
Because the gates of M15 and M16 are connected together, we can get:
2
If all transistors are matched, equation (3.12) and (3.15) can be combined as:
Chapter 3 CMOS Voltage References
Simplify equation (3.16), we can get:
PTAT
K is a design parameter which composed of transistor ratios. Because M, N, S, and Q are ratios, they will make K more accurate when the manufacturing process varies.
In order to get a zero temperature coefficient, we take the derivative of equation (3.18) with respect to temperature (T).
0
According to equation (2.13) and (2.14), we can rewrite equation (3.20) as:
0
From equation (3.21), we can get the design constant K will be:
)] Above all, two PTAT and IOAT reference circuitry architectures are designed. The linearity of PTAT reference is compensated by the transistor, Mc. This compensation technique has been proposed before. Our design is to add a well-defined IOAT
Chapter 3 CMOS Voltage References reference and an efficient current compensation circuit. This Chapter has described the design concepts of two proposed circuits, one is resistor-based PTAT and IOAT reference circuitry architecture and another one is all-MOS-based PTAT and IOAT reference circuitry architecture.
Next session we will discuss the power-supply rejection ratio (PSRR) issue.
3.3 Power Supply Rejection Ratio (PSRR)
From section 3.2, we proposed two PTAT and IOAT reference circuitry architectures and some compensation technique. However, the power supply rejection ratio (PSRR) of these circuits deteriorates sharply in deep-submicro technology. So the analysis of PSRR is necessary for a reference circuit. The PSRR of PTAT reference has been discussed in previous research [18].
The small signal DC gain vptat vdd of this circuit can be derived from the low frequency small signal model shown in Fig. 3.6. Assume go <<gm for all transistors, then
Figure 3.6 Low-frequency small-signal model of the resistor-based PTAT reference shown in Fig. 3.3.
Chapter 3 CMOS Voltage References According to above result, we can know that gm2⋅go1 = gm1⋅go2 and
∞
+ →
PSRR for low frequency response.
After finishing the PSRR analysis of PTAT reference, we continue to discuss the PSRR analysis of IOAT reference in this circuit.
The small signal DC gain vioat vdd of this circuit can be derived from the low frequency small signal model shown in Fig. 3.7. Assume go <<gm for all transistors, then And the voltage of node x can be derived as:
8 1
Figure 3.7 Low-frequency small-signal model of the resistor-based IOAT reference shown in Fig. 3.3. become infinite, and the gain of the IOAT reference will be
Chapter 3 CMOS Voltage References
9 9
1 o
o
ioat g
A g
≈ + (3.29) Ifgo9 >>1, the gain of IOAT reference will be unity. So we can know the power supply rejection ratio (PSRR) of IOAT is dependent on the power supply rejection ratio (PSRR) of PTAT, and the gain of IOAT reference will been unity.
3.4 Summary
In this Chapter, we proposed two kinds of PTAT and IOAT reference circuitry architectures, which one is resistor-based and another one is all-MOS-based. The design concepts are well described in this Chapter. After we describe the circuits, the issue of power supply rejection ratio (PSRR) is also discussed. According to the results, we know the PSRR of PTAT can achieve to infinite. When this happened, the gain of IOAT reference will be unity. The much well the PSRR of PTAT, the much well the PSRR of IOAT is.
Next Chapter, the pre-layout simulation results will be shown. And the layout concept is also discussed. In the end, we will show the post-layout simulation results.
Chapter 4 Simulation and Experimental Results
CHAPTER
4
Simulation and Experimental Results
In this Chapter, the both pre-layout simulation and post-layout simulation are presented. We simulate the both resistor-based and all-MOS-based circuitry architectures with TSMC 0.18μm CMOS technology. Moreover, all-MOS-based circuitry architecture is further simulated with TSMC 0.13μm CMOS technology.
Then, the layout with TSMC 0.18μm CMOS technology is shown. Post-layout simulation is shown in the end of this Chapter.
4.1 Pre-layout Simulation
In Chapter 3, we proposed two new circuitry architectures, resistor-based and all–MOS based voltage generators and have been complete described. First, we simulate both the circuitry architectures with TSMC 0.18μm CMOS technology. The simulation results are shown in figure 4.1 and 4.2.
Figure 4.1 shows the PTAT voltage versus temperature for all-MOS-based and resistor-based PTAT references simulated in TSMC 0.18μm 1P6M standard CMOS technology. The simulation range is from -55°C to 170°C temperature range conduced for each circuit. The R-squares of resistor-based and all-MOS-based circuits are 0.99963 and 0.99968 respectively.
Figure 4.2 shows the PTAT voltage versus temperature for all-MOS-based IOAT reference simulated in TSMC 0.18μm 1P6M standard CMOS technology. The simulation range is from -55°C to 170°C for each circuit. The means of resistor-based and all-MOS-based circuits are 578.75mV and 514.94mV respectively. The variation
Chapter 4 Simulation and Experimental Results
−40 −20 0 20 40 60 80 100 120 140 160
50 60 70 80 90 100 110 120
Temperature = −55 to 170 DEG−C
V(T) mV
Temperature VS. PTAT Voltage (TSMC 0.18um CMOS technology)
All−MOS PTAT Simulation Result Resistor−based PTAT Simulation Result
Figure 4.1 The simulation result of PTAT references simulated in TSMC 0.18μm CMOS technology.
of the resistor-based circuit is about ±5mV. For the all-MOS-based circuit, the variation is about ±8mV.
The performance is summarized in Table 4.1. All the transistors aspects are shown in Table 4.2 and Table 4.3. According to the simulation results, we know the performance of resistor-based circuit is not better than the performance of all-MOS-based circuit. Moreover, for the area consideration, resistor-based circuit requires more area. This means the resistor-based circuitry architecture is not suited for the market demand. For the low cost consideration, we give up this architecture, and force on all-MOS-based circuitry architecture. The further simulation of all-MOS-based circuitry architecture is done with TSMC 0.13μm CMOS technology.
Table 4.1 Summary of TSMC 0.18μm CMOS technology simulation results TSMC 0.18μm PTAT Temperature
Coefficient (mV∕°C)
PTAT R-square
IOAT Mean (mV)
R-based 0.206 0.99963 514.94
All-MOS-based 0.276 0.99968 578.75
Chapter 4 Simulation and Experimental Results
−40 −20 0 20 40 60 80 100 120 140 160
520 530 540 550 560 570 580 590
Temperature = −55 to 170 [DEG−C]
Vref(T) [mV]
Temperature VS. Reference Voltage (TSMC 0.18um CMOS technology)
All−MOS IOAT Simulation Result Resistor−based IOAT Simulation Result
Figure 4.2 The simulation result of IOAT references simulated in TSMC 0.18μm CMOS technology.
Table 4.2 Sizing of resistor-based circuit in TSMC 0.18μm CMOS technology TSMC 0.18μm CMOS technology Model Name Aspect (W/L)
M1,M2,Mn NCH 1.2/0.36 m=40
M3,M4 PCH 0.6/2.8
M5 PCH 0.64/0.6 m=10
M6,M7,M8,M9 PCH 0.64/0.6
Mc NCH 1.2/0.36 m=150
X1 Rppo1rpo 2/3050
X2 Rppo1rpo 2/12800
Table 4.3 Aspect of all-MOS-based circuit in TSMC 0.18μm CMOS technology TSMC 0.18μm CMOS technology Model Name Aspect (W/L)
M1,M2,M13 NCH 1.2/0.36 m=20
M3,M4,M5,M9,M12,M14,M17,M19 PCH 0.44/0.6
M6 PCH 0.44/0.6 m=10
M7,M8,M10,M11,M15,M16,M18,M20 NCH 0.3/1.4
Mc NCH 0.3/1.4 m=132
Chapter 4 Simulation and Experimental Results Figure 4.3 shows the PTAT voltage versus temperature for all-MOS-based PTAT reference simulated in TSMC 0.13μm 1P8M standard CMOS technology. The simulation range is from -55°C to 170°C temperature range conduced for each circuit.
The R-squares of all-MOS-based circuits are 0.99969 and 0.99968.
Figure 4.4 shows the PTAT voltage versus temperature for all-MOS-based IOAT reference simulated in TSMC 0.13μm 1P8M standard CMOS technology. The simulation range is from -55°C to 170°C for each circuit. The means of all-MOS-based circuit is 417.26mV. Table 4.4 summarized this simulation. All the transistors aspects are shown in Table 4.5.
Table 4.4 Summary of TSMC 0.13μm CMOS technology simulation result
−40 −20 0 20 40 60 80 100 120 140 160
80 90 100 110 120 130
Temperature = −55 to 170 DEG−C
V(T) mV
Temperature VS. PTAT Voltage (TSMC 0.13um CMOS technology) SImulation Result
Linear Regression
Figure 4.3 The simulation result of PTAT reference simulated in TSMC 0.13μm CMOS technology.
PTAT
Temperature Coefficient (mV∕°C)
PTAT R-square
IOAT Mean (mV) All-MOS
(0.13μm) 0.267 0.99969 417.26
Chapter 4 Simulation and Experimental Results
−40 −20 0 20 40 60 80 100 120 140 160
416 416.5 417 417.5 418 418.5
Temperature = −55 to 170 [DEG−C]
Vref(T) [mV]
Temperature VS. Reference Voltage (TSMC 0.13um CMOS technology)
Figure 4.4 The simulation result of IOAT reference simulated in TSMC 0.13μm CMOS technology.
Table 4.5 Aspect of all-MOS-based circuit in TSMC 0.13μm CMOS technology TSMC 0.13μm CMOS technology Model Name Aspect (W/L)
M1,M2,M13 N 0.6/0.2 m=20
M3,M4,M5,M9,M12,M14,M17,M19 P 0.2/0.3
M6 P 0.2/0.3 m=10
M7,M8,M10,M11,M16,M18,M20 N 0.2/0.7
Mc N 0.6/0.18 m=132
M15 N 0.2/0.6
Above all, we know that all-MOS-based circuitry architecture takes advantage of both area and performance. Figure 4.5 shows both PTAT and IOAT voltage references together. The simulation results done with TSMC 0.18μm and 0.13μm CMOS technology have shown all-MOS-based circuit is well-work in this two kinds of technology. In next session, the layout in TSMC 0.18μm CMOS technology is presented. The layout concept is also described. The post-layout simulation is shown
Chapter 4 Simulation and Experimental Results
−40 −20 0 20 40 60 80 100 120 140 160
100 150 200 250 300 350 400
Temperature = −55 to 170 DEG−C
V(T) mV
Temperature VS. Reference Voltage (TSMC 0.13um CMOS technology)
Figure 4.5 The simulation results of both PTAT and IOAT references simulated in TSMC 0.13μm CMOS technology.
4.2 Layout Consideration and Post-layout Simulation
Before we start the layout implementation, the fine tuning concept has to be considered. The positive and negative temperature coefficients will be changed due to the change of current ratio after LPE (PEX). So the constant K which we introduce in Chapter 3 has to be modified after LPE (PEX). Our design flow is shown in figure 4.6.
Figure 4.7 shows the layout of all-MOS-based circuit which is designed with TSMC 0.18μm 1P6M CMOS technology. Because of fine tuning consideration, the length of M15 is designed to be easily changed in the layout. The supply voltage is 1.2v and area is about 42um 31× um(1260um ). Figure 4.8 and 4.9 show the post-layout 2 simulation of PTAT and IOAT references before fine tuning. Figure 4.10 and 4.11 show the post-layout simulation of PTAT and IOAT references after fine tuning. The post-layout simulation results compared with pre-layout simulation result are summarized in Table 4.6. In next session, we have a discussion on these simulation results and some considerations for applying our circuit in smart temperature sensors.
Chapter 4 Simulation and Experimental Results
Figure 4.6 The block diagram of our design flow.
Figure 4.7 The all-MOS-based layout of TSMC 0.18μm 1P6M CMOS technology.
Chapter 4 Simulation and Experimental Results
−40 −20 0 20 40 60 80 100 120 140 160
80 90 100 110 120 130
Temperature = −55 to 170 DEG−C
V(T) mV
Temperature VS. PTAT Voltage (TSMC 0.18um CMOS technology)
Post−sim Result Linear Regression
Figure 4.8 Post-layout simulation of PTAT reference before tuning.
−40 −20 0 20 40 60 80 100 120 140 160
423 424 425 426 427 428 429 430 431 432 433
Temperature = −55 to 170 [DEG−C]
Vref(T) [mV]
Temperature VS. Reference Voltage (TSMC 0.18um CMOS technology)
Figure 4.9 Post-layout simulation of IOAT reference before tuning.
Chapter 4 Simulation and Experimental Results
−40 −20 0 20 40 60 80 100 120 140 160
80 90 100 110 120 130
Temperature = −55 to 170 DEG−C
V(T) mV
Temperature VS. PTAT Voltage (TSMC 0.18um CMOS technology)
Sumulation Result Linear Regression
Figure 4.10 Post-layout simulation of PTAT reference after tuning.
−40 −20 0 20 40 60 80 100 120 140 160
421 421.5 422 422.5 423
Temperature = −55 to 170 [DEG−C]
Vref(T) [mV]
Temperature VS. Reference Voltage (TSMC 0.18um CMOS technology)
Chapter 4 Simulation and Experimental Results Table 4.6 Simulation summary of all-MOS-based circuitry architecture
4.3 Discussion
According to the post-layout simulation results, we know that the linearity of PTAT is almost the same with pre-layout simulation results. It means the compensation circuit (M17-M20, and Mc) is efficient. But the variation of IOAT is dependent on the process variance. In this work, we run the design flow to get the optimization of IOAT in the simulation level. The results also prove the improvement of IOAT by fine tuning.
In order to apply our work in smart temperature sensors, the level shift circuit has to design. When we take PTAT and IOAT as temperature signals, the first thing we have to do is to shift PTAT and IOAT in order to produce a cross point. The cross point will be defined as reference voltage at certain temperature. And if we subtract PTAT from this cross point, the difference will be taken as temperature difference signal. After the process of A/D converter, the digital value of temperature will be presented.
Above all, we can know how to improve the variation of IOAT and some design concepts for using this proposed circuit and some considerations for applying our circuit in smart temperature sensors. The conclusions and future works are discussed in next Chapter.
All-MOS-based (0.18μm)
Power (μW)
PTAT TC (mV∕°C)
PTAT R-square
IOAT Variance*
(mV) Pre-sim 18.4773 0.276 0.99968 87.12 Post-sim 27.8820 0.257 0.99787 142.49 Post-sim
(after tuning) 28.5227 0.264 0.99788 28.46
∑
−=[ ( () )2]12
*Variance y i mean
Chapter 5 Conclusions and Future Works
CHAPTER
5
Conclusions and Future Works
In the previous Chapter, simulation and experimental results have been shown.
Basing on those results, we make some conclusions of proposed design. Section 5.1 describes the conclusions of this thesis. The long term future works are also discussed in Section 5.2.
5.1 Conclusions
At the beginning, we review the temperature sensing methods, from mercury-in-glass thermometer to very low power and low cost smart temperature sensors. Then we discuss the advantages and disadvantages of both bipolar transistors and subthreshold MOSFETs for the low power design. Finally, we proposed new PTAT and IOAT reference circuitry architectures and show the simulation and experimental results.
In this thesis, -55 Co to 170 Co high linear voltage references circuitry for fully
In this thesis, -55 Co to 170 Co high linear voltage references circuitry for fully