Discussion

According to the post-layout simulation results, we know that the linearity of PTAT is almost the same with pre-layout simulation results. It means the compensation circuit (M17-M20, and Mc) is efficient. But the variation of IOAT is dependent on the process variance. In this work, we run the design flow to get the optimization of IOAT in the simulation level. The results also prove the improvement of IOAT by fine tuning.

In order to apply our work in smart temperature sensors, the level shift circuit has to design. When we take PTAT and IOAT as temperature signals, the first thing we have to do is to shift PTAT and IOAT in order to produce a cross point. The cross point will be defined as reference voltage at certain temperature. And if we subtract PTAT from this cross point, the difference will be taken as temperature difference signal. After the process of A/D converter, the digital value of temperature will be presented.

Above all, we can know how to improve the variation of IOAT and some design concepts for using this proposed circuit and some considerations for applying our circuit in smart temperature sensors. The conclusions and future works are discussed in next Chapter.

All-MOS-based (0.18μm)

Power (μW)

PTAT TC (mV∕°C)

PTAT R-square

IOAT Variance*

(mV) Pre-sim 18.4773 0.276 0.99968 87.12 Post-sim 27.8820 0.257 0.99787 142.49 Post-sim

(after tuning) 28.5227 0.264 0.99788 28.46

∑

=[ ( () )²]¹²

*Variance y i mean

Chapter 5 Conclusions and Future Works

CHAPTER

5

Conclusions and Future Works

In the previous Chapter, simulation and experimental results have been shown.

Basing on those results, we make some conclusions of proposed design. Section 5.1 describes the conclusions of this thesis. The long term future works are also discussed in Section 5.2.

5.1 Conclusions

At the beginning, we review the temperature sensing methods, from mercury-in-glass thermometer to very low power and low cost smart temperature sensors. Then we discuss the advantages and disadvantages of both bipolar transistors and subthreshold MOSFETs for the low power design. Finally, we proposed new PTAT and IOAT reference circuitry architectures and show the simulation and experimental results.

In this thesis, -55 C^o to 170 C^o high linear voltage references circuitry for fully integrated temperature sensor is designed and implemented in TSMC 0.13μm and 0.18μm CMOS technology. The proposed circuit utilized temperature complementation technique on PTAT and IOAT references. Base on the simulation results, the R-squares of both circuitries are better than 0.999 in a considerable wider temperature range from -55 C^o to 170 C^o as shown in the Chapter 4. Thus, a fully integrated temperature sensor with wider temperature range is designed and easily to integrate to modern system-on-chip designs with minimal efforts. In a world, we can make three points to conclude the thesis.

1. Propose the architecture based on subthreshold MOSFETS that produce both VPTAT and VREF. And the circuitry is working in both TSMC 0.18μm and 0.13μm CMOS technology.

2. Compensate the leakage current to get good linearity in high temperature.

Chapter 5 Conclusions and Future Works

Thermal Sensor

Interface Circuit

Thermal (Power) Control Mechanics

Thermal-Aware Power Management

Figure 5.1 The block diagram of the thermal-aware power management system.

3. A fully integrated temperature sensor with wider temperature range (-55~170 C^o ) is designed and easily to integrate to modern SOC designs with minimal efforts.

5.2 Future Works

Our long term goal is to implement the thermal-aware power management. The mid term goal is to structure a very low power and high performance smart temperature sensor. After this thesis’ work, the next step will be to research how to efficiently combine this PTAT and IOAT reference circuitry architecture with A/D converter.

However, some dynamic offset-cancellation techniques should be applied in order to maintain or even improve the performance. Finally, integrate with digital interface bus to get the digital output for the thermal-aware power management. Figure 5.1 shows the block diagram of this system.

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