Organization

In Chapter 2, the beginning is the overview of the analog-to-digital converters (ADC). After them, the quantization issues, oversampling and noise shaping are introduced. Then the performance metrics of sigma-delta modulators (SDM) end this chapter.

Chapter 3 describes the system level design considerations, including power supply and area issues of SDM, the topology and the important parameters selections of the SDM.

Chapter 4 discusses the topics of sub-circuits that will be used to realize an actual integrated circuit, which covers an operational amplifier (OPAMP), a comparator, switches and capacitors. The simulation results and device ratios are given at each section. The circuit level, transistor level, and layout level design will be described in sequence.

In chapter 5, the testing environment is present, including the instruments and external testing circuits on printed circuit board (PCB). Experimental results for a SDM, which is fabricated in a 0.18μm 1P6M1.8V standard CMOS with MIM process, will be plotted and summarized.

4

Chapter 2

Fundamentals of SDM

In this chapter, we begin with a brief overview of analog-digital converter (ADC) in the aspects of speed and architecture. Following by the classification of ADC, the oversampling and noise shaping is introduced and defined mathematically. The performance metrics of targeting ADC is then described in the end of this chapter.

2.1 A brief Introduction of ADC

The ADCs are fed a continuous-time analog signal to convert discrete-levels. To convert a continuous-time analog signal into a digital one, two operations should be performed. First, we discretize the continuous analog signal by sampling circuit. After sampling, the quantization is followed by digitizing the amplitude of the discrete signal, as shown in Figure 2.1.

Figure 2.1 Block diagram of an ADC

5

Analog-to-digital converters (ADCs) are employed in many electronic products, and it is important to make a choice between accuracy and speed for different applications. Several types of ADCs are developed for different speed and resolution requirements as depicted in Table 2.1 and Figure 2.2. In the ADCs, sigma-delta ADC is suitable for high resolution application in audio band.

Category Structure

Low-to-Medium Speed High Accuracy

Integrating ADC Sigma-Delta ADC Medium Speed

Medium Accuracy

Successive approximation ADC Algorithmic ADC

High Speed

Low-to-Medium Accuracy

Pipeline ADC Flash ADC

Table 2.1 Several kinds of ADC

The quantization stepΔ is called the least significant bit (LSB) of the ADC, as shown in Figure 2.2. It is often desirable to approximate when the data pass through the quantizer. The deviation of the real data from the approximate is called quantization error or quantization noise. And quantization error is less than a half of LSB.

If we assume that the quantization noise is white noise, it is uniformly distributed between

2

±

LSB

, as shown in Figure 2.3:

6

Figure 2.2 Transfer curve of quantizer

2

12 ⎟

⎠

⎜ ⎞

⎝

⎛ Δ

Δ 2

− Δ 2

Figure 2.3 Probability of quantization noise

Therefore, the power of the quantization error can be derived as:

2

2

( )

e q

12

P

^∞

e ρ e de

−∞

= ∫ = Δ

(2.1)

7

For a sinusoidal input signal, its maximum peak value without clipping is 2 2

N Δ , where N is the bit number of the quantizer. Thus the sinusoidal signal power equals

to:

From the equation, if the quantization noise can be modeled as a noise source, we can calculate the signal-noise-ratio (SNR) of an ideal N-bit ADC:

( )

10log 10log 10log 2 10log 6.02 1.76( ) 2

improvement of 6.02dB.

2.2 Oversampling and Noise Shaping

This section describes the principle and the theorem of the digital signal processing technique. We discuss oversampling first, which is followed by noise shaping.

8

2.2.1 Oversampling

For a signal bandwidth of

f , the Nyquist rate is 2

_B

f .A Nyquist ADC represent

_B that the sampling frequency of the ADC is at Nyquist rate. Moreover, an ADC with the oversampling technique can also improve the SNR. Its sampling rate

f is greater

_S more times than the signal bandwidth 2

f , and the oversampling ratio is defined

_B as

B s

f OSR f

= 2 , as Figure. 2.4, than the quantization power spectral density is reduced to:

Figure 2.4 Quantization noise in an oversampled converter Thus the peak SNR equals to:

2.2.2 Noise Shaping

With oversampling technique, the SNR increase 0.5 bit if sampling frequency is doubling. In addition to use oversampling technique to improve the performance of

9

ADCs, we can use noise shaping technique to further increase the SNR of the ADC, by applying a loop filter before the quantizer and introducing the feedback, a

noise-shaping modulator is built and new noise transfer function is realized.

A basic Sigma-Delta modulator is shown in Figure 2.5, it contains a loop filter, a quantizer and a feedback loop. If we assume that the DAC feedback gain is unity, than we can express the output of the SDM is:

( ) ( ) ( ) ( ) ( )

Y z = STF z X z + NTF z E z

(2.7)

Figure 2.5 A linear model of the sigma-delta modulator

Where STF(z) represents the signal transfer function and NTF(z) represents the noise transfer function. And the STF(z) and NTF(z) can be calculated as:

( ) ( ) ( ) ( ) 1 ( )

Y z H z STF z

X z H z

= =

+

(2.8)

( ) 1

( ) ( ) 1 ( ) NTF z Y z

E z H z

= =

+

(2.9)

10

With the large gain of H(z) at the frequency band, the STF(z) will approximate unity and the NTF(z) is going to approximate zero over the signal band. Thus the quantization noise is further attenuated than only by oversampling.

2.3 Performance Metrics

The performance metrics is shown at Figure 2.6 with a full scale sine wave to ADC, performed a Discrete Fourier Transform (DFT) to map into Fast Fourier Transform (FFT) spectrum. Some of the performance metrics are listed below, while the unit is

“dB”.

1. SFDR: the abbreviation of “spurious free dynamic range”. Difference between the fundamental bin and the highest harmonic bin.

2. SNR: the abbreviation of “signal to noise ratio”. Fundamental power divided by the power of the bins in the FFT other than DC, fundamental and first N harmonic bins.

3. SNDR: the abbreviation of “signal to noise and distortion ratio”. Fundamental power divided by the power of the bins in the FFT other than DC and fundamental bins.

4. ENOB: the abbreviation of “effective number of bits”, which is defined at Equation 2.10:

1.76 ( ) 6.02

ENOB = SNDR − dB

(2.10)

11

5. DR: the abbreviation of “dynamic range”. Effective input range when SNR remains positive.

Figure 2.6 Performance metrics

0 1000 2000 3000 4000 5000 6000 7000

-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0

Frequency [Hz]

Output spectrum [dB]

Fundamental pin

Harmonic pin

SFDR

Frequency [Hz]

Output Spectrum [dB]

12

Chapter 3

System Level Design Considerations

This chapter discusses actual SDM design considerations. First, we review previous researches fabricated in 0.18um technology for audio band applications. Some researches consider power issue and one of them focus on area. And then the system parameter considerations are discussed in Section 3.2. Several non-idealities such as gain requirement, settling of opamp and capacitor sizing are discussed in the end of the chapter.

3.1 Area Issues in SDM

In order to realize an area-efficient switched-capacitor circuit, capacitors with high capacitance per unit area are required. An opportunity to achieve the condition is using MOSFET capacitances (MOSACAPs). But MOSACAPs should only be used when high linearity is not required [4]. So we decide to adopt metal-insulator-metal capacitors (MIMCAPs) for the switched-capacitor circuit. And we optimize the capacitor value used in the circuit by simulation to reduce the area. The area of my design is proven to be as large as the SDM of Ref [4] after layout. The process will be shown later.

13

Table 3.1 Comparison of previous researches fabricated in 0.18um technology

3.2 Supply Voltage Issue in SDM

Supply voltage in modern CMOS process is continuously decreasing .Thus the switch-driving problem is brought for switched capacitor (SC) circuits at low supply voltage. When Supply voltage (VDD) is lower than the sum of the threshold voltage of n-and p-MOSFETs (Vtn+Vtp), the circuit may not work correctly as shown in Fig.3.1.

Vin

both on

both off

Small headroom No headroom

Vin Vout

Problem of CMOS s witch

Vtn

Vtn

Vtp Vtp

PMOS on

PMOS on

NMOS on NMOS on

VDD

VDD VDD

VDD

Fig.3.1. Switch-driving problem in low supply voltage.

14

A switched-OPamp technique combined with a dc level shift has been proven to allow proper operation under low VDD conditions (1v,0.7v,0.65v), thus lower the power consumption[4][6][7]; A new fully differential CMOS class AB Operational Amplifier with a charge-pump is proposed to avoid the switch-driving problem [5].Thus it will increase the complexity when designing circuit at low supply voltage.

So we make the supply voltage a bit higher than Vtn+Vtp to reduce the complexity when designing circuit. Finally, we will show that the overall power consumption of the SDM is acceptable.

3.3 System Parameter Considerations

The design goal is to design a low power consumption and small-area SDM while the target SNR (DR) is high enough for hearing-aid applications. There are many trade-offs when designing a low-power and small-area SDM, thus three steps are followed in this section to determine the system parameters of the SDM, topology decision, architecture selection and coefficient decision, respectively.

3.3.1 Design target of SDM

First, we decide the specification of SDM in three aspects: supply voltage, signal- bandwidth and resolution.

1. We design a Sigma-Delta modulator in hearing aid operating at 1V supply voltage with zinc air battery (open circuit voltage 1~1.2V).

2. Although normal-hearing humans can detect approximately from about 20Hz to about 20kHz, hearing aids have been limited to a spectral response of 6kHz. [8] [9]

15

Speech articulation range is 200Hz to 6kHz, and considering some consonants in high frequency, we choose the signal bandwidth of Sigma-Delta modulator is 8kHz.

3. 9bit resolution (SNDR =55dB) of Sigma-Delta modulator is enough to compensate 41~55dB hearing loss for moderately hearing-impaired.

3.3.2 Topology Decision

The first step to design a sigma-delta modulator is to determine the system level parameters based on the modulator specifications to lower the power consumption.

The power consumption formula:

^{Power = × = × × I V f c} ( ^Vdd )

² (3.1)

Therefore, we must choose the supply voltage we used in this thesis. The basic principle is to reduce power, and in TSMC 0.18um technology, vtn+vtp is about 0.9v, so we choose supply voltage is 1v for our design.

The system-level parameters include oversampling ratio (OSR), the loop filter order (L), the number of the quantizer level (N).

First we decide N. Because the power consumption of the quantizer increases proportionally with N, and a multi-bit quantizer have more complicated DAC structure, thus will make whole circuit more complicated and consume more power, so for a low-power SDM design, the number of the quantizer should be minimized, so we choose N=1.

16

Second, because single-stage structure has more advantages on low-power design, for example simple analog circuit, good circuit mismatch characteristic, so single stage architecture is selected.

Therefore, for a target SNR, the oversampling ratio (OSR) can be made after deciding the loop filter order n:

( )

^{2 1}

A higher loop filler order n have more switches and integrators, lower sampling frequency and higher order of n has more stability issue. So we have to make a trade-off between the order and the sampling frequency. If we compare different order N by simple estimation (We suppose the power consumption of OP is proportional to unity-gain frequency), we can know that for loop filter order 2and 3, we can have similar power consumption as Table 3.2 shows.

80

power cons umption (uW)

5

OSR for target resolution 9bit

power cons umption (uW)

5

OSR for target resolution 9bit Loop filter

order (n)

Table 3.2 power consumption of OP in 4 kinds of loop filter order

From the table above, we choose loop filter order n=2, OSR=64 for power and area efficiency to achieve our target SNR.

17

3.3.3 Architecture Selection

The most general single stage topology in the SDM design is the CIFB architecture, and it is shown at Figure 3.2:

Figure 3.2 Chain of Integrators with distributed feedback(CIFB)

The output of integrator one and two are:

( ) ^{( 1 ) ( )}

The outputs depend on the input signal. Thus the disadvantage of CIFB is that it needs large signal swing at the output of the integrators and may consume more power.

The advantage is that it is low sensitivity to component variations [14]

Another single stage topology in the SDM design is the CIFF architecture, and it is shown at Figure 3.3:

18

Figure 3.3 Chain of integrators with weighted feed-forward summation. (CIFF)

The output of integrator one and two are:

( ) ^Z

The outputs are independent of the input signal. Thus the advantage of CIFF is that it reduces output swing which does not depend on the input signal and may operate with low voltage. The disadvantage is that the out-of-band frequencies due to high frequency boost can overload the quantizer and drive the modulator into instability.

[14]

Because We have made the supply voltage at 1 volt, the advantage of CIFF is not apparent in my design. Thus we choose the CIFB structure for system stability and we should care the issue of output swing.

19

3.3.4 Coefficient Decision

In a general structure of CIFB sigma-delta modulator like Figure 3.4, the modulator contains five coefficients: two integrator gain (b1, b2) and two feedback factor ( a1, a2):

Figure 3.4 Parameters of second order CIFB Sigma-Delta modulator topology

We can use Matlab and the toolbox to get the parameters [3]. The sigma-delta modulator is OSR=64, loop filter order=2, Cascade-of-integrators feedback form (CIFB) structure, we can get:

a1 =0.2636 b1= 0.2636 a2= 0.2249 b2=0.3254   

The parameters should be ratio of unit capacitor. Thus we round the parameters to simple ratios when considering layout of capacitors. The unit capacitor is 0.1pf which is the smallest capacitor value in my design. Because of a1 is equal to b1, we simulate 8 times to get the best performance with the parameters after rounding. It is shown in Table.3.3

20

Parameters SFDR (dB)

a1 =0.2636 b1= 0.2636

3.4 Non-idealities Considerations

There are some non-ideal effects in analog circuit design and it is unavoidable, so we must evaluate the non-ideal effect to make our designs meet the desired margin.

3.4.1 Gain requirement

21

However, the gain of OP cannot be infinite in circuit design, when a finite gain is A in an OP, the transfer function will become:

1

Figure 3.5 a switched-capacitance circuit in SDM

A finite gain of OP means that the pole of the H(Z) will depart from unit circle, and when the distance of the zero exceed about

1 begins to degrade, so the lower limit of A is recommended to be 30 dB or more[3].

And after simulation, OP dc gain 50dB is chosen for 2bit resolution margin for the target when per-layout simulation.

3.4.2 Capacitor Sizing

The input-referred thermal noise of the integrator is:

s

n

C

V

² =

KT

, (3.9)

22

Cs is sampling capacitor of the integrator.

With an oversampling ratio of OSR, the in-band KT/C noise:

And if for a full scale input amplitude, the in-band noise power must be at least 78dB below the signal power [3]:

2

With OSR=64, VDD=1V, SNR=72dB,

we can get Cs is about 8.2fF, but after simulation it only reach SFDR 50dB.

Thus we simulate with Cs from 8.2fF to 1pF to get the proper Cs as shown in Figure 3.6.

From Fig.3.5, we find that Cs should be larger than 0.1pf to satisfy the goal.

We set the Cs = 0.2pF => SFDR =72.6dB, SNDR=67.7dB

23

Figure 3.6 SFDR versus Cs1 with parameters after rounding

The KT/C noise at the input of the second integrator is shaped by the first-order noise shaping, so that Cs2 can be scaled down since its effect of thermal noise is fewer. In this SDM system, we choose CS2=0.1pF.

3.4.3 Slew rate of the OP

In a switched-capacitance circuit, the loop filter can be separately into two parts, namely the sampling period and the integration period, as shown at Figure 3.7:

To estimate the slew current, the largest quantity of charge may need to be transferred from the sampling capacitor Cs to the integrating capacitors is CsVDD.

We allocate 25% of a half clock period for slewing [3]

Cs1(pF) SFDR

(dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

50 55 60 65 70 75

0.2pf

24

the slew current is :

The slew rate is about 2.7V/us when simulation.

      Figure 3.7 Sampling and integration period of a loop filter  

uA fCsVdd

I

=8 =4.8

25

Chapter 4

Circuit Implementation of SDM

The proposed sigma-delta modulator has been fabricated in TSMC 0.18um CMOS standard process. The circuitry is operating at a supply voltage of 1 volt. The

sub-circuitry of each component which includes OP, comparator, clock generator and switched capacitor circuit is described in Section 4.1. In Section 4.2, the simulation results of sub-blocks and whole SDM are presented. In Section 4.3, the final layout design of proposed SDM is then described.

4.1 Circuit Level Design

The detail schematic design and system considerations have been present in earlier this thesis. Implementation of these principles to an actually monolithic chip is our objective here. Let us recall all of building blocks of SDM, they are a loop filter, a quantizer, switches and capacitors. We should notice that a loop filter can be carried out by a differential SC integrator, and the sample and hold circuit can be omitted. In addition to this, a one-bit ADC is used be to be a quantizer for SDM. Therefore the SDM can be divided into two parts, which consist of sub-circuits, and we can summarize them in Table 4.1 below.

A fully experimental SDM circuit is shown in Figure 4.1 at next page, input signal Vi and output signal q are illustrated.

26

Schematic Building block Sub-circuit Section OPAMP 4.2.1 Loop

filter

Differential

SC Integrator

Switches & capacitors

4.2.2

Quantizer 1-bit ADC Comparator 4.2.3

Table 4.1 Organization of SDM

+

OPAMP1 OPAMP2 Com parator

Figure 4.1 Circuit level of SDM

27

4.2 Transistor Level Design

This section described the elaboration of sub-circuits that will be used to realize an actual integrated circuit, which covers an operational amplifier (OPAMP), a comparator, switches and capacitors. The simulation results and device ratios are given at each section.

4.2.1 Differential OPAMP

Utilizing switched-capacitor technology and an operational amplifier (OPAMP) to realize a loop filter in a SDM is a common circuitry for low speed and high accuracy applications. It is clearly that, however, the performance of this loop filter dominates dynamic specifications of a SDM. Designing a low power OPAMP to satisfy our goal is the main purpose in this section. The OPAMP is shown at Figure 4.2. In addition to a main circuit, a bias circuit and a common mode feedback circuit (CMFB) will be discussed.

1st stage 2nd stage

Av1= gm₁[r_o6+gm₆r_o6(r_o2〃r_o4)]

Figure 4.2 Fully differential OPAMP

28

The OPAMP circuit consists of eleven transistors, from M1 to M15. The first stage consists of a PMOS input pair M1, M2 and a folded load consisting of four equal sized PMOS transistors M8-M11. A differential signal sees a high load impedance since the gm’s of the transistors M10 and M11 are cancelled by the gm’s of the cross coupled devices.The second stage is output stage which consists of the common source connected gain transistors M14 and M15 and the current source loads M12 and M13. Mc1 and Mc2 are used as resistors with the compensating capacitor C1, C2 to compensate the phase margin. The transistor size summary of the first OP is shown at Table 4.2:

Transistor W L M

M1,M2 0.4 0.4 4

M3 0.4 0.4 8

M4,M5 0.8 0.4 2

M6,M7 0.4 0.4 2

M8,M9,M10,M11 1 0.4 2

M12,M13 2 0.4 1

M14,M15 1.6 0.4 4

Mc1,Mc2 0.4 0.4 2

Table 4.2 Device ratio summary of first OP The decision of the size is based on the following principles:

(1) The current density is matched.

(2) Tune M1, M2 to meet the gm and Fu specification.

(3) Tune M3 to supply the current for M1, M2.

(4) Tune M8~M11 to make a high load impedance for differential signal.

(5) Tune M12~M5 that the output stage has a output closed to 0.5VDD, and the gain of the whole OP exceed 50dB.

(6) Tune Mc1,Mc2 to make the phase margin exceed 60°

29

The performance summary of the first OP is listed at Table 4.3:

Specification Result

DC gain 50.8dB

Phase margin 71.4°

Slew rate 2.68V/us

ICMR (input common mode range) 960mv

Output Swing -950mv~950mv

PSRR 97dB CMRR 68dB

GB 7.1MHz Power 20.2uW

Table 4.3 Summary of first OP simulation results

The comparison of the two OP for a 1.6pf loading capacitance is listed at Table 4.4, and the frequency response of the first OP is shown at Figure 4.7:

Gain(dB) GBW Total Power

OP1 50.8dB 7.1MHz 20.2uW

OP2 50.6dB 5MHz 8.8uW Table 4.4 Performance comparison of the two OP

30

Figure 4.3 Frequency Response of first OP

Because of the differential architecture of the OP, we must have a CMFB circuit which is used because it is the most power-efficient. as shown at Figure 4.4. In the CMFB circuit, Vcmo is set to 0.5v and only the switch connect to CMFB use CMOS switch, other switches is PMOS switch only.

C1a C1b

C2a C2b

CM

Vo1 Vo2

Vcmo Vcmo

Vcmo Vcmo

31

Figure 4.4 Dynamic CMFB circuit

The device ratio summary we used in CMFB circuit is listed at Table 4.4, and the

The device ratio summary we used in CMFB circuit is listed at Table 4.4, and the

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