Chapter 4 Circuit Implementation of SDM…
4.4 Layout Level Design
A physical design in the context of integrated circuit is referred to as layout. Effects of parasitic components and mismatching will damage the performance of the chip, so layouts must be considered heavily in design process. Several principles of layout must be obeyed to minimize cross-talk, mismatches include (a) multi-finger transistors (b) symmetry (c) dummy cell (d) common centroid.
The diagram of layouts are shown at Figure 4.13, there are eighteen I/O pads, including a pair of differential inputs, a pair of modulator outputs, a input clock, three VDD and GND for analog and digital circuit, a pair of clock for measurement, others for reference voltages. The I/O pad description is listed at Table 4.7. This circuit is fabricated in a TSMC 0.18 um CMOS Mixed Signal RF General Purpose Standard Process FSG Al 1P6M process. The chip area is 0.349mm2 including I/O pads and
102 103 104 105 106
-120 -100 -80 -60 -40 -20 0
Frequency [Hz]
Output Spectrum [dB]
Input signal =4kHz SFDR=73B SNDR=68dB
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0.058mm2 for the core area.
Clock 1st stage
2nd stage
comparator
Figure 4.13 Diagram of the layout
The package type of proposed chip is S/B type 18 pin, as shown in Figure 4.14.
Figure 4.14 Diagram of the18 pin DIP package
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Pin Name Description
1 CLK Input clock signal
2 CK1d Output clock for measurement
3 CK2 Output clock for measuremen
4 Agrgnd Ground for analog circuit guard ring
5 Vbias Voltage for bias circuit
6 Vcmo Reference voltage
7 Vcmi Reference voltage
8 Vrefn Reference voltage
9 Vrefp Reference voltage
10 Vin1 Differential input signal
11 Vin2 Differential input signal
12 Agnd Ground for analog circuit
13 Avdd VDD for analog circuit
14 Vout1 Differentail output signal
15 Vout2 Differentail output signal
16 Dgrgnd Ground for digital circuit guard ring
17 Dgnd Ground for digital circuit
18 Dvdd VDD for digital circuit
Table 4.7 Pin Assignments of whole chip
The 8192-point FFT of the post simulation result is shown as Figure 4.15 with the input frequency of 4k and1k and the input amplitude is -6dB of full scale.
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Figure 4.15a 8192-point FFT of the post-simulation result
Figure 4.15b 8192-point FFT of the post-simulation result
102 103 104 105 106
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0
Input signal =1kHz SFDR=69dB SNDR=63dB Frequency [Hz]
Output Spectrum [dB]
102 103 104 105 106
-120 -100 -80 -60 -40 -20 0
Output Spectrum [dB]
Frequency [Hz]
Input signal =4kHz SFDR=72dB SNDR=66dB
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Because of the possibly process variation, we simulate the SNR results for corners, the corner simulation results are summarized at Table 4.8.
TT FF SS
SFDR (dB) 72 69 69
SNDR (dB) 66 64 63
Table 4.8 Corner of post-layout simualtion
The dynamic range is 74dB as Figure 4.16 shows.
-80 -70 -60 -50 -40 -30 -20 -10 0
0 10 20 30 40 50 60 70 80
Figure 4.16 Dynamic range of the SDM Vin/Vref (dB)
SNDR (dB)
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Finally, the performance summary of the proposed SDM is listed at Table 4.9, the simulation result shows that the peak SNDR is 66dB for a 4 KHz signal bandwidth and sampling frequency of 1MHz. The difference in SNDR between Pre-Sim. and Post-Sim. is due to the parasitic capacitor between the input and output of OPamp which changes the integrator gain (b1, b2) majorly. The average power consumption is 48uW, core area is 0.058mm2.
Specification Pre-Sim. Post-Sim.
Supply voltage 1v
Signal bandwidth (Hz) 8k Clock frequency (Hz) 1M
SFDR (dB) 73 72
SNDR (dB) 68 66
Chip area 638um*548um
Power (uW) 45.5 48
Table 4.9 Summary of the proposed SDM
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Chapter 5
Testing Setup and Experimental Results
A testing setup for fabricated chip is presented in this chapter. And a costumed designed printed circuit board (PCB) is designed and fabricated to integrate the targeting prototype chip in order to measure the performance metrics of proposed design. Following by the setup for measurement, the experimental results is presented and discussed. And the performance summary is summarized in the end of this chapter.
5.1 Testing Environment Setup
The testing environment setup is shown as Figure 5.1. It includes a printed circuit board (PCB) including a device under test (DUT) board, a logic analyzer (Agilent 16902A), an audio-band function generator (Stanford Research DS360), a power supply (Keithley 2400), a clock function generator (HP HEWLETT PACKARD 33120A) and a PC to analyze the output bit stream of proposed modulator.
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Power supplyKeithley 2400
Clock generator HP 33120A
Signal Generator Stanford Research
DS360
PCB
Logic analyzer Agilent 16902A
BUS
PC (Matlab)
Figure5.1 experimental test chip
As shown in Figure 5.1, the input signal is generated by audio-band function generator, and the digital output is fed to the logic analyzer, then load to PC for MATLAB simulation. A PCB board combines the clock generator and a device under test (DUT) to measure the chip. The photograph of the measurement environment is shown at Figure 5.2.
Figure 5.2 Photograph of the measurement environment
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5.2 Problem of Chips
We encountered a problem when measuring the chips. The output of clock
generator was connected to the output pads to observe if the clocks are nonoverlapped.
It is shown at Figure 5.3. The capacitors of output pads increase the loading of clock generator so that the clock generator doesn’t work as simulation. After discussing with my adviser, we cut the metals between output pads and clock generator. Thus the clock generator works normally and we measured the chips again. The die photos and are shown at Figure 5.4 and Figure 5.5
46 Clock generator
Figure 5.3 The problem of clock generator
Figure 5.4 The die photo before modifying
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Figure 5.5 The die photo after modifying
5.3 Performance Evaluations
The performances of SDM in this work were assessed by input it with a fully sinusoidal signal 1kHz and acquired the digital output from a logic analyzer, after then transferring them into PC. Subsequent analysis contained digital filtering and frequency domain examination is performed by program MATLAB.
The active area of experimental SDM is 0.058mm2 including output buffers, sub-circuits for verification and bias circuits. This proposed SDM based on second-order structure are operating at OSR=64, clock rate is 1MHz, and the corresponding bandwidth is 8kHz. The time domain analysis is measured by an oscilloscope (Agilent 54641D) as well as the differential inputs and outputs of this prototype are shown in Figure 5.6, simultaneously, these waveforms without decimation filter and calculated by FFT with Hanning window are shown in Figure 5.7. The bit-stream of SDM outputs drive a logic analyzer (Agilent 16902A)
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and are evaluated digital signal processing (DSP) by MATLAB, the measured
performance SNDR is 58 dB and SFDR is 66 dB by 8192 FFT with Hanning window.
The log scale plot and linear scale plot are sequentially shown in Figure 5.8 and Figure 5.9.The static and dynamic performances of this SDM are summarized in Table 5.1.
Figure 5.6 Measured output waveforms of the SDM
Figure 5.7 Measured output spectrum of the SDM
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Figure 5.8 linear scale PSD of measurement
Figure 5.9 log scale PSD of measurement
102 103 104 105 106
Input signal =1kHz SFDR=66B SNDR=58dB Frequency [Hz]
Output Spectrum [dB]
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Architechture Second order SDM
Process TSMC 0.18μm 1P6M1.8V standard CMOS with MIM process
Actice rea 0.058mm2
Sampling rate 1MHz
OSR 64
Input bandwidth 8kHZ
Peak SFDR 66dB
Peak SNDR 58dB
Power dissapation 53uW
Table 5.1 Performance Summary
5.4 Comparison
The comparison of this work and previous researches are listed at Table 5.2 , in order to compare the design result, we define the figure-of-merit as:
The FOM comparison shows that the proposed SDM is low power consumption and small chip area when comparing to other researches .
FOM=
power * area bandwidth
* SNDR
[4]
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Table 5.2 comparison with other SDM in 0.18um
5.5 Summary
The circuit present in this thesis is implemented by design considerations described in Chapter 3 and circuit design implementation in Chapter 4.This work emphasized the design flow for low-power and small-area design and the stability.
The partial difference in SNDR between Post-Sim. and measurement is due to the loading of package which induces the second order harmonic tone in-band.
The target resolution of this SDM is 9 bits (55 dB), and the actual one when measuring is 9.5 bit (58 dB). It achieves the performance which we expected.
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Chapter 6 Conclusions
This thesis describes the design criteria of a second-order sigma-delta modulator (SDM) with CIFB structure for audio-band applications. The simple switched- capacitor circuit with a low power OPamp and small capacitor value makes the whole power consumption of SDM is 53uW and the active area is 0.058mm2.
The Sigma-Delta ADC which has high resolution 、high stability and low cost is employed in the hearing aids for moderately hearing-impaired. Using 0.18um CMOS technology, this modulator achieves SNDR of 58dB with 8kHz bandwidth. The measured SNDR achieves the target (SNDR 55dB).
The power consumption of SDM is 53uW which doesn’t dominate the power consumption of hearing-aids. We might decrease the power consumption of the SDM if it is for other applications which need low power.
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