Slew rate of the OP

In a switched-capacitance circuit, the loop filter can be separately into two parts, namely the sampling period and the integration period, as shown at Figure 3.7:

To estimate the slew current, the largest quantity of charge may need to be transferred from the sampling capacitor Cs to the integrating capacitors is CsVDD.

We allocate 25% of a half clock period for slewing [3]

Cs1(pF) SFDR

(dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

50 55 60 65 70 75

0.2pf

24

the slew current is :

The slew rate is about 2.7V/us when simulation.

      Figure 3.7 Sampling and integration period of a loop filter  

uA fCsVdd

I

=8 =4.8

25

Chapter 4

Circuit Implementation of SDM

The proposed sigma-delta modulator has been fabricated in TSMC 0.18um CMOS standard process. The circuitry is operating at a supply voltage of 1 volt. The

sub-circuitry of each component which includes OP, comparator, clock generator and switched capacitor circuit is described in Section 4.1. In Section 4.2, the simulation results of sub-blocks and whole SDM are presented. In Section 4.3, the final layout design of proposed SDM is then described.

4.1 Circuit Level Design

The detail schematic design and system considerations have been present in earlier this thesis. Implementation of these principles to an actually monolithic chip is our objective here. Let us recall all of building blocks of SDM, they are a loop filter, a quantizer, switches and capacitors. We should notice that a loop filter can be carried out by a differential SC integrator, and the sample and hold circuit can be omitted. In addition to this, a one-bit ADC is used be to be a quantizer for SDM. Therefore the SDM can be divided into two parts, which consist of sub-circuits, and we can summarize them in Table 4.1 below.

A fully experimental SDM circuit is shown in Figure 4.1 at next page, input signal Vi and output signal q are illustrated.

26

Schematic Building block Sub-circuit Section OPAMP 4.2.1 Loop

filter

Differential

SC Integrator

Switches & capacitors

4.2.2

Quantizer 1-bit ADC Comparator 4.2.3

Table 4.1 Organization of SDM

+

OPAMP1 OPAMP2 Com parator

Figure 4.1 Circuit level of SDM

27

4.2 Transistor Level Design

This section described the elaboration of sub-circuits that will be used to realize an actual integrated circuit, which covers an operational amplifier (OPAMP), a comparator, switches and capacitors. The simulation results and device ratios are given at each section.

4.2.1 Differential OPAMP

Utilizing switched-capacitor technology and an operational amplifier (OPAMP) to realize a loop filter in a SDM is a common circuitry for low speed and high accuracy applications. It is clearly that, however, the performance of this loop filter dominates dynamic specifications of a SDM. Designing a low power OPAMP to satisfy our goal is the main purpose in this section. The OPAMP is shown at Figure 4.2. In addition to a main circuit, a bias circuit and a common mode feedback circuit (CMFB) will be discussed.

1st stage 2nd stage

Av1= gm₁[r_o6+gm₆r_o6(r_o2〃r_o4)]

Figure 4.2 Fully differential OPAMP

28

The OPAMP circuit consists of eleven transistors, from M1 to M15. The first stage consists of a PMOS input pair M1, M2 and a folded load consisting of four equal sized PMOS transistors M8-M11. A differential signal sees a high load impedance since the gm’s of the transistors M10 and M11 are cancelled by the gm’s of the cross coupled devices.The second stage is output stage which consists of the common source connected gain transistors M14 and M15 and the current source loads M12 and M13. Mc1 and Mc2 are used as resistors with the compensating capacitor C1, C2 to compensate the phase margin. The transistor size summary of the first OP is shown at Table 4.2:

Transistor W L M

M1,M2 0.4 0.4 4

M3 0.4 0.4 8

M4,M5 0.8 0.4 2

M6,M7 0.4 0.4 2

M8,M9,M10,M11 1 0.4 2

M12,M13 2 0.4 1

M14,M15 1.6 0.4 4

Mc1,Mc2 0.4 0.4 2

Table 4.2 Device ratio summary of first OP The decision of the size is based on the following principles:

(1) The current density is matched.

(2) Tune M1, M2 to meet the gm and Fu specification.

(3) Tune M3 to supply the current for M1, M2.

(4) Tune M8~M11 to make a high load impedance for differential signal.

(5) Tune M12~M5 that the output stage has a output closed to 0.5VDD, and the gain of the whole OP exceed 50dB.

(6) Tune Mc1,Mc2 to make the phase margin exceed 60°

29

The performance summary of the first OP is listed at Table 4.3:

Specification Result

DC gain 50.8dB

Phase margin 71.4°

Slew rate 2.68V/us

ICMR (input common mode range) 960mv

Output Swing -950mv~950mv

PSRR 97dB CMRR 68dB

GB 7.1MHz Power 20.2uW

Table 4.3 Summary of first OP simulation results

The comparison of the two OP for a 1.6pf loading capacitance is listed at Table 4.4, and the frequency response of the first OP is shown at Figure 4.7:

Gain(dB) GBW Total Power

OP1 50.8dB 7.1MHz 20.2uW

OP2 50.6dB 5MHz 8.8uW Table 4.4 Performance comparison of the two OP

30

Figure 4.3 Frequency Response of first OP

Because of the differential architecture of the OP, we must have a CMFB circuit which is used because it is the most power-efficient. as shown at Figure 4.4. In the CMFB circuit, Vcmo is set to 0.5v and only the switch connect to CMFB use CMOS switch, other switches is PMOS switch only.

C1a C1b

C2a C2b

CM

Vo1 Vo2

Vcmo Vcmo

Vcmo Vcmo

31

Figure 4.4 Dynamic CMFB circuit

The device ratio summary we used in CMFB circuit is listed at Table 4.4, and the transient response of the first OP and CMFB circuit is shown below at Figure 4.9:

Transistor Type W/L Transistor Type W/L

PMOS 2/0.4 NMOS 1/0.4 Capacitor Value Capacitor Value

C1 0.2pf C2 0.4pf

Table 4.5 CMFB circuit summary

Figure 4.5 Transient Response of first OP output

4.2.2 1-bit Quantizer

The 1-bit quantizer is realized with a comparator and a SR latch, shown at Figure 4.6. The comparator is a dynamic comparator which has lower average power consumption, when CLK1 is high, the comparator compares the two input voltage, and the comparison result is followed by the SR latch behind the comparator.

32

inp inn

CLK1

outn

outp

Comparator SR latch

M1a M1b

M2a

M2b

M3a M3b

M4a

M4b M5a

M5b

M6a M6b

M7a M7b

M8a M8b M9a M9b

Figure 4.6 a power-efficient 1-bit quantizer

The simulation result of the 1-bit quantizer is shown at Figure 4.7, for a 10KHz input signal and a clock of 1MHz, the quantizer compare the input signal correctly.

After the simulation result, the device ratio of the quantizer is listed at Table 4.6.

Figure 4.7 Simulation results of the 1-bit quantizer

33

Width(um) Length(um) M

M1a,b 4 0.4 1

M2a,b~M5a,b 1 0.4 1

M6a,b 1 0.4 5

M7a,b 1 0.4 1

M8a,b 1 0.4 5

M9a,b 0.5 0.4 1 Table 4.6 Quantizer transistor size summary

4.2.3 Clock Generator

The on-chip clock generator is shown as Figure 4.8, an external clock input signal is buffered and then two non-overlapping clock phases are generated. To avoid the signal dependent charge injection, two delayed clocks, i.e., C1d and C2d, are also be generated.

clk

clk1 clk1d

clk2 clk2d

Figure 4.8 Clock generator circuit

34

The outputs of the clock generator are four different clock phase, the simulation results are shown at Figure 4.9 which shows that the phase one and two are non-overlapped each other.

Figure 4.9 Output of the clock generator

4.2.4 Switches

The current of a MOS switch:

(

_{GS DS}

)

_DS The turn-on resistance of the NMOS, PMOS and CMOS switches can be derived as:

)

35

It is clearly that:

(1) A bigger device ratio has smaller turn on resistances, but larger area is resulted.

(2) Use NMOS switch as much as we can due to the area consideration.

(3) When the signal of the MOS switch is large, for example, input signal and feedback signal, use CMOS switch.

4.3 Modulator Design and Simulation

A second-order sigma-delta modulator with CIFB topology is done as Figure 4.10:

+

OPAMP1 OPAMP2 Com parator

Figure 4.10 2nd order CIFB SDM

36

The Sigma-Delta modulator is implemented by fully differential input and output signal, the building blocks in this figure are done as we described in previous sections.

With a 4kHz sinusoidal input signal and a -6dB full scale input amplitude, the simulated time-domain integrator output signal and the frequency-domain output spectrum can be observed by Figure 4.11 and Figure 4.12, respectively:

Figure 4.11 output signals of input and two integrators

37

Figure 4.12 8192-point output FFT of the pre-simulation result

4.4 Layout Level Design

A physical design in the context of integrated circuit is referred to as layout. Effects of parasitic components and mismatching will damage the performance of the chip, so layouts must be considered heavily in design process. Several principles of layout must be obeyed to minimize cross-talk, mismatches include (a) multi-finger transistors (b) symmetry (c) dummy cell (d) common centroid.

The diagram of layouts are shown at Figure 4.13, there are eighteen I/O pads, including a pair of differential inputs, a pair of modulator outputs, a input clock, three VDD and GND for analog and digital circuit, a pair of clock for measurement, others for reference voltages. The I/O pad description is listed at Table 4.7. This circuit is fabricated in a TSMC 0.18 um CMOS Mixed Signal RF General Purpose Standard Process FSG Al 1P6M process. The chip area is 0.349mm² including I/O pads and

10² 10³ 10⁴ 10⁵ 10⁶

-120 -100 -80 -60 -40 -20 0

Frequency [Hz]

Output Spectrum [dB]

Input signal =4kHz SFDR=73B SNDR=68dB

38

0.058mm² for the core area.

Clock 1st stage

2nd stage

comparator

  Figure 4.13 Diagram of the layout

The package type of proposed chip is S/B type 18 pin, as shown in Figure 4.14.

Figure 4.14 Diagram of the18 pin DIP package

39

Pin Name Description

1 CLK Input clock signal

2 CK1d Output clock for measurement

3 CK2 Output clock for measuremen

4 Agrgnd Ground for analog circuit guard ring

5 Vbias Voltage for bias circuit

6 Vcmo Reference voltage

7 Vcmi Reference voltage

8 Vrefn Reference voltage

9 Vrefp Reference voltage

10 Vin1 Differential input signal

11 Vin2 Differential input signal

12 Agnd Ground for analog circuit

13 Avdd VDD for analog circuit

14 Vout1 Differentail output signal

15 Vout2 Differentail output signal

16 Dgrgnd Ground for digital circuit guard ring

17 Dgnd Ground for digital circuit

18 Dvdd VDD for digital circuit

Table 4.7 Pin Assignments of whole chip

The 8192-point FFT of the post simulation result is shown as Figure 4.15 with the input frequency of 4k and1k and the input amplitude is -6dB of full scale.

40

Figure 4.15a 8192-point FFT of the post-simulation result

Figure 4.15b 8192-point FFT of the post-simulation result

10² 10³ 10⁴ 10⁵ 10⁶

-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0

Input signal =1kHz SFDR=69dB SNDR=63dB Frequency [Hz]

Output Spectrum [dB]

10² 10³ 10⁴ 10⁵ 10⁶

-120 -100 -80 -60 -40 -20 0

Output Spectrum [dB]

Frequency [Hz]

Input signal =4kHz SFDR=72dB SNDR=66dB

41

Because of the possibly process variation, we simulate the SNR results for corners, the corner simulation results are summarized at Table 4.8.

TT FF SS

SFDR (dB) 72 69 69

SNDR (dB) 66 64 63

Table 4.8 Corner of post-layout simualtion

The dynamic range is 74dB as Figure 4.16 shows.

-80 -70 -60 -50 -40 -30 -20 -10 0

0 10 20 30 40 50 60 70 80

Figure 4.16 Dynamic range of the SDM Vin/Vref (dB)

SNDR (dB)

42

Finally, the performance summary of the proposed SDM is listed at Table 4.9, the simulation result shows that the peak SNDR is 66dB for a 4 KHz signal bandwidth and sampling frequency of 1MHz. The difference in SNDR between Pre-Sim. and Post-Sim. is due to the parasitic capacitor between the input and output of OPamp which changes the integrator gain (b1, b2) majorly. The average power consumption is 48uW, core area is 0.058mm².

Specification Pre-Sim. Post-Sim.

Supply voltage 1v

Signal bandwidth (Hz) 8k Clock frequency (Hz) 1M

SFDR (dB) 73 72

SNDR (dB) 68 66

Chip area 638um*548um

Power (uW) 45.5 48

Table 4.9 Summary of the proposed SDM

43

Chapter 5

Testing Setup and Experimental Results

A testing setup for fabricated chip is presented in this chapter. And a costumed designed printed circuit board (PCB) is designed and fabricated to integrate the targeting prototype chip in order to measure the performance metrics of proposed design. Following by the setup for measurement, the experimental results is presented and discussed. And the performance summary is summarized in the end of this chapter.

5.1 Testing Environment Setup

The testing environment setup is shown as Figure 5.1. It includes a printed circuit board (PCB) including a device under test (DUT) board, a logic analyzer (Agilent 16902A), an audio-band function generator (Stanford Research DS360), a power supply (Keithley 2400), a clock function generator (HP HEWLETT PACKARD 33120A) and a PC to analyze the output bit stream of proposed modulator.

44

Power supply

Keithley 2400

Clock generator HP 33120A

Signal Generator Stanford Research

DS360

PCB

Logic analyzer Agilent 16902A

BUS

PC (Matlab)

Figure5.1 experimental test chip

As shown in Figure 5.1, the input signal is generated by audio-band function generator, and the digital output is fed to the logic analyzer, then load to PC for MATLAB simulation. A PCB board combines the clock generator and a device under test (DUT) to measure the chip. The photograph of the measurement environment is shown at Figure 5.2.

Figure 5.2 Photograph of the measurement environment

45

5.2 Problem of Chips

We encountered a problem when measuring the chips. The output of clock

generator was connected to the output pads to observe if the clocks are nonoverlapped.

It is shown at Figure 5.3. The capacitors of output pads increase the loading of clock generator so that the clock generator doesn’t work as simulation. After discussing with my adviser, we cut the metals between output pads and clock generator. Thus the clock generator works normally and we measured the chips again. The die photos and are shown at Figure 5.4 and Figure 5.5

46 Clock generator

Figure 5.3 The problem of clock generator

Figure 5.4 The die photo before modifying

47

Figure 5.5 The die photo after modifying

5.3 Performance Evaluations

The performances of SDM in this work were assessed by input it with a fully sinusoidal signal 1kHz and acquired the digital output from a logic analyzer, after then transferring them into PC. Subsequent analysis contained digital filtering and frequency domain examination is performed by program MATLAB.

The active area of experimental SDM is 0.058mm² including output buffers, sub-circuits for verification and bias circuits. This proposed SDM based on second-order structure are operating at OSR=64, clock rate is 1MHz, and the corresponding bandwidth is 8kHz. The time domain analysis is measured by an oscilloscope (Agilent 54641D) as well as the differential inputs and outputs of this prototype are shown in Figure 5.6, simultaneously, these waveforms without decimation filter and calculated by FFT with Hanning window are shown in Figure 5.7. The bit-stream of SDM outputs drive a logic analyzer (Agilent 16902A)

48

and are evaluated digital signal processing (DSP) by MATLAB, the measured

performance SNDR is 58 dB and SFDR is 66 dB by 8192 FFT with Hanning window.

The log scale plot and linear scale plot are sequentially shown in Figure 5.8 and Figure 5.9.The static and dynamic performances of this SDM are summarized in Table 5.1.

Figure 5.6 Measured output waveforms of the SDM

Figure 5.7 Measured output spectrum of the SDM

49

Figure 5.8 linear scale PSD of measurement

Figure 5.9 log scale PSD of measurement

10² 10³ 10⁴ 10⁵ 10⁶

Input signal =1kHz SFDR=66B SNDR=58dB Frequency [Hz]

Output Spectrum [dB]

50

Architechture Second order SDM

Process TSMC 0.18μm 1P6M1.8V standard CMOS with MIM process

Actice rea 0.058mm²

Sampling rate 1MHz

OSR 64

Input bandwidth 8kHZ

Peak SFDR 66dB

Peak SNDR 58dB

Power dissapation 53uW

Table 5.1 Performance Summary

5.4 Comparison

The comparison of this work and previous researches are listed at Table 5.2 , in order to compare the design result, we define the figure-of-merit as:

The FOM comparison shows that the proposed SDM is low power consumption and small chip area when comparing to other researches .

FOM=

power * area bandwidth

* SNDR

[4]

51

Table 5.2 comparison with other SDM in 0.18um

5.5 Summary

The circuit present in this thesis is implemented by design considerations described in Chapter 3 and circuit design implementation in Chapter 4.This work emphasized the design flow for low-power and small-area design and the stability.

The partial difference in SNDR between Post-Sim. and measurement is due to the loading of package which induces the second order harmonic tone in-band.

The target resolution of this SDM is 9 bits (55 dB), and the actual one when measuring is 9.5 bit (58 dB). It achieves the performance which we expected.

52

Chapter 6 Conclusions

This thesis describes the design criteria of a second-order sigma-delta modulator (SDM) with CIFB structure for audio-band applications. The simple switched- capacitor circuit with a low power OPamp and small capacitor value makes the whole power consumption of SDM is 53uW and the active area is 0.058mm².

The Sigma-Delta ADC which has high resolution 、high stability and low cost is employed in the hearing aids for moderately hearing-impaired. Using 0.18um CMOS technology, this modulator achieves SNDR of 58dB with 8kHz bandwidth. The measured SNDR achieves the target (SNDR 55dB).

The power consumption of SDM is 53uW which doesn’t dominate the power consumption of hearing-aids. We might decrease the power consumption of the SDM if it is for other applications which need low power.

53

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在文檔中 應用於音頻之三角積分調變器之設計與製作 (頁 33-0)