Chapter 1 Introduction
1.2 Organization
This thesis is organized as six chapters. Chapter 2 describes the overview of current-steering DAC at first, then SFDR constrained by switch size of current cell and glitch-reducing method will be discussed.
Chapter 3 explains the non-idealities in the current-steering DAC, including the relation between glitch problems and spectral performance then random and symmetric errors are mentioned. Some paper will be reviewed in this chapter.
Chapter 4 presents the implementation of the DAC. It includes “multi-finger” for reducing glitch and optimal switching sequence for reducing INL. The impact of output impedance on INL and SFDR performance is explained. Then layout of settling time and bias circuit are considered. Finally the simulation results are presented.
Chapter 5 presents the testing setup and measurement results. Conclusions are following by Chapter 6.
Chapter 2
Overview of Current steering DAC
This chapter begins with a brief overview of digital-to-analog converter (DAC) in the aspects of segmented current-steering architecture. Following by the classification of DAC, we discuss the nonlinearity of current-steering DAC.
2.1 Ideal Digital-to-analog Converter (DAC)
When a DAC is used in wireless communication applications it is important to know the limitations of the converter and how they affect the performance of the entire system.
Therefore measures to characterize the converters are needed. The DAC viewed as a black box (shown in Fig. 2.1), takes an digital input signal and converts it to a analog output usually in the form of a voltage or a current.
2.2 Static Performance of DAC
Due to non-ideal circuit elements in the actual implementation of a DAC the
digital code transition points in the transfer function will moved as illustrated in Fig.2.2. The step size in the non-idea data converter deviates from the ideal size Δ and this error is called the differential nonlinearity (DNL) error. For a DAC the DNL can be defined as the following equation since the analog value can be directly measured at the output. In the other way, the total deviation of an analog value from the ideal value is called integral nonlinearity (INL). The normalized INL can expressed as Fig. 2.2.
Differential nonlinearity
Fig. 2.2 Non-ideal DAC’s transfer function.
2.3 Dynamic Performance of DAC
A sinusoidal signal is often used to characterize a data converter. It is therefore interesting to calculate the ideal signal-to-noise ratio of a DAC using such an input signal, q is the quantization process.
Δ Δ
Noise power = 2 1 2
( ) 12
P
n =∫ q
×pdf q
×dq
= Δ Signal power = 1 22
S F
P
=A
S2
6 2
s FS
n
P A
SNR
≡P
= × Δ2 3
2 6.02 1.76
2
N
SNR
dBN dB dB
⇒ = × = × + (2.1)
The spurious free dynamic range (SFDR) is the ratio of the power of the signal and the power of the largest spurious within a certain frequency band. SFDR is usually measured in the FFT spectrum (shown in Fig. 2.3). Its the height between the signal power and largest spurious power. So SFDR can be expressed as (2.2) [18].
Signal Power
10 log( )
Largest Spurious Power
SFDR
dB = × (2.2)Fig. 2.3 FFT spectrum of non-ideal DAC
2.4 Segmented Architecture Current-steering DAC
To achieve good monotonicity and reduce the influence of glitches, as well as reducing the sensitivity to matching errors, the DAC should be segmented into a coarse and fine part. The coarse part is thermometer coded and find part is kept binary weighted.
The thermometer ceded DAC architecture means that a number of equally weighted elements. The binary input code is encoded into a thermometer code as illustrated in Table 2.1 for 3-bit input code. With N binary bits, we have M =
thermometer coded bits. The analog output dependent by digital input i :
2N −1
0
( )
Mout LSB
k
I i I k
=
= × ∑
(2.5)Table 2.1 Decimal, binary and thermometer code representations.
Decimal Binary weighted Thermometer code
0 000 0000000 1 001 0000001 2 010 0000011 3 011 0000111 4 100 0001111
5 101 0011111 6 110 0111111 7 111 1111111
In the thermometer coded DAC the reference elements are all equally large and the matching of the individual elements becomes simpler than the binary case. The total sum of all weighted is2N −1. The transfer function of the thermometer coded
converter is monotonic and the DNL and INL is improved compared to the binary version. The requirement on element matching is also relaxed. In fact, if the matching is within a 50% margin, the converter is still monotonic [6].
For a high resolution and large number of bits, the digital circuits converting the binary code into thermometer code and the number of interconnecting wires may be occupied large area. This implies a more complex circuit layout.
To trade off the performance and cost, the better choice is a DAC structure where the M most significant bits (MSBs) are thermometer coded and the N least significant bits (LSBs) are binary weighted. This is referred to as a segmented structure and it is illustrated in Fig. 2.4. Each architecture that of the current cells is shown in Fig. 2.4 includes latch, current source and switch pair.
An extension to the segmented structure is to use multi-segmentation. For example, the M MSBs are thermometer coded in one cluster, the K LSBs are kept binary coded, and the N-M-K intermediate bits are also thermometer coded in one separate cluster for example as [6].
out out
Fig. 2.4 Segmented current source array.
2.5 Nonidealities in current-steering DAC
This section discusses defects of actual current-steering DAC caused by glitch, random errors and systematic errors. As following, several papers to overcome above limitation are proposed and detail mechanisms of papers in the recently years.
As mentioned in chapter 1, the glitch causes THD (the best total harmonic distortion) high, so that the SFDR will get worse. The dynamic performance of current-steering DAC is limited by three factors:
Δ 3Δ 2Δ
Fig. 2.5 An actual DAC output signal and the FFT of sine iuput
2.5.1 The imperfect synchronization of the control signals of the switch pair
This problem can be solved by placing synchronization latches in front of the switches. In this way any different delay introduced by the digital decoding logic circuit can be eliminated. This is to overcome the skew between the row and column select signal. Moreover , special attention has been paid to the layout to ensure that the interconnect capacitance and resistance at the latch outputs are the same value, so that the synchronism is kept as good as possible. However, the logic of the 4 LSB’s is
more difficult to keep synchronism with the MSB’s part.
2.5.2 Coupling of the control signals feed-through the C
gdof the switch pair to the output
The coupling of the switching control signals to the output lines through the Cgd of the switching transistors is a source of glitches.
I
OUTI
OUTΔV
g switch
V − Δ
Fig. 2.6 The effect of Cgd
The voltage variation at the DAC output is approximately by
gd
g switch
gd d tot
V C
C C
− −Δ ≈ Δ
+ V
(3.1)where Cd-tot is the total parasitic drain capacitance of the switching transistor, then n number current switch cell the total glitch is
n
ΔV
, when n is large, significant glitches appear at the output of DAC. Furthermore, the glitches dependent on the control signal of the switch transistor, so it is code dependent, they cause harmonic distortion of the DAC input signal.2.5.3 Drain voltage fluctuation of the current source transistors
Ideally, the voltage at the drain node of current source transistor should be constant to produce stable current. In the conventional switch driver, both switches may be simultaneously in the off-state for a short period of time, so the current source transistor will enter the linear region. Therefore a large voltage variation at this node can manly degrade the DAC’s dynamic performance.
A popular circuit solutions is to isolate the drain node of the current source by using cascode transistor. This solution is effective, however , provided that cascode transistor remain in saturation. Furthermore, because of the limited power supply voltage, the current source gate voltage overdrive must be reduced by the Vd-sat
voltage of the cascode transistor.
I
OUTI
OUTVcs
Vcas VDD
Switch pair
Current source
Cascode MOS
Voltage fluctuation
g switch
V − g switch
V −
Fig. 2.7 The effect of voltage fluctuation
2.6 Current Source Random Error
Matching current sources suffer a finite mismatch due to uncertainties in each step of the manufacturing process. The random variation is modeled using a normal distribution with expected value zero and a relative standard deviation σ( )I I.
( (2 ))N p Y
Fig. 2.8 Random error and its normal distribution
. From [7], for 10 bit resolution we require 99.7% yield to achieve INL specification (<0.5LSB) ,so σ( )I I is about 0.5%.
1/ 2
1/ 2LSB ( (2 ))N (2 )N C ( (2 ))N (2 )
LSB
p Y dY
Cσp Y dY
σ
− = −
∫ ∫
N0.5 2
yield
= +
INL
_ 0.5 _
2 INL yield C = inv norm ⎛ ⎜ + ⎞ ⎟
⎝ ⎠
2
1 2
NI
I C
σ
+
⎛ ⎞ ≤
⎜ ⎟
⎝ ⎠ •
2.7 Current Source Systematic Errors
For DAC with a resolution of 10-bit and higher, the dimensions of the current source array become so large that process, temperature, and electrical gradients have to be considered. A radial pattern in the oxide thickness which gives rise to a shift values in the current source array approximately linear with the devices separation distance. Temperature gradients and stress gradients are responsible for errors approximately parabolic across the array matrix as shown in Fig. 2.9.
-1
Fig. 2.9 Systematic Errors
2.8 Review of Current Steering DAC
There are many papers presented in the recently years as shown in Table 2.2.
Here we take attention on glitch problem which is focused by some papers. [7] is the comparison with my goal.
Table 2.2 Specification of current-steering DAC papers in the recently years
Year Tech
2.8.1 Deglitch and low power latch
The glitch problem has great effect upon the dynamic performance of current-steering DAC. The synchronization of control signals of the switches and the voltage variations at the drain of the current source transistors. Generally, the latch which is placed in front of the current cell can be seen as a driver. It performs the final synchronization and adjusts the crossing point of the differential output of control signals.
This has presented a latch as shown in Fig. 2.10 in [7] which reduces power glitches and dynamic power consumption because there is no dc current path from VDD to GND. For PMOS current switch used in this design, the differential output control signals of the latches must have a low crossing point to prevent switch transistors from being simultaneously turned off.
Din
Din
Fig. 2.10 Low power and low glitch latch
2.8.2 Dummy transistors for preventing glitch
For minimizing the feedthrough to the output lines, the drain of the switching transistors is isolated from the output lines. This thesis adds two cascaded transistors (with the same dimensions as the switching transistors), as shown in Fig. 2.11 in [4].
For a high-to-low transition of the control signal, while the switching transistor is forming a channel, the cascaded transistors are off and the signal path from the drain of the switching transistor to the output node is open. The coupling is therefore avoided. For a low-to-high transition some coupling exists at the beginning, but since the switching transistor cuts off very rapidly the voltage at the source of the cascade transistor drops, turning it off, and isolating the output node for the remaining of the transition of the control signals.
I
OUTI
OUTFig. 2.11 The current cell with dummy transistors
2.8.3 Finger approach for reducing glitch
the glitch height, but does not completely remove this glitch.
[5] MSB current cell requires a relatively large size of the switch to pass this large current. But due to overlap capacitance, there occurs a glitch. When it changes from off to on state. To reduce this glitch, a novel approach is used. In this approach, the large dimension of switch is split into different small switches. The gate inputs of these switches are progressively delayed by an optimum delay (Fig. 2.12). This reduces the height of the glitch, because it splits the big glitch into different small glitches. Finger approach definitely reduces
Fig. 2.12 The current cell with finger approach
2.9 Summary
There is an deglitch circuit proposed to reduce the clock feed-through from latch to DAC’s output in [2][3], but it still can’t reduce the glitch produced by switch transistors when the switching moment.
Dummy transistors in [4] that are placed under switch transistors to prevent the switching glitch. The current cell with dummy transistors needs high supply voltage to keep every transistor in the current cell work in saturation.
The glitch height is reduced in [5], it has presented a “finger-approach”
technique to make the switch on or off in the different time. But the slightly different time is tune by delay cell in front of the current cell, may cause more power consumption, and hard designed in high speed DAC.
This paper has proposed a “multi-finger” technique to reduce the glitch energy efficiently without adding any circuit, so it needn’t additional power consumption and area.
Chapter 3
Reducing The Glitch Energy
Most current-steering DACs are implemented using a segmented architecture in [5] as shown in Fig. 3.1 includes N bits binary-weighted current sources and M bits unary current cell which are the equally weighted in thermometer part.
W L W
L+ ΔL
W L+ ΔL W
L
Fig. 3.1 “N + M” segmented current steering DAC
The main glitch is caused by MSB part (thermometer DAC) which requires a relatively larger size of the switching transistors. MSW, MSB pass this larger current.
However, due to overlap capacitance, when switches are in the switching moment then the worst case of glitch occurs. This paper present a special technique called
“multi-finger” which make the MSB’s switch transistors finger into two transistors which have slightly different length, so the switches will trigger non-simultaneously to reduce the glitch energy.
3.1 SFDR Constrained by Switch Size of Current Cell
The SFDR is constrained by two conditions: the first is the gain of switch transistors; the other is the delay difference (dmax) of output net of DAC.
The current cell can achieve an improved bandwidth up to the Nyquist frequency in [8]. There is a relationship between the required output impedance and SFDR specification is given by
(1 2 )
4 4
L L
required
NR Q NR
R Q Q
= − ≈ (3.1)
where Q is the ratio between the fundamental signal and the second harmonic component (Q can be seen as SFDR).
V
g,sw Vg,swVDD
MCS
MCAS
MSW MSW
RL RL
V ( )O t V ( )O t
Fig. 3.2 The basic current cell
Besides, the gain of switch transistor has to be larger than the given equation (3.2) otherwise the non-linearity introduced by the output impedance of the DAC make a hard constraint on the dynamic specification.
0
2
0msw sw N required
g r ≥ π f C R
(3.2)where fN is the Nyquist frequency, C0 is the total capacitance at the drain of the current source. Combine (3.1) (3.2) condition.
0
2
0We can get a relationship between switch size and SFDR for gain condition.
On the other way, there is an issue about the delay difference on the output net in [9]. We call the delay dmax in this thesis. The dmax influences the SFDR as the equation (3.4).
where
Δ 2rd
is the second harmonic, fin is input frequency, fck is sampling frequency.For current-steering DAC, the switches are driven by latches. Normally the slew rate of the latches determines the transition time Tsw. As a simply approximation, if the gate capacitance of the switch transistor is Csw, then the transition time can be expressed as
Fig. 3 shows the waveform of the control signal Vg,sw. Tsw is the transition time of control signal. Vd,sw is the drain voltage of the switch transistor, Vo,pp is the peak-to-peak value of the output voltage. Vd,sw is the 1/ (1+gmro) ratio of Vo,pp. The factor Vg,sw/Tsw is the switching speed. We can see that the dmax can be expressed as
,
take (3.5) in (3.4) equation
⇒
4
,The intrinsic idea of this method is to increase the size of switch transistor to improve the SFDR specification.
d
maxT
swV
g,swV
d,swFig. 3.3 Transition of the control signal of switch (MSB)
3.2 Multi-finger Technique
The optimal solution of switch size must satisfy the (3.2) for gain condition and (3.6) for dmax condition as shown in Fig. 3.4. The W*L is taken A to achieve best SFDR specification.
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Fig. 3.4 SFDR constrained by switch size
In this thesis, we especially finger MSB’s switch into two transistors and tune the length of them slightly different to make the switch on or off non-simultaneously as equation (3.7).
( ) ( ) *( Besides, full scale current of DAC has been decided at first, then the MSB’s current of unary cell in thermometer part is the M times of LSB’s current in binary part. So that to keep the same Vov of switch transistor for every current cell of all DAC.
MSB LSB MSB LSB
W W
I M I M
= ⇒ L =
L
(3.8) From the equations (3.7) and (3.8), we can get the only solution of L to design the different switching time for reducing glitch energy in the derivation in (3.9) and asshown in Fig. 3.5. The glitch energy is proportional to the switch size, if the finger transistor can on or off non-simultaneously. The glitch energy will be reduced approximately half.
* ( 2
LSB
L
)A M W L
Δ= + (3.10)
1
* W L
Fig. 3.5 The only solution of ΔL
Chapter 4
DAC Implementation
In this chapter, to verify the method of reducing glitch energy, we have proposed a segmented architecture includes 4 bits LSBs binary-weighted DAC and 6 bits MSBs thermometer part as shown in Fig. 4.1. multi-finger is proposed at first and each component will be design as following, infinite output impedance and layout consideration are the important issues in the DAC design. Finally, the simulation results are presented at last.
Input Registers
Local Decoder + Latches Array
4 bits binary 6 bits thermometer
Fig. 4.1 “4 + 6” segmented current steering DAC
4.1 Multi-finger For Reducing Glitch
As Chapter 3 mentioned, the constant A of this design is 0.54um2. M = 24 for this 4 bits binary DAC + 6 bits thermometer DAC current-steering architecture. After
simply calculating, we can get the only solution for ΔL = 0.18um. The fingered size of MSB’s transistors is listed in Table 4.1.
Table 4.1 : The finger size of MSB’s switch transistors MSW1 MSW2
Width 1um 1um
Length 0.18um 0.18um+0.18um
4.2 The Digital Circuits
Fig. 4.2 shows the digital circuits which are perform in the front end of DAC.
First, the 10-bit input signal need to synchronize by the registers. Then the input binary codes of 6-MSBSs are converted into 63 bits thermometer codes. Because the 6-to-63 decoder circuits are complicated, we divide it into row-and-column which are two 3-to-7 thermometer codes. All the signals from the binary-to-thermometer circuits feed into the local decoders in the same time to control the 63 latches. A delay equalizer in the binary-weighted path is used to eliminate the different delay time between the control paths in the MSB and LSB part.
Fig. 4.2 Digital circuits
Fig. 4.3 (a) is the schematic of 3-bit to 7-bit thermometer code. Fig. 4.3 (b) is the wave form of the thermometer code.
T1=b1+b2+b3 T2=b2+b3 T3=b1 b2+b3•
T4=b3
T5=(b1+b2) b3• T6=b2 b3• T7=b1 b2 b3• •
(a) schematic
(b) simulation of binary to thermometer code Fig. 4.3 3bits binary to 7 bits thermometer code
Symbol
4.3 The High-Speed Latch
We place a latch in front of the current cell. The 4bits binary-weighted and 63bits thermometer codes differential signals that produced from the local decoder are finally synchronized to control the current cell in the same time. Second, when the latch’s differential output signals operates in the crossing point which is in the middle of supply voltage. The switch pair will turn off simultaneously, so that the current-source transistor will work in the linear region. The voltage fluctuation occurs on the drain node of the current-source transistor.
Fig. 4.4 shows the schematic of the latch in this design [10]. For PMOS current cell used in this thesis, the low crossing point is needed to prevent the switch pair turn off simultaneously. Two extra NMOS transistors (M5a, M5b) are placed in the parallel with each of the cross-coupled NMOS. M5a, M5b perform the fall time is much faster than rise time of the driver circuit. In this way, a low crossing point of the differential outputs is available at the output of the latch. The additional feedback by the inverter pair suppresses the clock feedthrough which is produced by the pass transistor and stabilizes the synchronized input signals. Fig. 4.4 (c) shows the wave form of the latch.
DIN
DIN
OUT OUT
(a) schematic
DVDD
(b) differential output signals
(c) simulation of differential output Fig. 4.4 The high speed latch
4.4 Output Impedance Analysis
The impedance at the DAC’s output node in Fig. 4.6 (a) is determined by a parallel circuit of the unity current switch cell. As generally known, the Zimp seen in DAC’s output needs to be made large so that its influence on the INL specification of the DAC is negligible. The relation between the Zimp and achieved INL specification
The impedance at the DAC’s output node in Fig. 4.6 (a) is determined by a parallel circuit of the unity current switch cell. As generally known, the Zimp seen in DAC’s output needs to be made large so that its influence on the INL specification of the DAC is negligible. The relation between the Zimp and achieved INL specification