Chapter 4 DAC Implementation
4.9 Simulation Results
Pre-layout simulation Results
The static specification DNL/INL need less than 0.5LSB to achieve accurate required. Pre-simulation results is in the condition of (fin/fck = 250M/500M), and shown in Fig. 4.11, DNL = 0.03LSB, INL = 0.042LSB. SFDR is 80 dB @ fin/fck = 50MHz/ 500MHz.
0 200 400 600 800 1000 1200
-0.04
0 200 400 600 800 1000 1200
-0.04
Fig. 4.11 Pre-layout simulation for (a)DNL (b) INL
0 0.5 1 1.5 2 2.5
Fig. 4.12 Pre-layout simulation for SFDR=80dB @ fin/fck = 50MHz/ 500MHz
Version 1 of Layout Diagram
This thesis is implemented in TSMC 0.18um 1P6M CMOS technique, the layout of core area is 0.25mm2 and 0.58mm2 with PAD. The layout diagram is shown in Fig.
4.13.
The static specification DNL/INL need less than 0.5LSB to achieve accurate required as shown in Fig. 4.14. DNL = 0.25LSB, INL = 0.27LSB.
Fig. 4.13 Version 1 of Layout Diagram
0 200 400 600 800 1000 1200
-0.2 -0.1 0 0.1 0.2 0.3
input code
DNL (LSB)
0 200 400 600 800 1000 1200
-0.2 -0.1 0 0.1 0.2 0.3
input code
INL (LSB)
Fig. 4.14. Post-layout simulation for Version 1 of (a)DNL (b) INL
The 2048-point FFT of the post-simulation result is shown as Fig. 4.15 (a) 55dB
@ fin/fck = 1MHz/500MHz, SFDR (b) SFDR is 47 dB fin/fck = 250MHz/500MHz
0 50 100 150 200 250
-120 -100 -80 -60 -40 -20 0
Frequency [MHz]
Output spectrum [dB]
X: 214.9 Y: -56.02
0 50 100 150 200 250
-120 -100 -80 -60 -40 -20 0
Frequency [MHz]
Output spectrum [dB] X: 18.52Y: -46.96
Fig. 4.15 Post-layout simulation for Version 1 of SFDR
The package type is LCC type 68 pins where the actual chip photograph is shown at Fig. 4.16.
Fig. 4.16 Version 1 of die photograph
The specification of post-layout simulation drop a lot by compared with pre-layout simulation. The main question is the parasitic capacitors between switch pair and the output node. There are 4+63 metal lines that connect to the switch pairs and output node .Those capacitors cause the timing skew and non-synchronization. So,
we need short the connecting line to get small capacitor.
The other problem is the input buffer consideration. The measurement of version
1 is presented in Chapter 5
To solve above two problems, we design the version 2 of layout diagram which includes minimizing metal line between each current cell and output node and adding input buffer in the front of DAC core circuit.
Version 2 of Layout Diagram
The
version 2 of layout diagram is shown in Fig. 4.17. The ESD pad is used in
this version. The metal of each current cell output is minimized to reduce the non-equal capacitors. We have add the input buffer to drive the input loading. The core area is only 0.175mm2 and 0.65mm2 with ESD pad.Fig. 4.17 The layout diagram of 10 bits DAC
Multi-finger Technique
The peak value of the glitch in a DAC’s output as it switches across the largest major transition (0111111111→ 1000000000). Glitch energy definition : 0.5*(glitch_height)*(impulse_time) in [2][3]. The post layout simulation shows that the glitch energy are 0.77pVs without multi-finger and 0.4pVs with multi-finger as shown in Fig. 4.18.
Fig. 4.18 Glitch energy (a) without “multi-finger” (b) with “multi-finger”
10 bits ramp digital is applied to the input, and the output of DAC (Fig. 4.19) is recoded to calculate DNL/INL with MATLAB tool. We can adjust the static performance well or not by the glitch produced in the signal transition.
Fig. 4.19 Differential symmetric ramp code of DAC output
INL and DNL as shown in Fig. 4.20 are less than 0.07 and 0.06 LSB, these results achieve the static requirement.
0 200 400 600 800 1000 1200
-0.1
0 200 400 600 800 1000 1200
-0.05
Fig. 4.20 Post layout simulation for static performance
The SFDR as shown in Fig. 4.13 for a 49M pling rate (a) DNL <0.06LSB (b) INL <0.07LSB
Hz signal at a 500MHz sam
is about 74dB, this specification can satisfy required wireless communication. The summary of the performance of the proposed DAC is show in Table 2. In the near future, the chip will be fabrication and testing the chip performance.
Symbol
0 0.5 1 1.5 2 2.5
Fig. 4.21 Post layout simulation of SFDR
(a) fin/fck /500MHz
4.10 Summary
ary of the DAC version 2 post-layout simulation = 49MHz/500MHz (b) fin/fck = 247MHz
Table 4.2. Summ
[2] APCCAS [3] ISSCC This thesis
version 2
Techn logy o 0.25-μm 0.18-μm 0.18-μmResolution 10-bit 10-bit 10-bit Sampling
(3MHz/300 (49MHz/250 (49MHz/500 59dB
consumption 84mW 22mW 14mW
active area 1.56 mm2 0.35mm2 0.175mm2
chip area 0.65mm2
ENOB
sampling
POWER
FOM= 2 × f
(4.5)Fig. 4.22 shows the performance of the version
shows that the post-simulation result is the lowest compared to the references. The power consumption is also the lowest.
2 posim in this thesis. The FOM
0
[7] [8] : dynamic element matching (DEM)
Fig. 4.22 FOM vs clock frequency
10
y (MHz
Chapter 5
Testing Setup and Measurement Results
In the chapter, we describe the testing environment, and the version 1 measurement results will be presented as followed. Finally, there is a discussion about the reasons of performance decay at last.
5.1 Measurement Setup
Fig. 5.1 shows PCB layout. The differential output of the DAC is connected by the RF transformer T1-6T (differential -to-single) to produce the single out signal.
This measurement include chip with package and without package. The capacitor on the PCB is used to stable the differential voltage between VDD and GND.
Mini_circuit RF transformer T1-6T (single-to-differential ) : 4M~300MHz
Stabling capacitors for VDD/GND : 0.1u, 1u and 10uF
PCB layout with LCC 68 pins package
Fig. 5.1 PCB layout
Fig. 5.2 Test Setup
Fig. 5.2 shows overall of the measurement setup, In the this setup, all of the input digital code is generated by Agilent 16902B logic analysis system. Agilent 54641D oscilloscope is used to measure the waveform of output and recode the voltage data. Apply 10-bit ramp wave ex : fin/fck = 50M/100M (Fig. 5.3), we can catch the data and calculate DNL/INL by Matlab.
Fig. 5.3 Ramp wave shown in oscilloscope
To measure SFDR, we apply 10-bit digital sine code and output is connected to Agilent E4407B which can calculate the FFT in frequency domain.
Fig. 5.4 Sine wave of DAC output
5.2 Measurement Results
Fig. 5.5 shows the DNL/INL in the 1M/100M and 50M/100M frequency, when operating in 50M/100M, the DNL/INL is larger than 0.5LSB (out of static
performance required). Fig. 5.5 shows the DNL/INL performance in different frequency.
Fig. 5.5 DNL/INL in measurement
Fig. 5.6 shows the SFDR in the 1M/100M, 41M/100M, 1M/300M and 50M/100MHz are 50dB, 17dB, 36dB and 11.4dB. Fig. 5.7 shows the SFDR in different (fin/fck). The performance drop in the high frequency of input, the reason will be discussed at last.
fin/fck=1M/100M, SFDR=50.34dB
fin/fck=1M/300M, SFDR=36.07dB
fin/fck=41M/100M, SFDR=17.03dB
fin/fck=49M/300M, SFDR=11.46dB
Fig. 5.6 SFDR in measurement
SFDR vs fin
Fig. 5.7 Measurement vs fin/fck
5.3 Summary
Fig. 5.9 shows the version 1 of DNL, INL and SFDR performance. When the input frequency move up, and performance get worse. This is the layout question which are no buffers in the input of DAC.
Because of the input driving ability is finite in the HSPICE. In actual, the input driving ability is infinite by the device of LNA (Fig.5.8). Input pad must use digital pad (ESD) and add buffer in front of the core circuit to prevent 10-bit input signal skew. There should be clock tree buffer to ensure each duty cycle of clock is 50%
and not skew. The same blocks of digital circuit should be layouted together and different blocks need to be layouted hierarchical. Digital circuit can be save large area by shorting the interconnect from each blocks. The posim with buffer has be shown in Fig. 5.9 and the data of performance is collected in Fig. 5.10.
Fig. 5.8 Actual input driving
Symbol
Post-layout Simulation with Input Buffer
0 200 400 600 800 1000 1200
-0.5
0 200 400 600 800 1000 1200
-1
Fig. 5.9 Posim with buffer vs fin/fck with input buffer
DNL vs fin @ fck = 100MHz
Fig. 5.10 Performance vs presim, posim and measurement
To measure power, we use the source meter to supply the power and record the current into the chip. Power consumption : 1.8V x 7.385mA (analog) + 1V x
1.406mA (digital) = 14.7mW @ (fin/fck = 50M/300M). There is a list about
performance in Table 5.1.Table 5.1 Version 1 specification summary of posim with buffer and measurement results Max clock frequency (Hz)
4+6 Max clock frequency (Hz)
4+6 Segmen-tation
10 Resolution (bit)
Technology (um)
Fig. 5.11 shows the measurement result and post-layout simulation compared with papers in fck vs FOM.
0 0.2 0.4
0.6 [8]
posim with buffer
measurement measurement posim with buffer
0.8 1 1.2 1.4 1.6 1.8 2
0 100 200 300 400 500
clock frequency (MHz)
FOM (pJ) [5]
[3]
[7]
[4]
[6]
[9]
[10]
Fig. 5.12 Performance caparison
Chapter 6
Conclusions and Future Work
This design of 1.8V 10-bit 500MHz current-steering DAC has been implemented in TSMC 0.18-μm. The “multi-finger” technique can reduce the glitch energy efficiently without adding any area and power consumption. The post layout simulation shows that the glitch energy are 0.77pVs without multi-finger and 0.4pVs with multi-finger.
The post layout simulation results that the SFDR about 74dB with a full-scale 49MHz input at 500MS/s. The INL and DNL are less than 0.07 LSB and 0.06 LSB.
The power consumption is only 14mW at maximum sampling rate.
The suggestions for further research are that increasing higher resolution for 12~16 bits or increasing sampling rate for 1GHz ~ 2 GHz.
References
[1] A Silva, J. Guilherme, R.F. Neves and N. Horta, “Designing Reconfigurable Multi-Standard Analog Baseband Front-End for 4G Mobile Terminals: System Level Design,” in Proc. IEEE VLSI Design, vol.42, pp. 34-46, Jan. 2009.
[2] Yongsang Yoo and Minkyu Song, “Design of A 1.8V 10 bits 300MSPs CMOS Digital-to-Analog Converter with A Novel Deglitching Circuit and Inverse Thermometer Decoder,” IEEE Asia Pacific Conference on Circuits and System (APCCAS), vol. 2, pp. 311-314, Oct. 2002.
[3] Jurgen Deveugel and Michiel Steyaert, “A 10 bits 250MS/s Binary-weighted Current-steering DAC,” IEEE Int. Solid-State Circuits Conf. (ISSCC), vol.20, pp.
1003-1013, Sept. 2004.
[4] J. Bastos, A. Marques, M. Steyaert and W. Sansen, “A 12-bit intrinsic accuracy high-speed CMOS DAC,” IEEE J. Solid-State Circuits (JSSCC), vol. 33, pp.
1959-1968, Dec. 1998.
[5] Gaurav Raja and Basabi Bhaumik, “16-bit Segmented Type Current Steering DAC for Video Applications,” VLSI Design on Circuits and Systems pp. 63-68, May 2006.
[6] Anne Van den Bosch, Michiel Steyaert, Willy Sansen , “An Accurate Statistical Yield Model for CMOS Current-Steering D/A Converters,” in Proc. IEEE Int.
Symp. Circuit and Systems (ISCAS), pp. 105-108, May 2000.
[7] Chueh-Hao Yu, Wen-Hui Chen, Day-Uei Li, and Wan-Ju Huang, “A 1V 10-Bit 400MS/s Current-Steering D/A Converter in 90-nm CMOS,” Int. Symp. on VLSI Design, Automation and Test (VLSI-DAT), pp. 148-151, Apr. 2007.
[8] Anne Van den Bosch, Marc Borremans, Michiel Steyaert and Willy Sansen,
“SFDR-Bandwidth Limitations for High Speed High Resolution Current-Steering CMOS D/A Converter,” IEEE Int. Solid-State Circuits Conf.
(ISSCC), vol.3, pp. 1193-1196, Sept. 1999.
[9] Tao Chen and Georges G. E. Gielen, Fellow, IEEE, “The Analysis and Improvement of a Current-Steering DACs Dynamic SFDR-Ⅰ: The Cell-Dependent Delay Differences,” IEEE Transactions of Circuit and Systems-Ⅰ: Regular Papers, vol. 53, no. 1, Jan. 2006.
[10] Kevin O’Sullivan, Chris Gorman, Michael Hennessy, and Vincent Callaghan, ” A 12-bit 320-MSample/s Current-Steering CMOS D/A Converter in 0.44mm2,” IEEE J. Solid-State Circuits, vol. 39, pp. 1064-1072, July 2004.
[11] Yonghua Cong and Randall L. Geiger, “Switching Sequence Optimization for Gradient Error Compensation in Thermometer-Decoded DAC Arrays,＂ IEEE Transaction on Circuits and Systems Ⅱ: Analog and Digital Signal Processing, vol. 47, pp. 585-595, July 2000.
[12] Chun-Yueh Huang, Tsung-Tien Hou, and Hung-Yu Wang, “A 12-bit 250-MHz Current-Steering DAC,” Circuits and Systems, IEEE ASIC, vol.1, pp. 411-414, Oct. 2005.
[13] Ni Weining, Geng Xueyang, and Shi Yin, “A 12-bit 300 MHz CMOS DAC for High-speed System Applications,” IEEE Int. Symp. Circuits and Systems (ISCAS), pp. 1402-1405, Dec. 2006.
[14] Kok Lirni Chani, Jlaian Ulhul and Lani Galtoni, “A 15OMS/s 14-bit Segmented DEM DAC with Greater than 83dB of SFDR Across the Nyquist band,” IEEE VLSI Design on Circuits and Systems, pp. 200-201, June 2007.
[15] Yusuke Ikeda, Matthias Frey, and Akira Matsuzawa, “A 14-bit 100-MS/s Digitally Calibrated Binary-Weighted Current-Steering CMOS DAC without Calibration ADC,” IEEE Asian Solid-State Circuits Conf (ASSCC), pp. 356-359, Nov. 2007.
[16] Petri Eloranta and Helsinki Finland, “A 14-bit D/A-Converter with Digital Calibration,” Circuits and Systems, IEEE Int. Symp. Circuits and Systems (ISCAS), pp.110-112, Sept. 2006.
[17] C-H. Lin and K. Bult, “A 10b 500MSamples/s CMOS DAC in 0.6 mm2, ” IEEE J. Solid-State Circuits (JSSCC), vol. 33, pp. 1948-1958, Dec. 1998.
[18] Anne Van den Bosch, Student Member, IEEE, Marc A. F. Borremans, Michel S.
J. Steyaert, and Willy Sansen, “A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter,” IEEE J. Solid-State Circuits (JSSCC), vol. 36, vol.36, Mar. 2001.
[19] Marcel J. M. Pelgrom, Member ea, ad c. J. Duinmaijer, and Anton p. G. Welbers
“Matching Properties of MOS Transistors, ” IEEE J. Solid-State Circuits (JSSCC), vol. 24, pp. 1433-1439, Oct. 1989.