Chapter 2 Overview of Current steering DAC
2.7 Current Source Systematic Errors
For DAC with a resolution of 10-bit and higher, the dimensions of the current source array become so large that process, temperature, and electrical gradients have to be considered. A radial pattern in the oxide thickness which gives rise to a shift values in the current source array approximately linear with the devices separation distance. Temperature gradients and stress gradients are responsible for errors approximately parabolic across the array matrix as shown in Fig. 2.9.
-1
Fig. 2.9 Systematic Errors
2.8 Review of Current Steering DAC
There are many papers presented in the recently years as shown in Table 2.2.
Here we take attention on glitch problem which is focused by some papers. [7] is the comparison with my goal.
Table 2.2 Specification of current-steering DAC papers in the recently years
Year Tech
2.8.1 Deglitch and low power latch
The glitch problem has great effect upon the dynamic performance of current-steering DAC. The synchronization of control signals of the switches and the voltage variations at the drain of the current source transistors. Generally, the latch which is placed in front of the current cell can be seen as a driver. It performs the final synchronization and adjusts the crossing point of the differential output of control signals.
This has presented a latch as shown in Fig. 2.10 in [7] which reduces power glitches and dynamic power consumption because there is no dc current path from VDD to GND. For PMOS current switch used in this design, the differential output control signals of the latches must have a low crossing point to prevent switch transistors from being simultaneously turned off.
Din
Din
Fig. 2.10 Low power and low glitch latch
2.8.2 Dummy transistors for preventing glitch
For minimizing the feedthrough to the output lines, the drain of the switching transistors is isolated from the output lines. This thesis adds two cascaded transistors (with the same dimensions as the switching transistors), as shown in Fig. 2.11 in [4].
For a high-to-low transition of the control signal, while the switching transistor is forming a channel, the cascaded transistors are off and the signal path from the drain of the switching transistor to the output node is open. The coupling is therefore avoided. For a low-to-high transition some coupling exists at the beginning, but since the switching transistor cuts off very rapidly the voltage at the source of the cascade transistor drops, turning it off, and isolating the output node for the remaining of the transition of the control signals.
I
OUTI
OUTFig. 2.11 The current cell with dummy transistors
2.8.3 Finger approach for reducing glitch
the glitch height, but does not completely remove this glitch.
[5] MSB current cell requires a relatively large size of the switch to pass this large current. But due to overlap capacitance, there occurs a glitch. When it changes from off to on state. To reduce this glitch, a novel approach is used. In this approach, the large dimension of switch is split into different small switches. The gate inputs of these switches are progressively delayed by an optimum delay (Fig. 2.12). This reduces the height of the glitch, because it splits the big glitch into different small glitches. Finger approach definitely reduces
Fig. 2.12 The current cell with finger approach
2.9 Summary
There is an deglitch circuit proposed to reduce the clock feed-through from latch to DAC’s output in [2][3], but it still can’t reduce the glitch produced by switch transistors when the switching moment.
Dummy transistors in [4] that are placed under switch transistors to prevent the switching glitch. The current cell with dummy transistors needs high supply voltage to keep every transistor in the current cell work in saturation.
The glitch height is reduced in [5], it has presented a “finger-approach”
technique to make the switch on or off in the different time. But the slightly different time is tune by delay cell in front of the current cell, may cause more power consumption, and hard designed in high speed DAC.
This paper has proposed a “multi-finger” technique to reduce the glitch energy efficiently without adding any circuit, so it needn’t additional power consumption and area.
Chapter 3
Reducing The Glitch Energy
Most current-steering DACs are implemented using a segmented architecture in [5] as shown in Fig. 3.1 includes N bits binary-weighted current sources and M bits unary current cell which are the equally weighted in thermometer part.
W L W
L+ ΔL
W L+ ΔL W
L
Fig. 3.1 “N + M” segmented current steering DAC
The main glitch is caused by MSB part (thermometer DAC) which requires a relatively larger size of the switching transistors. MSW, MSB pass this larger current.
However, due to overlap capacitance, when switches are in the switching moment then the worst case of glitch occurs. This paper present a special technique called
“multi-finger” which make the MSB’s switch transistors finger into two transistors which have slightly different length, so the switches will trigger non-simultaneously to reduce the glitch energy.
3.1 SFDR Constrained by Switch Size of Current Cell
The SFDR is constrained by two conditions: the first is the gain of switch transistors; the other is the delay difference (dmax) of output net of DAC.
The current cell can achieve an improved bandwidth up to the Nyquist frequency in [8]. There is a relationship between the required output impedance and SFDR specification is given by
(1 2 )
4 4
L L
required
NR Q NR
R Q Q
= − ≈ (3.1)
where Q is the ratio between the fundamental signal and the second harmonic component (Q can be seen as SFDR).
V
g,sw Vg,swVDD
MCS
MCAS
MSW MSW
RL RL
V ( )O t V ( )O t
Fig. 3.2 The basic current cell
Besides, the gain of switch transistor has to be larger than the given equation (3.2) otherwise the non-linearity introduced by the output impedance of the DAC make a hard constraint on the dynamic specification.
0
2
0msw sw N required
g r ≥ π f C R
(3.2)where fN is the Nyquist frequency, C0 is the total capacitance at the drain of the current source. Combine (3.1) (3.2) condition.
0
2
0We can get a relationship between switch size and SFDR for gain condition.
On the other way, there is an issue about the delay difference on the output net in [9]. We call the delay dmax in this thesis. The dmax influences the SFDR as the equation (3.4).
where
Δ 2rd
is the second harmonic, fin is input frequency, fck is sampling frequency.For current-steering DAC, the switches are driven by latches. Normally the slew rate of the latches determines the transition time Tsw. As a simply approximation, if the gate capacitance of the switch transistor is Csw, then the transition time can be expressed as
Fig. 3 shows the waveform of the control signal Vg,sw. Tsw is the transition time of control signal. Vd,sw is the drain voltage of the switch transistor, Vo,pp is the peak-to-peak value of the output voltage. Vd,sw is the 1/ (1+gmro) ratio of Vo,pp. The factor Vg,sw/Tsw is the switching speed. We can see that the dmax can be expressed as
,
take (3.5) in (3.4) equation
⇒
4
,The intrinsic idea of this method is to increase the size of switch transistor to improve the SFDR specification.
d
maxT
swV
g,swV
d,swFig. 3.3 Transition of the control signal of switch (MSB)
3.2 Multi-finger Technique
The optimal solution of switch size must satisfy the (3.2) for gain condition and (3.6) for dmax condition as shown in Fig. 3.4. The W*L is taken A to achieve best SFDR specification.
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Fig. 3.4 SFDR constrained by switch size
In this thesis, we especially finger MSB’s switch into two transistors and tune the length of them slightly different to make the switch on or off non-simultaneously as equation (3.7).
( ) ( ) *( Besides, full scale current of DAC has been decided at first, then the MSB’s current of unary cell in thermometer part is the M times of LSB’s current in binary part. So that to keep the same Vov of switch transistor for every current cell of all DAC.
MSB LSB MSB LSB
W W
I M I M
= ⇒ L =
L
(3.8) From the equations (3.7) and (3.8), we can get the only solution of L to design the different switching time for reducing glitch energy in the derivation in (3.9) and asshown in Fig. 3.5. The glitch energy is proportional to the switch size, if the finger transistor can on or off non-simultaneously. The glitch energy will be reduced approximately half.
* ( 2
LSB
L
)A M W L
Δ= + (3.10)
1
* W L
Fig. 3.5 The only solution of ΔL
Chapter 4
DAC Implementation
In this chapter, to verify the method of reducing glitch energy, we have proposed a segmented architecture includes 4 bits LSBs binary-weighted DAC and 6 bits MSBs thermometer part as shown in Fig. 4.1. multi-finger is proposed at first and each component will be design as following, infinite output impedance and layout consideration are the important issues in the DAC design. Finally, the simulation results are presented at last.
Input Registers
Local Decoder + Latches Array
4 bits binary 6 bits thermometer
Fig. 4.1 “4 + 6” segmented current steering DAC
4.1 Multi-finger For Reducing Glitch
As Chapter 3 mentioned, the constant A of this design is 0.54um2. M = 24 for this 4 bits binary DAC + 6 bits thermometer DAC current-steering architecture. After
simply calculating, we can get the only solution for ΔL = 0.18um. The fingered size of MSB’s transistors is listed in Table 4.1.
Table 4.1 : The finger size of MSB’s switch transistors MSW1 MSW2
Width 1um 1um
Length 0.18um 0.18um+0.18um
4.2 The Digital Circuits
Fig. 4.2 shows the digital circuits which are perform in the front end of DAC.
First, the 10-bit input signal need to synchronize by the registers. Then the input binary codes of 6-MSBSs are converted into 63 bits thermometer codes. Because the 6-to-63 decoder circuits are complicated, we divide it into row-and-column which are two 3-to-7 thermometer codes. All the signals from the binary-to-thermometer circuits feed into the local decoders in the same time to control the 63 latches. A delay equalizer in the binary-weighted path is used to eliminate the different delay time between the control paths in the MSB and LSB part.
Fig. 4.2 Digital circuits
Fig. 4.3 (a) is the schematic of 3-bit to 7-bit thermometer code. Fig. 4.3 (b) is the wave form of the thermometer code.
T1=b1+b2+b3 T2=b2+b3 T3=b1 b2+b3•
T4=b3
T5=(b1+b2) b3• T6=b2 b3• T7=b1 b2 b3• •
(a) schematic
(b) simulation of binary to thermometer code Fig. 4.3 3bits binary to 7 bits thermometer code
Symbol
4.3 The High-Speed Latch
We place a latch in front of the current cell. The 4bits binary-weighted and 63bits thermometer codes differential signals that produced from the local decoder are finally synchronized to control the current cell in the same time. Second, when the latch’s differential output signals operates in the crossing point which is in the middle of supply voltage. The switch pair will turn off simultaneously, so that the current-source transistor will work in the linear region. The voltage fluctuation occurs on the drain node of the current-source transistor.
Fig. 4.4 shows the schematic of the latch in this design [10]. For PMOS current cell used in this thesis, the low crossing point is needed to prevent the switch pair turn off simultaneously. Two extra NMOS transistors (M5a, M5b) are placed in the parallel with each of the cross-coupled NMOS. M5a, M5b perform the fall time is much faster than rise time of the driver circuit. In this way, a low crossing point of the differential outputs is available at the output of the latch. The additional feedback by the inverter pair suppresses the clock feedthrough which is produced by the pass transistor and stabilizes the synchronized input signals. Fig. 4.4 (c) shows the wave form of the latch.
DIN
DIN
OUT OUT
(a) schematic
DVDD
(b) differential output signals
(c) simulation of differential output Fig. 4.4 The high speed latch
4.4 Output Impedance Analysis
The impedance at the DAC’s output node in Fig. 4.6 (a) is determined by a parallel circuit of the unity current switch cell. As generally known, the Zimp seen in DAC’s output needs to be made large so that its influence on the INL specification of the DAC is negligible. The relation between the Zimp and achieved INL specification (< 0.5 LSB) is given (4.1).
where RL is the load resistor, Iunit the LSB current, and N the total number of unit current sources.
To design a sizing strategy in current cell is important with the 1.8V analog supply voltage. First, the aspect ratio W/L fixes the overdrive voltage (VGS-VT) for each transistor and for a given current . The optimal aspect ratio can be found to give MCAS and MSW more rest in headroom, most important, we must consider the output swing and output impedance.
For DAC static requirement INL < 0.5 LSB, take the parameters RL = 50 N = 1024 into (4.5) → ro > 1.31GΩ
For SFDR =70dB to satisfy the wireless communication specification in, take the parameters N = 2b (b = DAC resolution) into (4.2) → ro > 367MΩ
20 log
o6( 2)[ ]
L
SFDR r b dB
= R − −
(4.2)For above INL and SFDR conditions, for INL/SFDR required
ro = (gm3+gmb3)(gm2+gmb2)ro3ro2ro1
= 2.097 GΩ > 1.31 GΩ
Fig. 4.12 shows the LSB differential output current which is 4.2uA.
VQ
VQ
out out
(a) schematic
(b) simulation of differential output Fig. 4.5 The LSB current cell
4.5 Random Errors
In chapter 2.6, to achieve the static specification that INL must be less than 0.5 LSB in 3σ. We can get σ( )I I is about 0.5% in the 10-bit resolution DAC. According to these results and the required area versus matching relation for current source transistor (Mcs) . The minimum area of a unit current source transistor is given by
2 2
Fig. 4.5 shows the curve above equation. In the design, the p-type transistor is more suitable than n-type transistor. Because Aβ and AVT of p-type are less than these in the n-type, smaller area of transistor can be implemented.
Symbol
*** 1unit current switch latch ***
6n
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0
10 20 30 40 50 60 70 80 90 100
Overdrive voltage (VGS-VT) of M1 [V]
Unit current source area [um2]
PMOS NMOS
Fig. 4.6 Unit current source area vs. its overdrive voltage
From Fig. 4.5, it is obvious that increasing the overdrive voltage reduces the area consumed. However, this value of overdrive voltage is limited by the headroom of Mcas and switch transistor. Consider the current switch headroom for 1.8V supply voltage, we take the VGS,min. For required output impedance, these transistors in the current cell must operate in the saturation region.
4.6 Systematic Errors
Systematic errors include parabolic error and linear error. The well known that row-column switching scheme is commonly used to eliminate the parabolic error. Its advantage is the simplicity for design and layout, especially reduce the routing between current cell and local decoder, so that a lot of area can be saved.
Fig. 4.7 The linear and parabolic error distribute in the current source array In this scheme, the parabolic errors are averaged in two directions. In each cell, the area occupied by the local decoder, switches and cascode transistors is often comparable to the active area, a possible way to reduce the source array area and the distances between elements, is to move all the other transistors from the array besides current source transistors.
4.6.1 Parabolic error compensation
First, we build a model of parabolic error as seen in Fig. 4.6. This optimal sequence can be found by tree structure in [11] (Fig. 4.6). The algorism is that to achieve lowest magnitude of error in 1x8 or 8x1 unary array. For 6 MSBs thermometer code, a 1×8 unary array with parabolic error is given in Table 4.1.
Three switching scheme are consider, first one is the sequential scheme and second is conventionally common-centroid, last is a optimal switching scheme presented by tree structure. Column 1 and 2 show the actual values of the elements in
the array and the relative error of each element. For example, with the common-centroid sequence, as the digital input increases from 1 to 8, the element with error -3% is switched on first and number 1, the element with error -3% is switched on next and numbered 2, and so forth. INL of the DAC can be calculated as shown in the last 2 columns of Table 4.1. The common-centroid sequence results in an INLDAC of 8% due to sever error accumulation. New switching scheme can further reduce the error by a factor of four.
Table 4.1 Switching schemes. (a) common-centroid (b) new switching scheme
The optimal sequence given in Table 4.1 is not unique. There are several other optimal sequences, two of which are obtained if the elements in the array (from the left to the right) are numbered 2 4 8 6 3 1 5 7 and 3 1 5 7 2 4 8 6.
4.6.2 Linear error compensation
As shown in Fig. 4.8, to suppress the linear erorr, some methods are that separating biasing for each quadrant of the current matrix, and splitting each current source into four units of quarter value. So that the 63 unit current source of the 6 MSBs are located in four symmetrical sub-matrix. All the digital circuits and interconnections between the switching matrix array and current sources array are put on top of the chip.
Fig. 4.8 The quarter symmetric and new switching scheme
4.7 Settling Time Condition
To obtain the settling time requirement, we use the single pole approximation to model the output node as shown in From Fig. 4.13. The worst case settling time
within 1/2LSB is derived as (4.3) and (4.4). To meet the specication in this work, we set M=10 and tsett = 2ns, such that the upper bound of equivalent capacitance value at output node to be 5.25pF when off chip RL = 50.
Fig. 4.9 Single pole approximation model for current cell
4.8 Bias Circuit
Fig. 4.10 shows the biasing scheme for the cascoded current sources. An internal resistor is used to generate the reference current. The NMOS sections of the biasing circuits are as “global biasing” while the PMOS sections are labeled as “local biasing.” In the actual implementation, the global biasing is realized using a common-centroid layout to reduce effects of gradients. The local biasing is separated into four quadrants. There is no direct connection between any two quadrants as shown in Fig. 4.10 (b).
(a) schematic
(b) floor plan of global and local bias Fig. 4.10 Bias circuit
4.9 Simulation Results
Pre-layout simulation Results
The static specification DNL/INL need less than 0.5LSB to achieve accurate required. Pre-simulation results is in the condition of (fin/fck = 250M/500M), and shown in Fig. 4.11, DNL = 0.03LSB, INL = 0.042LSB. SFDR is 80 dB @ fin/fck = 50MHz/ 500MHz.
0 200 400 600 800 1000 1200
-0.04
0 200 400 600 800 1000 1200
-0.04
Fig. 4.11 Pre-layout simulation for (a)DNL (b) INL
0 0.5 1 1.5 2 2.5
Fig. 4.12 Pre-layout simulation for SFDR=80dB @ fin/fck = 50MHz/ 500MHz
Version 1 of Layout Diagram
This thesis is implemented in TSMC 0.18um 1P6M CMOS technique, the layout of core area is 0.25mm2 and 0.58mm2 with PAD. The layout diagram is shown in Fig.
4.13.
The static specification DNL/INL need less than 0.5LSB to achieve accurate required as shown in Fig. 4.14. DNL = 0.25LSB, INL = 0.27LSB.
Fig. 4.13 Version 1 of Layout Diagram
0 200 400 600 800 1000 1200
-0.2 -0.1 0 0.1 0.2 0.3
input code
DNL (LSB)
0 200 400 600 800 1000 1200
-0.2 -0.1 0 0.1 0.2 0.3
input code
INL (LSB)
Fig. 4.14. Post-layout simulation for Version 1 of (a)DNL (b) INL
The 2048-point FFT of the post-simulation result is shown as Fig. 4.15 (a) 55dB
@ fin/fck = 1MHz/500MHz, SFDR (b) SFDR is 47 dB fin/fck = 250MHz/500MHz
0 50 100 150 200 250
-120 -100 -80 -60 -40 -20 0
Frequency [MHz]
Output spectrum [dB]
X: 214.9 Y: -56.02
0 50 100 150 200 250
-120 -100 -80 -60 -40 -20 0
Frequency [MHz]
Output spectrum [dB] X: 18.52Y: -46.96
Fig. 4.15 Post-layout simulation for Version 1 of SFDR
The package type is LCC type 68 pins where the actual chip photograph is shown at Fig. 4.16.
Fig. 4.16 Version 1 of die photograph
The specification of post-layout simulation drop a lot by compared with pre-layout simulation. The main question is the parasitic capacitors between switch pair and the output node. There are 4+63 metal lines that connect to the switch pairs and output node .Those capacitors cause the timing skew and non-synchronization. So,
we need short the connecting line to get small capacitor.
The other problem is the input buffer consideration. The measurement of version
1 is presented in Chapter 5
To solve above two problems, we design the version 2 of layout diagram which includes minimizing metal line between each current cell and output node and adding input buffer in the front of DAC core circuit.
Version 2 of Layout Diagram
The
version 2 of layout diagram is shown in Fig. 4.17. The ESD pad is used in
this version. The metal of each current cell output is minimized to reduce the non-equal capacitors. We have add the input buffer to drive the input loading. The core area is only 0.175mm2 and 0.65mm2 with ESD pad.The