Chapter 1 Introduction
1.5 Organization of This Thesis
In this thesis. We bring up the new process to enhance the strain engineering.
We discuss the effects of fluorine incorporation into the passivation of strained-si HfO2/SiON gate stack n-MOSFETs, evaluated in terms of reliability and performances. In this chapter, we introduce the reason of the high-k dielectrics and the strain engineering on CMOS technology and discuss the effects of fluorine incorporating on MOSFETs with strained-Si high-k gate dielectric stacks, this thesis is organized as follows:
In chapter 02, we discuss the theoretical characteristics of strained-Si technology. Besides, hot carrier reliability is also discussed.
In chapter 03 we describe the experimental process flow for fabricating
HfO2/SiON gate stack nMOSFETs test devices with different passivation. Then, show basic electrical performance, i.e. I-V characteristics, and presents the effects of FSG passivation dielectric on strained-Si HfO2 n-MOSFET reliability.
In chapter 04, we bring up conclusions for these experimental results above . Some advices for the possible future researches are suggested in this area.
Fig .1- 1Measured and simulated Ig-Vg characteristics under inversion conditions of SiO2 nMOSFET devices.
Fig .1- 2 Using high-k material can suppress gate direct-tunneling current.
Table 1- 1 2009 ITRS roadmap for high performance devices
Table 1- 2 2009 ITRS roadmap for low operating power device
Table 1- 3 2009 ITRS roadmap for low standby power devices
Chapter 2
Local strained-Si on HfO
2/SiON nMOSFETs
2.1 Mobility degradation by high-k materials
In the future, High-K insulators will be utilized as gate dielectric films for advanced CMOS devices. But one of main problems of the high-K MOSFETs is reduced carrier mobility compared with that of thermally grown pure SiO2 MOSFETs because of the uncompleteness on high-k film itself (see Fig. 2-1). The research reveal that the electron mobility degradation for HfSiON MOSFETs [36] (see Fig. 2-2) and find that two sources of the mobility degradation: one is Coulomb scattering caused by fixed charges in High-k films and the other is phonon scattering by interfacial thin oxynitrided (SiON) layer.
2.2 Mobility enhanced by local strained-si
In order to improve the degradation mobility caused by High-k gate stacks, strained-Si are required to improve drive current. When deciding on a strained-Si process flow, it is first necessary to comprehend the potential magnitude for electron versus hole mobility enhancement and whether the mobility enhancement results from
relationship for semiconductors depends on nearest neighbor atomic spacing, certain stress (in particular shear stress) warps the valence bands (although less so for conduction band but some warping for shear stress) [38]. The warping of the valence band provides dramatic changes to the constant-energy surfaces in k space and can lead to large hole mobility enhancement via reduced conductivity mass in the channel direction. Mobility enhancement via reduced mass (as opposed to reduced scattering) is key in nanoscale MOSFETs and often not appreciated. Only mobility enhancement from reduced mass (unlike reduced scattering) is maintained at the very short 15–20-nm channel lengths (35-nm gate length) devices currently in production. A strained-Si flow, which is scalable for multiple technology nodes, thus, needs to focus on reducing the hole conductivity mass with the goal of improving the n/p ratio from
~2 to ~1. Therefore, we first focus on strain-enhanced hole mobility from reduced conductivity mass. As a starting point, it is helpful to visualize the effect of strain on the valence-band constant-energy surfaces in k space for bulk Si. Fig. 2-3 [37] shows the surfaces obtained using six band k • p and band parameters in [39]. The strain-altered surfaces for the top two bands are shown at 1 GPa for the common stresses of interest: longitudinal compression on (001) and (110) hybrid wafer orientation and biaxial tensile stress. Note from the constant-energy surfaces in Fig.
2-3, the heavy and light hole bands lose their meaning and we label the bands (first,
second, etc.) in this paper. Some important differences in the band structure under the various stresses at 500 MPa are summarized in Fig. 2-4 [37] for the in-plane and out-of-plane conductivity effective masses and density of states at the band edge.
Before covering strain-altered hole mobility calculations, we will briefly cover a qualitative model for strained-enhanced electron mobility since the concepts are
similar for electrons and holes. The electron mobility in bulk strained- Si along <110>
direction is determined by occupation and scattering in the Δ2 and Δ4 valleys and can
be expressed as:
where q, n, τ , and m are the electron charge, concentration, relaxation time, and
conductivity mass in the MOSFET channel direction, respectively. Strain improves the mobility by increasing the electron concentration in the Δ2 valley. The
repopulation improves the average in-plane conductivity mass (unstressed: mt = 0.19m0 versus ml = 0.98m0) and some further improvement is possible for stresses that warp the conduction valleys and lower mt [38]. Reduced intervalley scattering by the strain-induced splitting between Δ2 and Δ4 plays some role (enhances long channel mobility) when the splitting becomes comparable or larger than the optical phonon energy. In addition to a low in-plane mass, a high out-of-plane mass for the Δ2 valley
(taken as the z-direction in this paper) is quantized. This quantization in addition to strain alters the position of the energy levels. The quantization leads to bands becoming subbands since only discrete wave vectors kz are allowed. Including quantization, the total inversion-layer electron energy is given by discrete values of energy (En) added to the electron energy in the x- and y-directions (in the plane of the MOSFET) [40]
Each step in energy is called a subband with En the energy of the bottom of the subband. As an example, self-consistent solution of Schrödinger and Poisson equation for 500 MPa of uniaxial tensile stress and an inversion-layer vertical field of 1 MV/cm gives the energy levels, as shown in Fig. 2-5 [37]. Since the subband separation is greater than kT, nearly all the electrons in most cases occupy the bottom
two subbands [ground state n = 0 typically called Eo (from Δ2) and Eo’ (from Δ4)]. The ground state energy is significantly lower for the Δ2 valleys because of the higher quantization mass (Δ2: mz = 0.98m0 versus Δ4: mz = 0.19m0) which leads to increased
splitting between the bottom two subbands and confinement and strain splitting being additive (for the common biaxial and uniaxial tensile stress). The strong confinement in an MOSFET shifts the energy levels more than the moderate 500-MPa stress
mass in the bottom subband (top subband for holes) is an important requirement for the strainaltered band structure. Lastly, in addition to a low in-plane and high out-of-plane effective mass, a high in-plane mass perpendicular to the channel direction is also important. The density of states per unit area for the quantized system is , which results in the density-of-states mass approximated by . Though strain does not significantly alter the electron subband density of states, as discussed next, a high will be shown to be important for maintaining a hole concentration in the top subband. Similar to strained-enhanced electron mobility, hole mobility in an inversion layer can qualitatively be described as resulting from occupation and scattering in the top two bands
However, hole transport is more complicated since strain significantly warps the valence band (as seen in Fig. 2-3) altering both the in- and out-of-plane mass and
. Further, the mass changes with stress and is not constant in k space. After the previous discussion on strain-enhanced electron transport, an advantageous strain for holes needs to warp the valence band to create both a low in-plane and high out-of-plane mass and, if possible, a large mass in the plane of the MOSFET
perpendicular to the channel direction (creates a large ).
2.3 Local strained-si induced Serious hot carrier injection phenomenon
We had discussed that strain-si can enhance the device mobility described as above, but it will create serious hot carrier injection. Fig 2-6 demonstrated that after added strain-si technology, enhance si-channel mobility and enhance the electron velocity near drain site, then give electron more energy, and will induce high probability to impact ionize (see Fig 2-7), results in serious hot carrier injection.
At chapter one, we had discussed that incorporating fluorine can give resistence to hot carrier (see Fig 2-8), so now we design a new experiment that we can enhance mobility and reduce the serious HCI effect by incorporated fluorine into strained-Si High-k gate stack devices.
Fig. 2- 1 Schematic representation of factors contributing to carrier mobility degradation in a high-k oxide layer.
Fig. 2- 2 Measured effective electron mobility for HfSiON MISFETs and pure SiO2 MOSFETs as a function of effective field at 300-423K.
Substrate concentration NA is 3 x 1016 cm-3.
Fig. 2- 3 Hole constant-energy band surfaces for the top band obtained from six-band k • p calculations for common types of 1-GPa stresses: (a) unstressed, (b) biaxial tension, (c) longitudinal compression on (001) wafer, and (d) longitudinal compression on (110) wafer (note significant differences in stress induced band warping altering the effective mass).
Fig. 2- 4 Summary of key valence-band parameters for top and second band for bulk Si under 500-MPa stress. The conductivity and density of states effective mass is listed at gamma point. Uniaxial compression is longitudinal along <110> channel direction (note significant differences for in-plane, out-of-plane, and density-of-states masses).
Fig. 2- 5 Conduction valley energy-level splitting under 500 MPa of longitudinal uniaxial tensile stress: Bulk and MOSFET inversion layer (1 MV/cm). Note that energy-level splitting from inversion-layer confinement is larger than strained.
Fig. 2- 6 Simulated electron velocity along the channel of 0.1 um nMOSFET.
Fig. 2- 7 Hot electrons and hot holes can be injected into oxide with the aid of vertical field, or with their own kinetic energy
Fig. 2- 8 Fluorine repair the defect in gate and channel, and give the resistance to stress because of its strong binding energy.
Chapter 3
Experimetal Result and discussion of Local strained-Si HfO2/SiON nMOSFETs with FSG
passivation layer
3.1 Experiment
This experiment construct simple HfO2/SiON gate stack nMOSFETs with SiO2
passivation layer deposited by TEOS source liquid for control, and with Nitride passivation layer for local strained-Si effect, and Nitride passivation layer with added FSG passivation layer on underside for Fluorine incorporated effect.
Fig.3-1 shows the experimental process flow of the nMOSFET with HfO2/SiON gate dielectric. The nMOSFETs were fabricated on 6-inch p-type (100) Czochralski (CZ) silicon (Si) wafer utilizing a conventional self-align process, followed by the standard RCA cleaning with a hydrofluoric (HF) acid-last process.
Prior to the HfO2 gate dielectric deposition, less than 1 nm interfacial SiON was grown by rapid thermal processing in the nitrous oxide (N2O) ambient at 800°C for 30 s. The 3 nm HfO2 gate dielectric was subsequently deposited by the AIXTRON metal organic chemical vapor deposition system at 500°C, followed by post deposition
200 nm poly- Si gate was then deposited by low-pressure chemical vapor deposition system using silane (SiH4) gas at 620°C. After gate electrode patterning by I-line lithography stepper and subsequently phosphorous implantation at 20 keV, 5 x1015 cm2 dose, dopants were then activated at 950°C for 30 s in N2 ambient. Afterward, wafer split into SiN capping, FSG buffer layer and control samples by varied passivation layer , and all passivation layer deposited using the plasma-enhanced chemical vapor deposition (PECVD) (see Fig. 3-2) system at 300°C. SiN capping sample deposited 300nm nitride and 100nm SiO2, FSG buffer layer sample deposited 20nm FSG ,300nm nitride and 100nm SiO2 , and control sample deposited 400nm for reference (see Table 2-1). Nitride passivation layer was deposited at the SiH4 , NH3, N2 ; FSG passivation layer was deposited at the SiH4, N2O and CF4, and undoped SiO2 passivation layer was deposited at the O2 and TEOS source gas. Varied passivation was used to investigate the effect of incorporated fluorine on local strain-Si HfO2/SiON device performances. Finally, contact holes etching and metallization Ti-TiN-AlSiCu were performed using standard CMOS process, followed by 400°C sintering for 30 min in N2 ambient. Fig 3-3 illustrate schematic cross section of HfO2/SiON n-MOSFETs with different passivation layer. Fig 3-4 illustrate F atoms diffuse into channel after sintering.
3.2 Measurement setup
Basic electrical characteristic such as I-V were measured by a HP4156A precision semiconductor parameter analyzer (see Fig 3-5).
In CVS reliability at room temperature and 100oC measurements, devices were stressed with the drain voltage set at 0.1 voltage, and the gate voltage biased at threshold voltage plus 3 voltage, and monitor the constant voltage degradation before and after stress. To find the condition, we first measured the ID –VGS characteristics with drain terminal was biased at the 0.1 voltage, and voltage found by current defined method (see Fig 3-6a).
In HCS reliability at room temperature and 100oC measurements, devices were stressed with the drain voltage set at a highly positive voltage, and the gate terminal was biased at the voltage where maximum absolute value of Isub occurred to accelerate the degradation. To find the condition, we first measured the Isub –VGS
characteristics with drain terminal biased at a given voltage. Besides, In order to identify the worst degradation condition, VGS = VGS@Isubmax (channel hot electron, CHE) was used to monitor the degradations of our devices for hot electron stressing.
To monitor the hot electron degradation, both the ID –VGS characteristics at VDS = 0.1V (linear region) and damages were monitored before and after the stress. The degradations in terms of threshold voltage shift (△Vth) were examined and recorded in
the accelerated stress test (see Fig 3-6b).
Additionally, in order to monitor the charge de-trapping effect, we set HCI stress/relaxtion with a 600 seconds HCI stress described as above and 600 seconds relaxtion voltage VGS=-2V, and 600 seconds HCI stress again to mention threshold voltage shift (see Fig 3-7).
3.3 Result and discussion
3.3.1 Electrical characteristics of high-k gate stack nMOSFETs with different P.L.
At Fig. 3-8, the SIMS profile shows that the Fluorine concerntration at gate higher than at HfO2/Si-channel interface, this means fluorine diffuses into gate and channel, and at Fig 3-9, from Hf track we can see that after fluorine diffused into gate, Hf-O binding energy become higher, at Fig 3-10, from F track we can see at 684eV binding energy has high peak shows that fluorine is indeed diffuse into gate and channel, and at 689eV has a small peak shows that because of the source gas of FSG buffer layer is CF4, carbon also diffuse into gate and channel and form some organic compounds. Fig. 3-11 shows the gate leakage current of HfO2/SiON gate stack n-MOSFET with different passivation under both inversion and accumulation modes.
It can obviously noted that with FSG buffer passivation layer and SiN capping
passivation layer because of Fluorine and Nitrogen passivate the defect at High-k gate, the leakage current is significantly suppressed. Fig.3-12 demonstrates the transconductance (Gm) and the linear region drain current as a function of gate voltage for different samples. The peak transconductance is 6.6%, 21.5% for SiN capping and FSG buffer samples respect to control sample, and the improved normalized linear drain–current ID which SiN capping sample is 9.8% higher above than control samples and the FSG buffer sample is 22.9% higher than control samples, indicating that fluorinated strained-si HfO2 has better interface characterization. Fig.
3-14 presents the excellent output drive current characteristics (ID-VDS) under various normalized gate biases (VGS-VTH), which almost 12% enhancement in magnitude of ID,SAT for FSG buffer sample with respect to control sample. The improvements are believed to be intimately related not only to the better interface quality but also to the reduced bulk trap density. Fig 3-13 indicates the transconductance of devices with different passivation layers as a function of channel length. And we find that transconductance for FSG buffer sample shows the better interface states than SiN sample and control sample. Thus, the strain-si technology will improve the transconductance in device, and FSG buffer layer can further improve it. In short, Table 3-2 and Fig 3-15 demonstrate that all fundamental electrical properties, including the threshold voltage, linear region drive current, saturation region drive
current, transconductance, swing, gate leakage current between the three splits with control, SiN capping and FSG buffer layer samples. We can see that local strain technology can improve electrical performance, and added FSG buffer layer can further improve them.
3.3.2 Reliability characteristics of high-k gate stack nMOSFETs with different P.L.
First, we focus on reliability characteristics of HfO2/SiON gate stack n-MOSFETs with different samples under constant DC stress condition. Fig. 3-16 and Fig. 3-17 compares the threshold voltage and ID,lin variations as a function of stress time for the different samples, respevtively. Fig. 3-18~20 shows the 100oC CVS with control, SiN capping, FSG buffer samples, respectively. We can see that compared to control sample, SiN capping sample have more resistance to CVS under 25oC and 100oC, and FSG buffer layer sample have advanced resistance compared to SiN capping sample. It is beleived that damage under CVS stress mainly comes from High-k bulk defect, so now we know when we only capping SiN, nitrogen can passivate the bulk defect; when we use FSG buffer, and the fluorine can passivate the bulk defect.
Secondly, we discuss the hot carrier injection stress. Fig. 3-21 shows that
strain-si induced more impact iozination, and they cause more Isub. Fig. 3-22 and Fig.
3-23 compares the threshold voltage and ID,lin variations as a function of HCI stress time for the different samples, respevtively. We can see that SiN capping sample suffer serious HCI damage than control sample, and FSG buffer sample can enhance HCI stress resistence under strain-si technology. It is beleived that damage under HCI stress mainly comes from High-k/Si-channel interface state, so now we know when we only capping SiN, hydrogen will passivate the bulk defect, but easily be damaged under stress, and when we use FSG buffer, this FSG buffer layer prevent the following hydrogen diffusing, and the fluorine can passivate the interface state defect.
Third, we discuss the ten year using straight line, Fig. 3-24 and Fig 3-25 shows added FSG buffer sample has better ID,SAT and Time-to-breakdown profiles Fourth, we discuss the voltage shift and relaxation under HCI stress, Fig 3-26 shows the results, and Fig 3-27(a-c) shows the mechanism with control sample, SiN capping sample, FSG buffer sample, respectively. Compared to control sample, SiN capping sample has more defect and release less electrons under relaxation phase, and FSG buffer sample can has less defect and release less electrons.
Now the experimental results reveal that the fluorine incorporated by FSG buffer layer can enhance the reliability. Because when fluorine diffuse into gate bulk and channel interface (shown in Fig. 3-28), they can form Si-F and Hf-F bonds, and
these bonds has strong binding energy, can give the resistence to CVS and HCI stress.
3.4 Summary
In this work, we show the experimental electrical properties of the devices with different passivation layer, significant device performance improvement in devices with FSG buffer P.L. were found, such as the excellent subthreshold swing, increased transconductance, higher current drive, as compared to the control TEOS sample and SiN capping sample. It was observed that incorporated fluorine can repair the defects
under the local strain-Si technology, further improve the device performance.