Chapter 2 Local strained-Si on HfO 2 /SiON nMOSFETs
3.4 Summary
In this work, we show the experimental electrical properties of the devices with different passivation layer, significant device performance improvement in devices with FSG buffer P.L. were found, such as the excellent subthreshold swing, increased transconductance, higher current drive, as compared to the control TEOS sample and SiN capping sample. It was observed that incorporated fluorine can repair the defects
under the local strain-Si technology, further improve the device performance.
And we also observe that serious degradation such as interface state trap, bulk trap density result in threshold voltage shift occurs in the control sample. The CF4-introduced silicon oxide as a FSG buffer layer showed that improved reliability characteristics under the CVS and HCI. It is believed that the CVS and HCI degradation are related to the electron traps in gate dielectrics. As compared to the control sample, the SiN capping sample suffer serious hot carrier injection, and The FSG buffer layer sample leading to the formation of stronger Hf-F and Si-F bonds compared to Hf-H and Si-H bonds reduced charge trap generation rate. These stronger bonds result in less interface states generation and charge trapping under CVS and HCS, which promotes better hot-carrier and CVS immunity against stress.
Fig. 3- 1 The process flow of n-MOSFETs with different
passivation layer.
Fig. 3- 2 The PECVD system used in this experiment.
Table. 3- 1 Conditions of samples with different passivation layers.
SiO2: 300sccm O2, 50sccm TEOS, 500mTorr, 40W, 300oC
NITRIDE: 20sccm SiH4, 20sccm NH3, 980sccm N2, 850mTorr, 20W, 300oC FSG: 5sccm SiH4, 90sccm N2O, 20sccm CF4, 1Torr, 11W, 300oC
3000A NITRIDE stress degree: 3.366x102 MPa Tensile stress
200A FSG+3000A NITRIDE stress degree: 3.028x102 MPa Tensile stress
Fig. 3- 3 Cross section of HfO2/SiON n-MOSFET with different passivation layer.
Fig. 3- 4 In FSG buffer P.L. devices, a large amount of F atoms
incorporating to passivating the bulk and interface trap charges
Fig. 3- 5 The experimental setup for the basic electrical
characteristics and long-term reliability test measurements.
Fig. 3- 6 Basic measurement method for (a) CVS (constant voltage stress), and (b) HCI (hot carrier injection stress).
n+
Fig. 3- 7 HCI stress and relaxtion measurement method
0 5 10 15 20 25 30
Fig. 3- 8 SIMS profiles shows that Fluorine diffuse into gate and channel
21 20 19 18 17 16 15 14 13
Fig. 3- 9 XPS shows that after sintering, fluorine enhance Hf-O binding energy under Hf4f track
680 682 684 686 688 690 F 1S of the HfO2
Intensity (arb. unit)
Binding Energy (eV)
Fig. 3- 10 XPS shows that fluorine diffuse into gate and channel, and some carbonized organic compounds.
Fig. 3- 11 Gate leakage current as a function of gate voltages of
HfO2/SiON gate stack with different passivation both under inversion and accumulation regions
-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
Fig. 3- 12 Drain current and transconductance as a function of gate voltages of HfO2/SiON gate stack with different passivation
0.2 0.4 0.6 0.8 1.0 1.2
Fig. 3- 13 The maximum transconductance versus channel length for all splits of HfO2/SiON gate stack n-MOSFETs.
Fig. 3- 14 Drain current versus drain voltage (ID-VD) curves of different P.L. under various normalized gate biases which 0V, 0.375V, 0.75V, 1.125V, and 1.5V,respectively.
Table. 3- 2 Electrical performance of samples with different passivation layers.
Fig. 3- 15 Enhanced percentage of electrical performance of samples with different passivation layers
0 5 10 15 20 25 30
SiN capping FSG buffer
Enh anced p er cen tag e(%)
S.S.
GMmax Id,lin Id,sat
0 200 400 600 800 1000
Fig. 3- 16 Vth shift degree under CVS stress for different samples at 25°C
Fig. 3- 17 Drain current degradation degree with different samples under CVS stress
0 1 2
Fig. 3- 18 Vth shift degree with control sample under 100oC CVS
0 1 2
Fig. 3- 19 Vth shift degree with SiN capping sample under 100oC CVS
0 1 2
Fig. 3- 20 Vth shift degree with FSG buffer sample under 100oC CVS
1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
Fig. 3- 21 Substrate current versus gate voltage for both samples of HfO2/SiON gate stack n-MOSFETs.
0 200 400 600 800 1000
Fig. 3- 22 Vth shift degree under HCI stress for different samples at 25°C
1 10 100 1000
Fig. 3- 23 Drain current degradation degree with different samples under HCI stress
0 10 20 30 40 50 60 70 80 90 100 sample better than SiN capping sample and control sample
0 1 2 3 4 5 6 7
Fig. 3- 25 Comparison of TBD lifetime projection as a function VGS of FSG buffer layer sample larger than SiN capping sample and control sample
Fig. 3- 26 Threshold voltage shift with de-trapping bias –2 V dependence after hot carrier stress on both samples.
(a)
(b)
(c)
Fig. 3- 27 Schematic explanation of stress and relaxation process with different bias conditions for (a) Control (b) SiN capping (c)FSG buffer samples
Fig. 3- 28 The Mechanism of Fluorine Incorporation to Improve Reliability Issue
Chapter 4
Conclusions and Suggested Future Works
4.1 Conclusions
Local strained-Si HfO2/SiON nMOSFETs with appropriate fluorine distributed close to the surface were investigated. We propose an alternative approach for forming an excellent new generation devices is demonstrated.
In this thesis, the effect of fluorine on the local strained-Si HfO2 gate stack were investigated. Several important phenomena were observed and summarized as follows:
First we have investigated its basic electrical properties. The novel strained-Si high-k device with FSG passivation layer to enhance the electrical characteristics due to fluorine passivation effect. This is attributed to the reduction of the interface state and bulk trap density in HfO2/SiON gate stack. Then we investigate the reliability such as the CVS and HCI mechanisms of polysilicon gate and HfO2 gate dielectric with nitride passivation and FSG passivation. It is believed that CVS degradation are mainly related to the electron traps in high-k dielectric bulk, and HCI degradation are mainly related to the electron traps in interfacial state, resulting in threshold voltage
because of bandgap narrowing effect induced by the channel strain. The fluorine diffused from added fluorinated silicate oxide under nitride passivation promotes the CVS and HCS immunity due to the formation of the rather stronger Si-F bonds in not only the HfO2 bulk but also the interface including channel and near S/D side. In research report reveal that fluorine incorporation from the CF4 gas is effective in suppressing bulk defect, thus reducing threshold voltage instability. Stress induced Vth
shift and its relaxation characteristics under the de-trapping (negative) gate bias under HCI stress has beed studied. The reversible electrons do not generate structural damage in the dielectrics, and can be de-trapped. However, the residual electrons trapping indicate permanent damage. And we can observe that , for the locally strain passivation layer, hot carrier induced permanent damage is significant severer than reversible cold carrier trapping.
4.2 Suggestion for Future Works
There are many issues and measurement skills that we can’t discuss completely.
We list some goals for future work as follows.
1. Fast transient pulsed Id-Vg measurement is also used to evaluate charge-trapping phenomena precisely.
2. How much flow rate of CF4 gas can makes the FSG passivation layer optimixed
that will not deteriorate the device and result in the degraded performance and reliability.
3. HRTEM is essential to verify real thickness and estimate value of the dielectric constant for HfO2/SiON gate stack.
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