The organization of this thesis is overviewed as follows. Chapter 2 gives some basic concepts in VGA Design. Chapter 3 introduces the novel high dynamic range VGA technique and compares with the reference technique. Chapter 4 describes the design of each building block and analyzes the simulation result. The low power UWB VGA is implemented in 0.18µm CMOS technology and performs excellent in measurement results in Chapter 5.
Chapter 6 concludes with a summary of contributions and suggestions for future work.
Chapter 2
Basic Concepts in VGA Design
This chapter presents some basic concepts in variable gain amplifier which are fundamental of the following chapters. Beginning with introduction to gain variation techniques, section 2.1 describes several basic VGA topologies. In section 2.2, the relationship between the linear-in-dB VGA and the constant settling time of auto gain control (AGC) loop will be discussed. Section 2.3 gives a pseudo-exponential gain control topology.
2.1 Basic VGA Topologies
The four basic gain variation techniques are shown in fig. 3. Our study of differential pairs reveals two important aspects of their operation: (1) the small-signal gain of the circuit is a function of the tail current and (2) the two transistors in a differential pair provide a simple means of steering the tail current to one of two destinations. By the combining these two properties, we can develop a versatile building block such as fig. 3 (a) and fig. 3 (b).
We want to construct a differential pair whose gain is varied by a control voltage. This can be accomplished as depicted in fig. 3(a), where the control voltage defines the tail current and hence the gain. In this topology, Av = Vout / Vin varies from zero (if ID3 = 0) to a maximum value given by voltage headroom limitations and device dimensions. This circuit is a sample example of a “variable-gain amplifier” (VGA). VGAs find application in systems
Figure 3 Basic topologies for gain variation.
where the signal amplitude may experience large variations and hence requires inverse changes in the gain[6].
In fig. 3(a), because the drain current of the M1,2 will be changed with the change of control voltage, since the output DC level will also be changed. Now suppose we seek an amplifier whose the sum of current can be constant under the different gain settling. Consider two differential pairs that amplify the input by opposite gains [fig. 4]. We now have Vout1 / Vin
= -gmR and Vout2 / Vin = +gmR , where gm denote the transconductance of each transistor in equilibrium. If I1 and I2 vary in opposite directions, so do |Vout1 / Vin| and | Vout2 / Vin |. Now, we combine Vout1 and Vout2 into a single output. As illustrated in fig. 3(b), the two voltages can be summed, producing Vout=Vout1 + Vout2 = A1Vin + A2Vin, where A1 and A2 are controlled
Figure 4 Two stages providing variable gain.
by Vc+ and Vc- [6]. The drain current of the M1,2 will be constant under this topology. The analysis will be derived as follow.
Fig. 3(b) to achieve the linear relationship between the VGA voltage gain and the control voltage VC,the Gilbert type four-quadrant multiplier is used since basically its outputs is equal to the product of the two inputs. The analytic form can be derived as follow. Assume all transistors operates at their small-signal mode, that is, the three differential pairs works as linear transconductor. If the transistor size of M3, M4, M5, M6 are all the same, namely, W/L.
Then the output voltage can be expressed as
( ) (
+ −)
We can see that under small-signal approximation, the output voltage is indeed proportional to the product of the two inputs and control voltage. It should be noticed, the relationship between the gain and control voltage will be linear-in amplitude. In the next section we will explain that the linear-in amplitude type VGA can not agree with constant settling time AGC loop. In order to satisfy the constant settling time theorem, we need the linear-in dB type VGA. Since fig. 3(c) and fig. 3(d) be developed.
In fig. 3(c) ，the transconductance of the source-coupled pair is varied by changing the resistance of the degeneration resistor Rs [7][8]. When the input signal is weak, small Rs is used to obtain high gain and low noise. When the input signal is large, large Rs is used to obtain low gain and high linearity. Thus, this topology can achieve constant signal-to-noise-and distortion ratio for the fixed output level regardless of the gain settings.
Fig. 3(d) shows a high-gain amplifier with resistor-network feedback. Its voltage gain be varied by changing the ratios of Rf1/R1 and Rf2/R2. High linearity can be achieved if the loop gain is large and the resistor network is linear [9]. However, if the conventional operational amplifier is used，the variation of the feedback factor results in variations of the bandwidth and the total harmonic distortion. When the circuit is designed to cover the worst-case scenario over the entire gain range, its power consumption is not optimized.
From fig. 3(c) and (d), the gain is varied by changing the resistance value. Under the appropriate design，the relationship between the gain and control voltage will show as linear in decibel，and will satisfy the constant settling time theorem. Although these two topology can change the appropriate resistance value to satisfy the linear-in dB characteristic，but in UWB system we need a wide dynamic range. In fig.3 (c) and (d) we need a lot of switches to control the differential resistor value. Too many switches will influence the accuracy of resistance value and cause a large parasitical capacitance in signal path. Since these topology are not suitable for a high dynamic and high speed VGA which is need for UWB system.
There is another technique which is called as "pseudo exponential VGA". We will discuss this technique in section 2.3 and explain that is more suitable for a high gain and high dynamic applications.
2.2 Constant Settling Time of AGC Loop
In Auto Gain Control systems as shown in Fig. 5, AGC circuits are widely applied.
Usually, error free recovery of data from the input signal cannot occur until the AGC circuit has adjusted the amplitude of the incoming signal. Such amplitude acquisition usually occurs during a preamble where known data are transmitted. The preamble duration must exceed the acquisition or settling time of the AGC loop, but its duration should be minimized for efficient use of the channel bandwidth. If the AGC circuit is designed such that the acquisition time is a function of the input amplitude, then the preamble is forced to be longer in duration than the slowest possible AGC circuit acquisition time. Consequently, to optimize system performance, the AGC loop settling time should be well defined and signal independent.
Figure 5 Block diagram of a front end circuit.
The AGC loop depicted in Fig. 6 consists of a variable gain amplifier (VGA), a peak detector, and a loop filter. The AGC loop is in general a nonlinear system having a gain
Figure 6 Block diagram of an AGC circuit.
logarithmic function shown in dotted lines and appropriate design of the loop components, the AGC system can operate linearly in decibels. This simply means that if the amplitude of the input and output signals of the AGC are expressed in decibels (dB), then the system response can be made linear with respect to these quantities. The derivations that follow will make these issues clear.
By the Fig. 6,the gain of the VGA, F(Vc) is controlled with the voltage signal Vc The peak detector and loop filter form a feedback circuit that monitors the peak amplitude, Aout, of the output signal Vout and adjusts the VGA gain until the measured peak amplitude ,Vp, is made equal to the DC reference voltage ,VREF. The output of the AGC circuit is simply the gain times the input signal: Vout(t) = F(Vc)Vin(t).
Since the feedback loop only responds to the peak amplitude, the amplitude of Vout is Ain
Vc F
Aout = ( ) (2-3) Where Ain is the peak amplitude of Vin.
The equivalent representation model of an AGC circuit, shown in Fig. 7, is derived as follows. First, the feedback loop of an AGC circuit only operates on signal amplitudes; hence the AGC input and output signals are represented only in terms of their amplitudes Ain(t) and Aout(t) respectively. Second, since the VGA multiplies the input amplitude, Ain, by F(Vc) as shown
Figure 7 Model of generalized AGC circuit.
in (2-3), an equivalent representation is
⎥⎦
⎢ ⎤
⎣
⎡ +
= exp ln[ ( )] ln( )
1 1
v
v P
Vc Ain F P
Aout (2-4)
Pv1 is a constant with the same units as Ain and Aout (e.g., volts). The AGC model in Fig.
7 uses (2-4), but duplicates the Pv1 exp() function inside and outside the outlined block so x(t) that y(t) and represent the input and output amplitudes of the AGC, expressed in decibels within a constant of proportionality. Similarly, the z input shown is the value of VREF
expressed in dB within a constant. The peak detector in Fig. 6 will be assumed to extract the peak amplitude of Vout(t) linearly and much faster than the basic operation of the loop so that Vp=Aout. Hence, the peak detector is not explicitly shown in Fig. 7. Finally, the loop filter in Fig. 6 is shown as an integrator in Fig. 7, with H(s) = GM2/sC.
The model in Fig. 7 helps to simplify the mathematical derivations in this section and aids intuition. Constant settling time operation of the AGC circuit simply requires that the
system enclosed in dotted lines with x(t) input and output y(t) be linear. Since x(t) is the input amplitude, Ain(t) in decibels and y(t) is the output amplitude Aout(t) in dB, then a linear response from x(t) to y(t) means the AGC circuit’s amplitude response from input to output will be linear in dB.
The classical result for constant settling time of the AGC loop will be derived next and will include the logarithmic amplifier shown with dotted lines in Fig. 6. Results of these derivations will be used in the next section where generalized constraints for constant settling time are developed.
The output y(t) in Fig. 7 is The control voltage Vc is derived as
{
P e P e τ dτ
Taking the derivative of (2-5) and substituting in the derivative of (2-6), the following expression is obtained:
)]
Equation (2-7) describes a nonlinear system response of y(t) to an input x(t) unless constraints are placed on the functions. Many constraints exist, but here those with practical circuit implementations are analyzed. The first step toward obtaining a linear relationship between x(t) and y(t) is to force the coefficient in the second term of (2-7) to equal a constant, Px,
And equation (2-7) can be rewritten as
Equation (2-9) describes a first-order linear system having a high pass response from the input x(t) to y(t) the output The time constant,τ, of the system is given by
1 The classical criterion for constant settling time of the AGC loop assumes that GM2 and C are constants in (2-8) and (2-10), forcing the gain control function of the VGA to satisfy the following constraint:
Where PG2=eC is a constant of integration. One can easily determine that the gain in decibels (dB) should vary linearly with the control signal, Vc. Using (2-12) for an exponential VGA gain characteristic and (2-10), the time constant of the AGC loop with a logarithmic amplifier included, is show as equation (2-13).
2 With the constraints provided, the AGC loop will operate as a linear system in decibels for any change in input amplitude. By taking inverse of equation (2-13) and multiplying 2π，
we can get the It is the locked bandwidth of AGC loop.
z Without Logarithmic Amplifier
In many AGC systems, the logarithmic amplifier shown with dotted lines in Fig. 6 is omitted. The objective of constant settling time can still be met under certain small-signal approximations. The key assumption in the following derivation will be that the output amplitude of the AGC loop is operating near its fully converged state (ie. Aout ~ VREF) . Equation (2-7) can be rewritten as:
]
The system response is nonlinear even with a constant Px due to ey(t). If the changes in the input and output amplitude levels are small, then the exponential ey(t) in (2-25) can be expanded in a Taylor series. Assume that the AGC loop is initially converged, such that the output amplitude, equals VREF Referring to Fig. 7， this implies that y(t)=z and the Taylor series expansion is
[
+ − +L]
≈ e y t z
ey(t) z 1 ( ) (2-16) And equation (2-16) can be represented as
)
That will be the same as equation (2-9), the first-order linear system is a high pass response with a time constant of
1
GM2 and C are linear and time invariant, then the constraint on constant settling time for the AGC loop is that the VGA has an exponential gain control characteristic as in (2-12).
Under these conditions, the AGC loop without a logarithmic amplifier has a time constant given by
From the above explanation, we can see that an exponential gain characteristic VGA is necessary for a constant settling time AGC loop [3].
2.3 Pseudo Exponential Technique
The exponential gain to linear control voltage characteristic is necessary for auto gain control loop to minimize variations in the output voltage and had be discussed in section 2.2.
In, CMOS devices, there is no logarithmic device characteristic which like bipolar device. In bipolar or BiCMOS technology, the exponential function is readily available with the base-emitter voltage to collector current characteristic. Here we present a methodology for generating the desired exponential transfer characteristics intrinsically using only MOS devices within the variable gain amplifier [9].
If the gain function is of the form ew, the exponential function can be approximated as equation (2-20).
Figure 8 Pseudo exponential gain versus control parameter.
The expression is plotted in Fig. 8, where the y scale is in dB’s. It is possible that the gain expression in equation (2-20) provides the necessary exponential transfer characteristics and shows good match for -0.7 < x < 0.7. Further, it can be shown that the maximum gain range is given by equation (2-21). Therefore, for a gain range of 30dB the value of x needs to be varied from -0.7 to +0.7. As just mentioned, the exponential characteristic matches fairly well within this range. Outside this region (-0.7 < x < 0.7) the rate of change in gain will be even more rapid.
Table1 lists the comparison between several methods. From the comparison result, we can see that the Pseudo exponential method is best choice for high speed linear in-dB variable gain amplifier.
Method dB-linear Speed cost
BJT device Yes High BJT(High)
Gilber cell NO High CMOS(Low)
Switch resistance Yes Medium CMOS(Low)
Pseudo exponential Yes High CMOS(Low)
Table 1. Comparison between several VGA method
Chapter 3
Novel High Dynamic Range Technique
This chapter presents a novel variable gain amplifier (VGA) circuit for high dynamic range applications. Section 3.1 addresses one example of pseudo-exponential topologies to approximate its gain polynomial to exponential. The proposed VGA will employ the concept of the referenced circuit as shown in section 3.1. The proposed pseudo-exponential gain control technique is presented to enhance the gain range and is described in section 3.2. The comparison between conventional methodology and proposed methodology will be shown in section 3.3.
3.1 Conventional Approach
A conventional topology for pseudo-exponential gain control using MOS transistors had been developed as shown in Fig. 9 [5]. The amplifier can be treated as a source-couple pair with diode connected load. The output impedance is determined by the diode connected load (1/gm) since the gain will be equivalent to input and load transconductance ratio.
The conventional circuit consists of three parts, namely, gain cell (M1-M8), gain control clock (M11-M14) and common mode feedback. The gain cell possesses the pseudo exponential gain transfer curve with respect to the linear gain control signal that is generated from the gain control cell. Common mode feedback circuit is used to stabilize the output
Figure 9 Schematic of the conventional variable gain amplifier.[5]
common mode level because all circuits are fully differential structure.
To control amplifier gain, the transconductance of MOS input and load transistor is varied with the change of control current. The currents through input pair and load are constant and equal to the current of upper PMOS (M7 and M8). The gain control block is formed by another PMOS source couple pair (M11 and M12). The gain control mechanism can be achieved by mirroring the gain control block differential output currents to the tail current source (M5 and M6) of input source coupled pair and load respectively. Current mirrors (M5, M6, M13, and M14) are long channel devices for good precision. The gain is hence proportional to the square root of the approximated polynomial as shown in equation (3-1).
Range:
15dB
Figure 10 Conventional circuit approximation on a decibel scale.
In equation (3-1), the transconductance of MOS input and load transistor varies with the change of current. The gain is hence limited by the square-root nature of the device. The maximum gain range is shown in Fig. 10 which is half of the ideal approximation equation since the gain is proportional to the square root of the approximated polynomial.
From Fig. 10, where variable x is the ratio of the additional current Ic to DC bias current Ib when control signal is applied. Equation (3-1) has the form like Equation (2-20) with power is 1/2. The polynomial matches a logarithmic function reasonably for parameter x up to ±0.7, however, with the power of 1/2 result in the maximum gain range is limited to about 15 dB per stage.
3.2 Proposed Approach
The proposed approach aims to improve the gain range by canceling the square-root of equation (3-1). In the conventional approach, the transconductance is varied with the change of control current, resulting in square-root relation. In the proposed method, we replace the controlled current with the varied voltage. The concept can be expressed as following:
Figure 11 The concept of the proposed methodology
The pseudo exponential technique is based on equation (1+x) / (1-x). If we control the gate voltage of NMOS and PMOS current source at the same time, we will increase (decrease) NMOS over driver voltage and decrease (increase) PMOS over driver voltage at the same time. For example is shown in Fig. 11, when ∆X is increased, Vgsn and Vsgp will be increased and decreased at the same time. Now we will apply this method to realize the pseudo exponential variable gain amplifier. Assume square law relation of drain current and gate-over drive voltage is applied, the transconductance isproportion to the over voltage of current source.
From equation (3-4), if we replace the control parameter with over voltage then the gain
Figure 12 Proposed technique.
will never limit by the square root again.
The proposed amplifier for enhancing maximum gain range of one stage is shown in Fig.
12. The gain circuit in the proposed topology is like the referenced VGA circuit, which a source-coupled pair serves as input transconductance stage, and diode-connected transistors are used for the loads. A DC-level shift block is applied for the suitable bias condition of NMOS and PMOS current sources. The ratio of input to load transconductances can be expressed as following:
)
From equation (3-5), the transconductances of input and load transistors are designed to vary in proportional to the change of the control voltage. By satisfying the condition as,
tp
Range:
30dB Range:
30dB
Figure 13 Proposed simulation on a decibel scale.
equation (3-5) can be further simplified.
From the above description, the pseudo exponential equation (1+x) / (1-x) is satisfied under the proposed method. The ideal simulation result is shown as Fig. 13 and the gain will be 30 dB dynamic ranges. We will make a comparison in next section and explain the benefit of the wide dynamic gain range.
3.3 Comparison
A. Gain Range
Figure 14 shows the comparison between the conventional pseudo-exponential polynomial, ideal logarithmic curve, and the polynomial of proposed approximation. This work fits the ideal exponential curve in the range of parameter x value between 0.7 and -0.7.
Figure 14 Real term generated by inductively source degeneration.
Since the gain of proposed topology is in proportional to (1 + x) / (1 - x) rather than its square root, the maximum gain range achieved is then doubled to about 30 dB. To get the
Since the gain of proposed topology is in proportional to (1 + x) / (1 - x) rather than its square root, the maximum gain range achieved is then doubled to about 30 dB. To get the