Summary

Table 7 summarizes the measurement result of wide band variable gain amplifier for voltage control (Meas. I) and digital control (Meas. II). It also lists the specification of our UWB system standard. The comparison between reference publications is shown in Table 8.

Since we reserve some design margin when we design circuit, although the measurement is not as well agree with the simulation, which is still a good result. The circuit is implemented in 0.18-µm CMOS technology, and the result is paving the way to a new generation of low power UWB applications.

Parameters Spec. Simulation. I(Voltage control) II(Digital control) Distortion -32dB(0.4Vpp) -40dB(0.47Vpp) -40dB (0.4 Vpp) -40dB (0.4 Vpp)

Control -- 0.93~1.3 V 0.9~1.25 V 6 bits

Noise 4.1nV/√Hz NF~18dB --

Table 7. Measurement Summary

Parameters This work VLSI 2001 [8] JSSC 2003 [9] JSSC 2005 [16]

Technology 0.18 um CMOS 0.25um CMOS 0.35 um CMOS 0.35 um CMOS

Power supply 1.8 V 2.5 V 3.3 V 3 V

6.79mW 20.79mW 39mW

Gain range 21.5 ~ 73 dB 5.6~17 dB 0~19 dB -7.78 ~79.79dB

Distortion -40dB (0.4 Vpp) 200MHz

Noise ~7.3nV/√Hz 16.75nV/√Hz 8.63nV/√Hz --

Table 8. Measurement Comparison

Chapter 6 Conclusions

This thesis has presented a linear-in dB topology employing a novel pseudo exponential technique for low power UWB VGA. It has enabled the implementation of a 230 MHz low power VGA in a 0.18μm CMOS technology. This novel topology has been applied to the analog front-end for the UWB direct conversion receiver which performs low power, wide bandwidth and wide dynamic gain range. In conclusion, the key contributions presented in previous chapters are summarized below.

6.1 Summary

A linear-in dB topology employing novel pseudo exponential technique has been presented for low power UWB VGA in Chapter 3 and Chapter 4. The novel technique improves the dynamic gain range per stage. Under this technique, we just need 2 stages VGA to implement the 50 dB gain rage. The lesser stages are used the lesser power consumption and release the bandwidth requirement for one stage. The VGA circuit implemented in 0.18-µm CMOS process shows a 230 MHz bandwidth in Chapter 5. The amplifier provides a minimum gain of 21.5 dB and maximum gain of 73dB while drawing 20.4 mW from a 1.8-V supply. If for a SOC application, the buffer is not needed in circuit and the power consumption will be about 9.4mW from a 1.8-V supply. A noise figure as low as 18

dB and a THD of -40dB (0.4Vpp at 200MHz) have been measured. In chapter 4, we also introduce a digital control function VGA (PGA). But the measurement gain range of this PGA is narrower than our expected and shows in Chapter 5. About this narrow dynamic gain range, we have discussed in Chapter 5. The gain error result is shows in Chapter 5, but the error correction has been explained and verified by the H-spice.

6.2 Recommendations for Future Work

In this thesis, there are some design considerations which are not paid an attention. We give some recommendations and improvement in this section. First, we don’t focus on noise analysis and the noise performance is not very satisfied in this thesis. Hence we must analyze about noise especial in high gain mode. Second, the digital control type VGA is usually needed in a modern communication system. In this thesis, we use the 6-bit Digital to Analog Converter (DAC) and a linear-load circuit to provide a digital control mode. The DAC will consume the extra power consumption. Hence the digital control can be designed as switching current source. By this kind of design, the control signals can direct to control current source and transconduct can also be directly controlled. Hence the current ratio of NMOS and PMOS source can be controlled more precise and save the extra power consumption. In Figure 20, the compensation circuit transistor Mr and capacitance of the common mode feedback amplifier may not be required after we analyze. We will make a correction in the future work.

Bibliography

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Publication List

1. Chao-Chun Sung, Mei-Fen Chou, Chang-Ching Wu, Che-Sheng Chen, Kuei-Ann Wen and Chun-Yen Chang, “Low Power CMOS Wideband Receiver Design” 16th International Conference on Microelectronics, pp. 287-290. Tunis, December 2004.

2. Chao-Chun Sung, Mei-Fen Chou and Kuei-Ann Wen, "Low Power CMOS Wideband Variable Gain Amplifier", Proc. IASTED Int. Conf. on Circuits, Signals, and Systems, Clearwater Beach, Florida, U.S.A., pp. 126-129, (November 2004).

Vita

Chao-Chun Sung

[email protected]

Chao-Chun Sung was born in Hsinchu, Taiwan, R.O.C., in 1981. He received the B.S. degree in electronic engineering from Fu Jen Catholic University, Taipei, in 2003. He worked toward the M.S. degree in electrical engineering at the National Chiao-Tung University, Hsinchu, Taiwan from 2003 to 2005.

His current research interests include analog front-end circuits for communications.

Education

M.S. Degree in Electronics Engineering, National Chiao Tung University 2005 B.S. Degree in Electronic Engineering, Fu Jen Catholic University 2003

住址: 苗栗縣竹南鎮仁愛路 1091 巷 5 號