Chapter 2 Basic Concepts in VGA Design
2.3 Pseudo Exponential Technique
The exponential gain to linear control voltage characteristic is necessary for auto gain control loop to minimize variations in the output voltage and had be discussed in section 2.2.
In, CMOS devices, there is no logarithmic device characteristic which like bipolar device. In bipolar or BiCMOS technology, the exponential function is readily available with the base-emitter voltage to collector current characteristic. Here we present a methodology for generating the desired exponential transfer characteristics intrinsically using only MOS devices within the variable gain amplifier [9].
If the gain function is of the form ew, the exponential function can be approximated as equation (2-20).
Figure 8 Pseudo exponential gain versus control parameter.
The expression is plotted in Fig. 8, where the y scale is in dB’s. It is possible that the gain expression in equation (2-20) provides the necessary exponential transfer characteristics and shows good match for -0.7 < x < 0.7. Further, it can be shown that the maximum gain range is given by equation (2-21). Therefore, for a gain range of 30dB the value of x needs to be varied from -0.7 to +0.7. As just mentioned, the exponential characteristic matches fairly well within this range. Outside this region (-0.7 < x < 0.7) the rate of change in gain will be even more rapid.
Table1 lists the comparison between several methods. From the comparison result, we can see that the Pseudo exponential method is best choice for high speed linear in-dB variable gain amplifier.
Method dB-linear Speed cost
BJT device Yes High BJT(High)
Gilber cell NO High CMOS(Low)
Switch resistance Yes Medium CMOS(Low)
Pseudo exponential Yes High CMOS(Low)
Table 1. Comparison between several VGA method
Chapter 3
Novel High Dynamic Range Technique
This chapter presents a novel variable gain amplifier (VGA) circuit for high dynamic range applications. Section 3.1 addresses one example of pseudo-exponential topologies to approximate its gain polynomial to exponential. The proposed VGA will employ the concept of the referenced circuit as shown in section 3.1. The proposed pseudo-exponential gain control technique is presented to enhance the gain range and is described in section 3.2. The comparison between conventional methodology and proposed methodology will be shown in section 3.3.
3.1 Conventional Approach
A conventional topology for pseudo-exponential gain control using MOS transistors had been developed as shown in Fig. 9 [5]. The amplifier can be treated as a source-couple pair with diode connected load. The output impedance is determined by the diode connected load (1/gm) since the gain will be equivalent to input and load transconductance ratio.
The conventional circuit consists of three parts, namely, gain cell (M1-M8), gain control clock (M11-M14) and common mode feedback. The gain cell possesses the pseudo exponential gain transfer curve with respect to the linear gain control signal that is generated from the gain control cell. Common mode feedback circuit is used to stabilize the output
Figure 9 Schematic of the conventional variable gain amplifier.[5]
common mode level because all circuits are fully differential structure.
To control amplifier gain, the transconductance of MOS input and load transistor is varied with the change of control current. The currents through input pair and load are constant and equal to the current of upper PMOS (M7 and M8). The gain control block is formed by another PMOS source couple pair (M11 and M12). The gain control mechanism can be achieved by mirroring the gain control block differential output currents to the tail current source (M5 and M6) of input source coupled pair and load respectively. Current mirrors (M5, M6, M13, and M14) are long channel devices for good precision. The gain is hence proportional to the square root of the approximated polynomial as shown in equation (3-1).
Range:
15dB
Figure 10 Conventional circuit approximation on a decibel scale.
In equation (3-1), the transconductance of MOS input and load transistor varies with the change of current. The gain is hence limited by the square-root nature of the device. The maximum gain range is shown in Fig. 10 which is half of the ideal approximation equation since the gain is proportional to the square root of the approximated polynomial.
From Fig. 10, where variable x is the ratio of the additional current Ic to DC bias current Ib when control signal is applied. Equation (3-1) has the form like Equation (2-20) with power is 1/2. The polynomial matches a logarithmic function reasonably for parameter x up to ±0.7, however, with the power of 1/2 result in the maximum gain range is limited to about 15 dB per stage.
3.2 Proposed Approach
The proposed approach aims to improve the gain range by canceling the square-root of equation (3-1). In the conventional approach, the transconductance is varied with the change of control current, resulting in square-root relation. In the proposed method, we replace the controlled current with the varied voltage. The concept can be expressed as following:
Figure 11 The concept of the proposed methodology
The pseudo exponential technique is based on equation (1+x) / (1-x). If we control the gate voltage of NMOS and PMOS current source at the same time, we will increase (decrease) NMOS over driver voltage and decrease (increase) PMOS over driver voltage at the same time. For example is shown in Fig. 11, when ∆X is increased, Vgsn and Vsgp will be increased and decreased at the same time. Now we will apply this method to realize the pseudo exponential variable gain amplifier. Assume square law relation of drain current and gate-over drive voltage is applied, the transconductance isproportion to the over voltage of current source.
From equation (3-4), if we replace the control parameter with over voltage then the gain
Figure 12 Proposed technique.
will never limit by the square root again.
The proposed amplifier for enhancing maximum gain range of one stage is shown in Fig.
12. The gain circuit in the proposed topology is like the referenced VGA circuit, which a source-coupled pair serves as input transconductance stage, and diode-connected transistors are used for the loads. A DC-level shift block is applied for the suitable bias condition of NMOS and PMOS current sources. The ratio of input to load transconductances can be expressed as following:
)
From equation (3-5), the transconductances of input and load transistors are designed to vary in proportional to the change of the control voltage. By satisfying the condition as,
tp
Range:
30dB Range:
30dB
Figure 13 Proposed simulation on a decibel scale.
equation (3-5) can be further simplified.
From the above description, the pseudo exponential equation (1+x) / (1-x) is satisfied under the proposed method. The ideal simulation result is shown as Fig. 13 and the gain will be 30 dB dynamic ranges. We will make a comparison in next section and explain the benefit of the wide dynamic gain range.
3.3 Comparison
A. Gain Range
Figure 14 shows the comparison between the conventional pseudo-exponential polynomial, ideal logarithmic curve, and the polynomial of proposed approximation. This work fits the ideal exponential curve in the range of parameter x value between 0.7 and -0.7.
Figure 14 Real term generated by inductively source degeneration.
Since the gain of proposed topology is in proportional to (1 + x) / (1 - x) rather than its square root, the maximum gain range achieved is then doubled to about 30 dB. To get the same gain control range, only half the numbers of amplifier stages are required by using the proposed topology. The reduction of cascaded stages not only reduces the power consumption but also increases the 3-dB bandwidth.
B. Bandwidth
Fig. 9 and Fig. 12 show the conventional and proposed VGA circuit. There are no high impedance nodes in the signal path. The only pole that limits the bandwidth of the VGA is at the output node. The bandwidth of this amplifier is determined by load transconductance and output node parasitic capacitance, as
out mload
BW C
g f RC
π
π 2
2
1 =
= (3-8)
Both conventional and proposed circuits apply the diode connected load. The bandwidth of circuits will be limited to the same condition as shown in equation (3-8). In the proposed
We can extend the bandwidth by increased the gmload, but the gain decreases at the same time.
C. Output Swing
In the conventional amplifier, there are three cascode devices which are composed of a NMOS tail current source, a PMOS tail current source and differential pair input stage with transconductance loads. The following equation proves the maximum output voltage swing constraint.
V Vt V
Vswing = DD − −3∆ (3-9) Where ∆V is the overdrive voltage for a device operated in saturation region. Assume Vt~0.5V, ∆V~0.3V and VDD=1.8. The Vswing will be 0.4 Vpp.
In the proposed amplifier, there are four cascade devices composed of a NMOS tail current source, a PMOS tail current source, input NMOS differential pair and PMOS transconductance loads. The four cascode devices will reduce the output swing. The output swing voltage will be shown as following equation.
V Vt V
Vswing = DD − −4∆ (3-10) Compared with the conventional circuit, the output swing a ∆V less. The Vswing will be 0.1 Vpp which is a very small voltage. The small output swing is a serious problem for system. In order to overcome this drawback, a post amplifier can be added after the VGA circuit. The overall architecture of VGA system will be discussed in chapter 4.
D. Gain Error
The gain error is related with the gain equation. The gain error of the equation (1 + x) / (1 - x) is double of the equation [(1 + x) / (1 - x)] 0.5 and the latter one has gain error about 0.5dB in appropriate design. Hence the novel pseudo exponential will get more gain error.
But in a wide gain range system, the dynamic gain range must more than 50dB. Total gain equation is [(1 + x) / (1 - x)] 2. Under the same gain equation, two circuits have the same gain
error.
3.4 Deep Submicron Effect
In 0.18µm CMOS process, since scaling has substantially deviated from the constant-field scenario, small-geometry devices experience significant mobility degradation.
An empirical equation modeling this effect is:
)
And the square-law current equation must be rewrite as:
0 2
We can drive the θ from the BSIM3V3 model Æ .Mobmod=2
2
Assuming θ(VGS-VTH)<<1, we obtain:
]
The pseudo exponential gain function is rewired as following:
)
In 0.18µm CMOS process, we can derive the error term
)
which influence the pseudo exponential equation. The gain range may be decreased about 6%. The gain range decreases due to deep submicron effect is about 0.6dB for one stage.
Chapter 4
Variable Gain Amplifier Design
Since the proposed high dynamic VGA performs well in the exponential approximation, the VGA circuit is employed in the UWB system for verification and will be discussed in this chapter. Section 4.1 introduces in brief the MutiBand OFDM proposal and focuses on gain range related information. Section 4.2 discusses the variable gain amplifier architecture for UWB system. Section 4.3 discusses the variable gain amplifier circuit design. Section 4.4 analyses the post amplifier circuit. Section 4.5 discusses the offset cancellation technique.
The simulation results for VGA application in the UWB system is shown in section 4.6.
4.1 MB-OFDM Proposal Brief
In the MB-OFDM proposal [11], the FCC approved spectrum, 3.1-10.6 GHz, is divided into 14 bands where each band has bandwidth of 528 MHz. As shown in Figure 1, the 14 bands are categorized into 5 band groups where a time-frequency code (TFC) is utilized to interleave coded data over up to three frequency bands. Each band uses a total of 122 modulated and pilot subcarriers out of a total of 128 subcarriers whose bandwidth is 4.125 MHz each. The OFDM subcarriers are modulated using QPSK. To avoid difficulties in DAC and ADC offsets and carrier feed-through in the RF system, the subcarrier falling at DC (0th subcarrier) is not used. The support of transmitting and receiving at data rates of 53.3, 110,
Figure 15 Transmitter power spectral density mask in MB OFDM proposal.
Minimum Sensitivity for Mode 1 (dBm)
Minimum Sensitivity for Mode 1 (dBm)
Data Rate (Mb/s)
Table 2. Receiver performance requirement in MB OFDM proposal.
and 200 Mb/s is mandatory, while the maximum capability can achieve 480 Mb/s. Devices operating in band group #1 are denoted Mode 1 devices, and it shall be mandatory for all devices to support Mode 1 operation, with support for the other band groups being optional and added in the future. The transmitted spectrum shall have a 0 dBr (dB relative to the maximum spectral density of the signal) bandwidth not exceeding 260 MHz, –12 dBr at 285 MHz frequency offset, and –20 dBr at 330 MHz frequency offset and above. The transmitted spectral density of the transmitted signal mask shall fall within the spectral, as shown in Fig.15. For a packet error rate (PER) of less than 8% with a PSDU of 1024 bytes, the minimum receiver sensitivity numbers for the various rates and modes are listed in Table 2.
In the MB-OFDM proposal, the output power of transmitter is defined as -10dBm. Assume
Figure 16 System architecture of UWB transceiver.
Figure 17 UWB receiver path.
the channel loss is about 30dB, then the maximum power will be revived by receiver is -40dBm. From Table.1, the minimum sensitive is -83.6dBm. Hence the input range is -40dBm ~ -83.6dBm for a UWB receiver. Direct-conversion is adopted in the system architecture as shown in Figure 16. The bulky image rejection filters are not necessary any more and system-on-chip (SOC) integration is more accessible with this more compact architecture. Besides, it is more important that power consumption can be much reduced.
Figure 17 shows the reciver building blocks and module specifications. We plan a receiver path from LNA to A/D converter as shown in Fig. 17. The VGA block will provide a wide dynamic range from 25 to 75 dB. In following section, we will introduce the VGA block.
4.2 Variable Gain Amplifier Architecture
Fig. 4 shows the block diagram of the VGA design. The VGA consists of two cascaded pseudo-exponential gain cells with a offset subtractor. The input referred offset voltage is derived from output common mode voltage by a 2nd order low-pass filter, and fed back to the offset substrator at the input port. The input referred offset voltage is reduced by the feedback amount with offset compensation loop. The dominant pole of the loop filter is introduced by an external capacitor with on chip resistor to save chip area [12]. In order to improve the linearity of over all VGA architecture, a post amplifier is connected after the variable gain amplifier. A post amplifier will provide a gain about 38.7dB and will compensate the small output swing of the VGA circuit. In order to drive a larger load, a buffer is used in the preceding stage. In this thesis, we assume the output load is 10p.
Figure 18 Variable gain amplifier architecture.
Parameters Spec.
Technology CMOS 1.8 um
Power supply 1.8 V
3-dB bandwidth 245 MHz
Power consumption 25mW
Gain range 25 dB ~ 75 dB Out swing @ THD 32dB 400m Vpp
Control Voltage --
Table 3. A simple specification of UWB VGA circuit.
Process Node Rate (Mb/s) Transmit Receive
110 93 mW 155 mW
200 93 mW 169 mW
90 nm
480 145 mW 236 mW
110 117 mW 205 mW
200 117 mW 227 mW
130 nm
480 180 mW 323 mW
Table 4. Power consumption for Mode1 DEV(3-Band).
A simple specification for an UWB VGA circuit is shown as Table.2, the minimum bandwidth is required 245MHz. Because the resolution of A/D converter is 5bits, hence the total harmonic destruction (THD) is required just more than 32dB. There is no specification about the power consumption, but Table 3 shows power consumption for Mode1 DEV(3-Band). As a consequence, a low power VGA of ultra-wide band cover all the frequency of interest, and according system budget the total power consumption of VGA should be limited in 20mW. A lot of power will be consumed in output buffer, and the distribution of power consumption will be discussed in section 4.4.
4.3 Variable Gain Amplifier Circuit
Fig. 19 shows the complete schematic of proposed VGA with a DC-level shift. In order to get better settling time performance and current balance, transistors M1 - M4 are the current mirror for transistor Msn and transistors M5 - M8 are the current mirror for transistor Msp, respectively. The M9 and M10 are adjusted by the common-mode feedback (CMFB) unit. Transistors M11 - M14 are used to perform voltage buffer and provide voltage level shift [13]. Transistors Msn and Msp are used to control input and load transconductance together with the control voltage as mentioned earlier.
Compare with Fig. 12, eight transistors M1 - M8 are added in Fig. 19 to balance the current when gain is varied. Because the gain is proportion to the ratio of transconductance, we need to control the drain current of Msn and Msp to vary the transconductance of input
Figure 19 Schematic of the variable gain amplifier.
Figure 20 Common mode feedback amplifier.
and load transistor. Now let us discuss about the circuit without transistors M1- M8. In high gain mode, Vctrl is increased and the over driver voltage of Msn is increased and Mps is decreased. Under this condition, the tail current source Msn will be driven to linear range and the pseudo exponential will never existence. There is another important parameter we must pay attention, in equation (3-7). The gain range of pseudo exponential equation will be -15dB
~ 15dB, if the parameter k equate one in equation (3-7). In our UWB system requirement, VGA’s gain range must be 25dB ~ 75dB. Hence we must shift the gain range of pseudo exponential equation. In this thesis the parameter k will be designed about 2.4 and the gain range of signal stage VGA circuit will be -7.8dB ~ 19.3dB. By this mean, there is about 27dB dynamic gain range for one stage VGA and only two VGA stages are required to satisfy the UWB system specification. If we chose the conventional VGA circuit we need four stages to satisfy the UWB system which more than 45dB dynamic gain range is required.
A common mode feedback circuit is used to stabilize the output common mode level, since all the circuits are fully differential. Output DC level variation is important in
Figure 21 Signal stage VGA simulation.
DC-coupled multi-stage VGA design. If the VGA cannot provide a stable and accurate output DC level, the following stages will be biased at wrong operation point under different gain settings. The output of the common mode feedback circuit is used to adjust the bias current through the transistors M9 and M10. The diagram of the common mode feedback unit is shown in Fig. 20. The compensative resistance is implemented by a transistor Mr operating in triode region [14]. This common mode amplifier has one benefit which can provide infinite impedance for the output node of the VGA circuit, since the gain variation is related with the output impedance in the VGA circuit. Hence the output connected to the gate of the transistor will not affect the gain of the VGA circuit. Fig. 21 shows the simulation curve of one stage VGA circuit. The dynamic gain is -7.8dB ~ 19.3dB.
The combination of the VGA and CMFB circuits is a negative feedback structure.
Hence the stability problem must be discussed in this feedback circuit. Fig. 22 is a circuit diagram for stability simulation; we interrupt the feedback path and put the gate capacitance of transistors M9 and M10 as an output load for CMFB. Fig. 23 & 24 are the phase margin simulation result for high gain and low gain mode, larger phase margin is necessary to avoid oscillate issue. From the Fig. 23 & 24 phase margins are 103deg and 117deg and we can make sure that this feedback structure is a stable structure.
Figure 22 Stability simulation setup.
Figure 23 Phase margin simulation (high gain).
Figure 24 Phase margin simulation (low gain).
Figure 25 Schematic of the post amplifier.
4.4 Post Amplifier & Buffer
The small output swing is a serious problem for UWB systems. In order to conquer this drawback, a post amplifier will be added after the VGA circuit. The post amplifier provides a
The small output swing is a serious problem for UWB systems. In order to conquer this drawback, a post amplifier will be added after the VGA circuit. The post amplifier provides a