Chapter 1 Introduction
1.3 Organization
This work is organized as follows. In Chapter 2, we discuss all the important noise and distortion models in SDM. In Chapter 3, the correlation issue for each SDM noise would be discussed. In Chapter 4, advantages of model-based SDM design are presented. In Chapter 5, the SDM power consumption is derived. In Chapter 6, we would propose a design optimization scheme, and use a published design case [3] to demonstrate its accuracy and practicability. Conclusion and future works are presented in Chapter 7.
2
SDM Noise Power and Distortion Power Models
Model-based high-level SDM design employs only mathematical models. In this chapter, we will first check about the availability of noise and distortion models against all non-idealities in SDM. These models are functions of design parameters. Modification to existing models will be made wherever needed. The models discussed here are for the popular switch-capacitor single-loop 2nd-order SDM structure shown in Fig. 2.1.
Fig. 2.1: Schematic of SC single-loop 2nd-order SDM
For SC single-loop 2nd-order SDM shown in Fig. 2.1, major circuit non-idealities are listed below:
1) Switches non-idealities;
2) Capacitors non-idealities;
3) Finite and nonlinear DC-gain;
4) Bandwidth and slew rate;
5) OTA noises;
6) Clock jitter effect;
7) Comparators;
8) Multi-bit DAC non-idealities.
The non-idealities of (1) - (5) are related to integrators. The non-idealities of (6) - (8) are from outside of integrators. In the following, noise and distortion power models related to each of eight non-idealities are discussed.
2.1 Switch Non-idealities
2.1.1 Switch Thermal Noise Power Model (P
Switch_thermal)
PSwitch_thermal [13] [14] is from switches before Cu and CS. The PSD of switch thermal
2.1.2 Nonlinear Switch on-resistance Distortion Power Model (P
Switch_distortion)
The switch on-resistance is nonlinear because its value depends on input signal. The SDM output distortion power PSwitch_distortion can be obtained from [15].
2.1.3 Clock-Feedthrough
The clock-feedthrough is caused by the charge of the gate-to-source capacitors of the switch that is injected to the sampling capacitor when switch turns off. This error can be attenuated by fully differential integrator [16].
2.1.4 Charge Injection
Charge injection is due to the charge of mobile channel injected to the sampling
capacitor when the switch turns off. This error can be solved by widely used circuit technology [16].
2.2 Capacitors Non-idealities
2.2.1 Capacitor Mismatch Noise Power Model (P
Cap_mismatch)
Capacitor mismatch can alter integrator gain from its nominal value, resulting in SDM output noise power PCap_mismatch [14].
2.2.2 Capacitor Nonlinearity Distortion Power Model (P
Cap_distortion)
The capacitor CS introduces harmonic distortion because its capacitance depends on the input signal. The output distortion power PCap_distortion is derived in [14] under the assumption that the gain of the second stage equals to one.
2.3 Finite and Nonlinear DC-gain
2.3.1 Finite DC-gain Noise Power Model (P
Finite_DC-gain)
Finite DC-gain affects the noise transfer function, resulting SDM output noise power PFinite_DC-gain [14].
2.3.2 Nonlinear DC-gain Distortion Power Model (P
DC-gain_distortion)
OTA DC-gain is nonlinear because it varies with integrator output voltage. The output distortion power PDC-gain_distortion can be obtained from [17].
2.4 Bandwidth and Slew-Rate
2.4.1 Settling Noise Power Model (P
Settling_noise)
The limited integrator bandwidth and slew-rate make the voltage charge and discharge incomplete at integrator output, which causes SDM output noise power PSettling_noise [18].
2.4.2 Slew-Rate Distortion Power Model (P
Settling_distortion)
If input signal of integrator is so large that it exceeds the integrator slew-rate limitation,
a dependency of the settling error on its input is created, which results slew-rate distortion.
The output distortion power PSettling_distortion can be obtained from [14].
2.5 OTA Noises
2.5.1 OTA Thermal Noise Power Model (P
OTA_thermal)
The OTA thermal noise originates from the OTA MOSFET non-idealities. Form the input-referred noise PSD VnOTA2
[14] [20], the in-band OTA thermal noise power at SDM output can be derived as
2 2
from noise source to integrator output in sampling phase and integration phase, respectively.2.5.2 Flicker (1/f) Noise Power Model (P
OTA_flicker)
The flicker noise also originates from the transistor non-idealities of OTA. The output noise power POTA_flicker can be obtained from [20].
2.5.3 Reference Circuit Noise Power Model (P
Ref_noise)
Reference circuit noise usually contains OTA thermal noise and flicker noise, appearing at reference voltage of DAC circuit in Fig. 2.1. The output noise power can be obtained from [13] [20].
2.6 Clock Jitter Effect (P
Jitter_noise)
The clock jitter noise originates from the sampling phase, resulting in non-uniform sampling of converter input signal. The noise power PJitter_noise can be obtained from [1].
2.7 Comparator Hysteresis(P
Hysteresis)
The comparator hysteresis is defined as the minimum overdrive to change the
comparator’s output, which leads to a loss of performance of SDM, and the noise power PHysteresis can be obtained from [1].
2.8 Multi-bit DAC Non-idealities
2.8.1 DAC Noise Power Model (P
DAC_noise)
The DAC noise originates from the capacitance of Cu mismatch, andcan be obtained from [13].
2.8.2 DAC Distortion Power Model (P
DAC_distortion)
The DAC is nonlinear because the transfer function of DAC depends on the capacitance of Cu. It causes DAC distortion.
3
SNDR Generation in Model-Based SDM Designs
The SDM design spec is typically given in terms of SNDR. SNDR is defined as
behavior simulations. In model-based SDM designs, PN and PD are computed by summing up each SDM output noise and distortion power models described in Chapter 2. However, there is one issue associated with the computation of PN and PD; i.e., the correlation problem.
The direct sum up of noise powers and distortion powers would work only when the SDM output noises and distortions are independent. Indeed, correlations between noises and distortions do exist, and they have to be considered in the computation of PN and PD. In this chapter, PN and PD are defined as
_ _ _ _ _
_ _
N Modified quantization noise Switch thermal OTA thermal Jitter noise
DAC noise Settling noise
D DC gain distortion DAC distortion
P P P (3.3)
Since finite DC-gain may produce changes in noise transfer function and increase in-band quantization noise, the quantization noise would be rewritten as
2 4 2 2
where μ represents the finite DC-gain error and VLSB represents the quantizer step size for mid-tread quantizer.
For the six noise powers in equation (3.2), the first five can be correctly summed up, since the five corresponding noises (i.e., modified quantization noise, switch thermal noise, OTA thermal noise, jitter noise and DAC noise) are independent. However, due to the reasons explained later, these five noises are correlated with settling noise. Therefore, there should be additional correlation powers terms in equation (3.2) to account for the correlation between settling noise and the five independent noises. These correlation terms are derived in follows.
Fig. 3.1: Block diagram of single-loop 2nd-order SDM
Consider the five independent noises. The modified quantization noise (3.4) is expressed in Fig. 3.1 as EQ applied at nodes 3 and the factor μ at feedback loop of first integrator. The remaining four noises are applied at node 1 of Fig. 3.1, the sum of which is donated as E. These five noises are treated as independent because EQ and the four noises in E are all assumed to be Gaussian and white. Next, to explain why these five noises are correlated to settling noise, recall that settling error ε is approximated in [18] as
1 3 5
1VS 3VS 5VS
(3.5)
According to Fig. 3.1, the VS in equation (3.5) can be expressed as
-2 1 2
(1- ) -[1 (1 )]
S Q
V z E z E (3.6)
It is clear from equations (3.5) and (3.6) that settling error ε is correlated to E, EQ and μ.
From discussions above, the noise signal at SDM output can be expressed as
_ _ _
( ) ( ) ( ) ( )
N Modified quantization noise Settling noise E
v t v t v t v t (3.7)
where
_ _ _ _
( ) ( ) ( ) ( ) ( )
E Switch thermal OTA thermal DAC noise Jitter noise
v t v t v t v t v t (3.8)
The autocorrelation function of vN(t) is
_ _ _
( ) [ ( ) ( )]
( ) ( ) ( )
( ) ( ) ( ) ( )
N N N
Modified quantization noise E Settling noise
SQ QS SE ES vModified_quantization_noise(t), and RSE(τ) and RES(τ) are cross-collection function of vSettling_noise(t) and vE(t). Since vModified_quantization_noise(t) and vE(t) are uncorrelated, thus, REQ(τ) and RQE(τ) do not exist in equation (3.9). Then, the power spectral density function of vN(t) is
_ _ _
( ) { ( )}
( ) ( ) ( )
( ) ( ) ( ) ( )
N N
Modified quantization noise E Settling noise
SQ QS SE ES
Modified quantization noise Switch thermal OTA thermal DAC noise Jitter noise f
Settling noise f SQ QS SE ES
P S f df
The first six terms at equation (3.11) are identical to those in equation (3.2). The remaining
terms at equation (3.11) are the correlation power models to be derived. The SQS(f), SSQ(f),
where VSettling_noise(f), VModified_quantization_noise(f), and VE(f) are the Fourier transforms of vSettling_noise(t), vModified_quantization_noise(t), and vE(t), respectively, over a finite time interval [-T, T].
(a)
(b)
Fig. 3.2: The magnitude and angle of VModified_quantizaition_noise(f)
Fig. 3.2 (a) shows the FFT of a typical vModified_quantization_noise(t) obtained from behavior simulation. Fig. 3.2 (b) shows that the angle of VModified_quantization_noise(f) is random and is
close to uniform distribution. Therefore, θQ(f) is assumed to be an arbitrary value in –π~π, and VModified_quantization_noise(f) is modeled as
_ _
Fig. 3.3 shows the FFT of vE(t) obtained from behavior simulation.
(a)
(b)
Fig. 3.3: The magnitude and angle of VE(f)
The angle of VE(f) is also close to a uniform distribution. Therefore, θE(f) is assumed to be an arbitrary value in –π~π, and VE(f) is modeled as
For the settling noise, VSettling_noise(t) and vSettling_noise(f) are expressed in [18] as
1 3 5
where vS(t) is the first integrator input signal, and by equation (3.6)
1 then the correlation power can be evaluated as
- B ( ) ( ) ( ) ( )
B
f
Correlation f SQ QS ES SE
P
S f S f S f S f df (3.21)With PCorrelation added, PN in equation (3.1) is then rewritten as
_ _ _ _ _ _
_
N Modified quantization noise Switch thermal OTA thermal Jitter noise DAC noise
Settling noise Correlation correlation power calculated by equation (3.21) and by behavior simulation for various SR and GBW combinations, with other parameters set at Fin=100kHz, B=1, OSR=100, Ain=0.2V and Vref =1V. The two surfaces in Fig. 3.4 (a) (b) are very close.
(a)
(b)
Fig. 3.4: Correlation powers (a) assumption that VE in negligible (b) assumption that VE exists
Next, an example is provided to investigate the relations between PSettling_noise, PQuantization_noise and PCorrelation under the assumption that VE(f) in negligible, which is the typical case. The relevant parameters are: Fin=100kHz, B=1, OSR=256, Ain=0.2V, Vref=1V and GBW=51.2MHz, Fig. 3.5 shows the three noise powers w.r.t different SR values.
Fig. 3.5: Each noise power for different SR values.
Discussion 1: As Fig. 3.5 shows, settling noise is in linear region [18] when slew-rate is large than 110V/μs. In this case, the α3 and α5 in equation (3.16) can be neglected, such
Correlation f SQ QS Quantization noise Settling noise
P S f S f df P P
(3.24)Since PQuantization_noise=-120dB and PSettling_noise=-159dB, the correlation power is -137dB, as is shown in Fig. 3.5.
Discussion 2: When slew-rate is less than 110 V/μs, the α3 and α5 in equation (3.16) would increase dramatically. Therefore, the normalized correlation between settling noise and quantization noise reduces when slew-rate decreases. However, as is shown in Fig. 3.5, PCorrelation increases steadily as SR decreases, and PCorrelation becomes larger than PQuantization_noise when SR<100 V/μs. This is because PCorrelation represents an absolute correlation power, not a relative one.
4
Advantages of Model-Based SDM Design
The first advantage of model-based design over simulation-based design is obviously its speed; the former can be at the order 104 times faster. The second advantage is that the model-based approach provides more insights to guide the design, since this design method explicitly computes all noise powers and distortion powers. These issues are quantitatively analyzed in this chapter.
4.1 SNDR Speed Comparison
For model-based SDM design, the SNDR is computed by equation (3.1). In simulation-based SDM design (in MATLAB SIMULINK environment), generating SNDR is a more complex process. First, behavior simulation is conducted and output data points are collected. Then, FFT is performed on collected data points to generate power spectral density (PSD). The total noise power PN is obtained from integrating in-band PSD floor, and total distortion power is obtained by summing up distortional powers in PSD. The accuracy of SNDR computed heavily depends on the number of data points involved, since sufficient number of data points in needed to generate relatively accurate PSD [22]. However, more data points require almost proportionally more simulation time because FFT accounts for only 0.3% of the total simulation time for generating SNDR. Table 4.1 lists the simulation times for obtaining 16384, 32768 and 65536 data points.
Fig. 4.1: Single-loop 2nd-order SDM model with relevant non-ideality blocks.
TABLE 4.1: Running time of each non-ideality for both design approaches
Non-idealities Data Points 16384 32768 65536
Quantization Noise
Simulation-Based 56.515ms 114.125ms 285.375ms
Model-Based 0.016ms 0.016ms 0.016ms
Switch thermal Noise
Simulation-Based 108.203ms 182.969ms 423.25ms
Model-Based 0.016ms 0.016ms 0.016ms
Jitter Noise
Simulation-Based 67.985ms 123.703ms 254.562ms
Model-Based 0.016ms 0.016ms 0.016ms
DAC Noise
Simulation-Based 83.86ms 165.157ms 370.297ms
Model-Based 0.016ms 0.016ms 0.016ms
OTA thermal Noise
Simulation-Based 65.438ms 119.219ms 256.844ms
Model-Based 0.422ms 0.422ms 0.422ms
Settling Noise
Simulation-Based 2171.72ms 4865.94ms 8578.59ms
Model-Based 23.469ms 23.469ms 23.469ms
DC-Gain Distortion
Simulation-Based 1967.063ms 3941.09ms 7828.078ms
Model-Based 0.031ms 0.031ms 0.031ms
Total Non-idealities
Simulation-Based 3847.03ms 7631.25ms 15382.03ms
Model-Based 24.125ms 24.125ms 24.125ms
In MATLAB 7.0.1, simulations were carried on AMD Athlon (tm) 64 X2 Dual Core Processor 6000+ PC with 4GB memory running at 3.11GHz.
In contrast, as is shown in Table 4.1, in model-based approach the SNDR computation time is a least 102 times loss than that in simulation-based approach. The model-based SNDR computation time can be reduced much further, since little research has been done on
the computational issue which would be discussed in follows.
As Fig. 4.2 shows, computing settling noise power accounts for 97% of the total time for generating SNDR. To reduce the computation time of settling noise power, we modify the settling noise analytic model [18].
Fig. 4.2: The pie chart of SNDR computation time in model-based SDM design method
The settling noise is approximated by following polynomial
1 3 5
where W(VS) is the weight function,
2
(f) are needed to computed settling noise.
3( ) ( ) ( ) ( )
Finally, the settling noise power is obtained by
1 3 5 coefficient computation, is the most time-consuming because using MATLAB to evaluate integrals in equation (4.2) costs much time. In MATLAB environment, dealing with algebra problem is much faster than evaluating integral problem. Hence, find the antiderivative of integrand in equation (4.2) and substitute the upper and lower limits of integration would make computation time for coefficients α1, α3, and α5 much faster. In this way the computation time for coefficients α1, α3 and α5 become much faster, and it only takes 0.219ms to generate settling noise power.
In addition, computing OTA thermal noise power also needs to evaluate the integrals in equation (4.7). Hence, we find the antiderivative of integrand in equation (4.7) and
Eventually, it takes only 0.312m second for generating SNDR in model-based SDM design after modifying noise analytic models. It is hundred times faster than before. But computing
settling noise power still accounts for 63% of the total time in generating SNDR as is shown in Fig. 4.3.
Fig. 4.3: The pie chart of SNDR computation time in modified model-based SDM design method
Despite the detail of two design approaches, in model-based SDM design the SNDR computation time is a least 104 times faster than that in simulation-based SDM design.
Consequently, model-based method is a time-efficient and practical solution in SDM design cycle.
4.2 SDM Design Guide
Simulation-based SDM design generates sum of noise PN and sum of distortion PD from SDM output PSD. In this process, it is not easy to find out the magnitude of individual noise or distortion. In contrast, model-based SDM design can explicitly compute all noise and distortion powers. This advantage may be exploited by designers. We now consider two possible cases.
In the case that design specification cannot be met, the knowledge about dominating noise or distortion would indicate where design can be improved. For example, in a design problem for the sensor applications, SNDR is required to be better than 96dB (i.e., a resolution of 16 bits), but SNDR at 87dB is the highest that is achieved by traditional design method. After computing noise and distortion powers using their models, it revealed that all noises and distortions are very small except that the DAC noise at -86dB is the dominating
factor for previous design result. This gives a guide about how the design can be improved.
After employing the DWA algorithm or making use of better CMOS device technology, the designer is able to reduce DAC noise to -123dB. New computations reveal that SNDR at 97dB is achieved, with dominating non-ideality power being switch noise power at -99dB.
In the case that design specification is met, the knowledge about magnitude of each noise or distortion would suggest where design parameters can be relaxed. For example, SNDR for an audio application is required to be better than 84dB (i.e. a resolution of 14 bits), and SNDR at 87dB is achieved by traditional design method. Since our model can compute all noise and distortion powers, we immediately find that -121dB for the settling noise power is by far smaller than the dominating non-ideality power which here is switch thermal noise at -94dB. Our models suggest that adjusting SR and GBW would significantly affect settling noise power and SDM power consumption, but otherwise has little effect on other noises and distortions. After relaxing design parameters SR (from 160V/μs to 91V/μs) and GBW (from 120MHz to 80MHz), designer raised settling noise to -98dB. Although SNDR is consequently lowered to 86dB, it still meets the 84dB requirement. But the benefits received are obvious: OTA power consumption is reduced from 11.23mW to 7.04mW, and OTA design complexity is much decreased.
5
Models of SDM Power Consumption
In this chapter, we propose an effective SDM power consumption model, which bases on single-loop 2nd-order SDM architecture shown in Fig. 2.1. Our power consumption model is split up in two parts: the analog power consumption of OTA and quantizer, and the digital power consumption of switch, DAC and data weighted averaging (DWA).
5.1 Analog Power Consumption:
5.1.1 OTA Power Consumption:
Given design parameters GBW, SR, and Ceq, OTA power consumption is derived partly based on study [23] [24]. Here, OTA model is depicted in Fig. 5.1. This model includes:
A single-pole dynamic
A non-linear characteristic with maximum output current IO
Fig. 5.1: OTA model
The OTA open-loop transfer function can be expressed as
0
where gm is the OTA transconductance and rout is the OTA open-loop output resistance.
p1 is the OTA open-loop pole
1
1
out L
p r C
(5.3)
where CL donates the open-loop effective load capacitance.
Using OTA model shown in Fig. 5.1 with infinite rout, the model of the SC integrator is shown in Fig. 5.2. Meanwhile, it also takes the parasitic capacitors associated to its input and output nodes into account.
Fig. 5.2: Integrator model with the parasitic capacitor
Here, CS and CI are the sampling and integrating capacitors of integrator; CP is the parasitic input capacitance and CL is the output load capacitance, which includes the OTA output feedback factor for the integrator is
I
S I P
f C
C C C
(5.5)
The unit-gain frequency for integrator is
0 1
where CO is the open-loop effective load capacitance of the integrator shown in Fig. 5.2.
/ /( )
O L I S P
C C C C C (5.7)
The close-loop gain -3dB bandwidth is defined as
3
where Ceq is the equivalent load capacitance for the integrator, and is estimated as
1 P S
For the step response calculation, the time constant τa of the integrator is defined as
3
Then, OTA transconductance for the integrator is obtained by
m 2 eq
g GBW C (5.11)
Besides, SR for the integrator is defined as
O eq
SR I
C (5.12)
Hence, OTA maximum output current IO is obtained by
O eq
I SR C (5.13)
Given specific values of GBW, SR and Ceq, equation (5.11) and equation (5.13) indicate the corresponding value of gm and IO of the OTA. However, estimating OTA power consumption is not only determined by these three design parameters, but also decided by chosen OTA topology. The merits of three OTA topologies here are examined: telescopic OTA, folded-cascode OTA, and two-stage Miller-compensated OTA. Their simplified circuit schematics would be presented in Fig. 5.3 (a), (b) and (c), respectively.
Fig. 5.3 (a) Telescopic OTA
For telescopic OTA, the slew-rate is
9 D
eq
SR I
C (5.14)
Then, the bias current ID9 corresponded to SR is defined as
9( )
D SR eq
I SR C (5.15)
The close-loop -3dB bandwidth for the integrator is
1
Combing (5.17) with the transcoductance equation in strong region inversion region,
9
The bias current ID9 corresponded to ω-3dB is defined as
9( ) 3 1 2 1
D GBW dB eq OV eq OV
I C V GBW C V (5.18)
where VOV1 is the transistor overdrive voltage of the differential pair.
Equation (5.15) and equation (5.18) indicate that the telescopic OTA bias current ID9 depends on VOV1. The designer could assume that VOV1 has a range (such as 0.1v~0.3v) when calculating ID9. If VOV1 is in the range, it would be self adjusted to make following
equation hold.
9( ) 9( )
B D SR D GBW
I I I (5.19)
If VOV1 is out of range, it would be stuck at the extreme value of the range and the following equation would be hold.
9( ), 9( )
B D SR D GBW
I Max I I (5.20)
Finally, the telescopic OTA power consumption is
DD B
PCV I (5.21)
where VDD donates the supply voltage.
Fig. 5.3 (b): Folded-Cascode OTA
Fig. 5.3 (b): Folded-Cascode OTA