Chapter 5 Models of SDM Power Consumption
5.2 Digital Power Consumption
5.2.3 DWA Power Consumption
technology, CSwitch could be obtained.
5.2.3 DWA Power Consumption:
DWA algorithm used to solve the nonlinearity problem of the feedback DAC can be implemented with an accumulator and a logarithmic shifter [27], as is depicted in Fig. 5.4.
Fig. 5.4: Block diagram of DWA implementation
As Fig. 5.4 is shown, the DWA circuit would be separate in: ROM encoder, accumulator,
and logarithmic shifter. A 2-bit ROM encoder is shown in Fig. 5.5.
Fig. 5.5: 2-bit thermometer-to-binary ROM encoder
When NMOS turns on, the current flows through the resistor and can be calculated as
When the NMOS turns off, there is no current on the resistor and no power consumption.
For example, as input thermometer code is 0000, the output binary code is 000, and then the ROM encoder consumes no power. As the input thermometer code is 0001, the output binary code is 001, and the power of the ROM encoder is VDD∙ID (Because one NMOS turns on). For the input thermometer code is given over some time interval, ROM encoder power consumption can be estimated.
For the accumulator and the logarithmic shifter, their power consumption are
where VSupply is the circuit supply voltage; CD,eq is the equivalent capacitance corresponding to the complexity of the accumulator and the logarithmic shifter, and its derivation is based on study [26]. Here, accumulator builds up with register and adder, and logarithmic shifter builds up with multiplexer. Therefore, a good approximation of CD,eq is the number of one
bit accumulator and logarithmic shifter that are operating at frequency fS, and is expressed as
, ( ) 2B
D eq Add Reg MUX
C B C C B C (5.47)
where CAdd, CReg, and CMUX are the one bit equivalent capacitance of adder, register and multiplexer, respectively.
For example, when we give CD,eq a specific value shown in Table 5.1, Fig. 5.6 (a)-(c) show the DWA power in equation (5.45) with the corresponding simulation result.
TABLE 5.1: The specific value of CD,eq for different bit number
2 Bit 3 Bit 4 Bit
CD,eq 0.2935 pF 0.4846 pF 0.8295 pF
Fig. 5.6 (a): 2-bit DWA Power
Fig. 5.6 (b): 3-bit DWA Power
Fig. 5.6 (c): 4-bit DWA Power
By summing up all the contributions in equations (5.40) - (5.43) and (5.46), the SDM power consumption can be estimated as
OTA Quantizer DAC Switch DWA
POWERPC PC PC PC PC (5.48)
The SDM power consumption is related to fB, OSR, CS, Ron, B, GBW and SR.
6
Model-Based SDM Design Optimization
In this chapter, we propose a methodology for model-based SDM design optimization.
This design method is applied to a published design task [3]. Compared with the single-loop SDM reported in [3], the SDMs designed by our method achieves much higher SNDR and significantly lowers power consumption. This shows that our method can effectively achieve more balanced designs for piratical application.
6.1 Design Optimization Schemes
A typical SDM design optimization algorithm is shown in Fig. 6.1. This algorithm searches the SDM design parameter space to find out one design parameter set which meet in terms of SNR or SNDR while keeping the power consumption as low as possible. The blocks or signals in Fig. 6.1 are explained in the following.
Fig. 6.1: Design optimization schemes
6.1.1 Design Parameters
Designers need to determine which design parameters are fixed to a specific value and which design parameters are adjusted during the optimization process run.
6.1.2 SNDR and POWER Computation
SNDR computation has been described in equation (3.1), and the POWER computation has been described in equation (5.48).
6.1.3 Cost Function Generation
After the SNDR and POWER are computed, they are used to generate
10 log( ) increasing SNDR would play a more important role than reducing POWER. In contrast, if low power design is needed, the value of K would be set smaller.
At the end of the optimization process, the design parameter set corresponding to the minimum cost function value is treated as the design.
6.2 ΣΔ ADC for ADSL-CO Applications
The ADSL design specs reported in [3] to be achieved are
Peak SNDR : 78 dB
Signal bandwidth : 276 kHz
According to [3], Vref and VDD are set at 0.9V and 1.8V for the 0.18-μm CMOS technology.
The σdac is set at 0.04% for the MIM capacitance. Design parameter space searched by our model-based optimization scheme is
R: 100 ~ 300 Ω
Ain: 0.1 ~ 0.9 V
The design published in [3] and that achieved from our methodology are listed in Table 6.1. The noise powers and distortion powers for both designs are listed in Table 6.2.
TABLE 6.1: Comparisons of our design results with those in [3]
Design parameters Reference [3] K = 0.2 Unit
TABLE 6.2: The corresponding noise and distortion power for both designs Non-ideality Power Reference [3] K = 0.2 Unit
PModified_Quantization_noise -109.69 -103.95 dB
PSwitch_thermal -96.92 -95.11 dB
POTA_thermal -116.28 -111.97 dB
PSettling_noise -216.63 -115.63 dB
PDAC_noise -85.68 -123.17 dB
PJitter_noise -122.87 -125.90 dB
PCorrelation -145.61 -123.36 dB
PDC-gain_distortion -95.58 -102.58 dB
PDAC_distortion -77.05 - dB
Discussion 1: The design from model-based optimization is better than that of [3], achieving 89.91dB SNDR at 13.22mW compared with 75.51dB SNDR at 34.19mW in [3].
Discussion 2: Ref. [3] chose to use a 3-bit DAC without DWA, resulting in a dominating DAC distortion at -77.05dB and a large DAC noise at -85.68dB which brought
down SNDR. In contrast, our method by nature tries to evenly distribute noise power and distortion power among all noise and distortion categories, while minimizing POWER at the same time. This is the main reason our design can achieve a higher SNDR with lower POWER. Our algorithm selected a 2-bit DAC with DWA, eliminating DAC distortion and lowering DAC noise to -123.17dB.
Discussion 3: The power consumption by SDM of [3] is more than two times that of our SDM. This large power consumption is due to high values of GBW and SR used.
Although large GBW and SR values indeed reduce Settling noise to -216dB in [3], this offered no help to boost SNDR.
Discussion 4: The SNDR computed by our model are verified by SIMULINK behavior simuation.
TABLE 6.3:Model-based optimization design results for different K values Design parameters K = 1 K = 0.2 K = 0.04 Unit
Discussion 5: Table 6.3 shows model-based optimization design results for different K values. It can be observed form Table 6.3 that when K increases, more emphasis is on rising SNDR; when K decreases, more emphasis is on reducing POWER.
7
Conclusions and Future Works
In order to increase the speed of circuit design for sigma-delta ADCs, this thesis offers an efficient optimization method to achieve the most suitable circuit specifications. All the noise and distortion powers also can be obtained after optimization process is performed, and the dominant noise or distortion power can be attenuated by adjusting the design parameters. Our proposed method has acceptable accuracy and fantastic speed, and the flexibility can be enhanced by building more noise or distortion models for different circuit structures.
Further, in order to reduce the time-cost for optimization, the algorithm efficiently search the entire design parameters space to find the design parameter set which satisfies the specifications must to be established.
Appendix
The antiderivative of integrand in first matrix in equation (4.2) shows in equations (A.1) - (A.5).
The antiderivative of integrand in second matrix in equation (4.2) shows in equations (A.6) - (A.8).
Besides, Erf donates the error function in equations (A.1) - (A.8), and is defined as
2
Erf has Taylor expansion and is expressed as
The antiderivative of integrand in equation (4.7) shows in equation (A.11).
where
2 1 1
2a a
22 2
1 1
bR CS a
2
1 1
A RCS a
c GBW
2 1 1
S
A a d RC
GBW
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