Chapter 5 Models of SDM Power Consumption
5.1 Analog Power Consumption
5.1.1 OTA Power Consumption
Models of SDM Power Consumption
In this chapter, we propose an effective SDM power consumption model, which bases on single-loop 2nd-order SDM architecture shown in Fig. 2.1. Our power consumption model is split up in two parts: the analog power consumption of OTA and quantizer, and the digital power consumption of switch, DAC and data weighted averaging (DWA).
5.1 Analog Power Consumption:
5.1.1 OTA Power Consumption:
Given design parameters GBW, SR, and Ceq, OTA power consumption is derived partly based on study [23] [24]. Here, OTA model is depicted in Fig. 5.1. This model includes:
A single-pole dynamic
A non-linear characteristic with maximum output current IO
Fig. 5.1: OTA model
The OTA open-loop transfer function can be expressed as
0
where gm is the OTA transconductance and rout is the OTA open-loop output resistance.
p1 is the OTA open-loop pole
1
1
out L
p r C
(5.3)
where CL donates the open-loop effective load capacitance.
Using OTA model shown in Fig. 5.1 with infinite rout, the model of the SC integrator is shown in Fig. 5.2. Meanwhile, it also takes the parasitic capacitors associated to its input and output nodes into account.
Fig. 5.2: Integrator model with the parasitic capacitor
Here, CS and CI are the sampling and integrating capacitors of integrator; CP is the parasitic input capacitance and CL is the output load capacitance, which includes the OTA output feedback factor for the integrator is
I
S I P
f C
C C C
(5.5)
The unit-gain frequency for integrator is
0 1
where CO is the open-loop effective load capacitance of the integrator shown in Fig. 5.2.
/ /( )
O L I S P
C C C C C (5.7)
The close-loop gain -3dB bandwidth is defined as
3
where Ceq is the equivalent load capacitance for the integrator, and is estimated as
1 P S
For the step response calculation, the time constant τa of the integrator is defined as
3
Then, OTA transconductance for the integrator is obtained by
m 2 eq
g GBW C (5.11)
Besides, SR for the integrator is defined as
O eq
SR I
C (5.12)
Hence, OTA maximum output current IO is obtained by
O eq
I SR C (5.13)
Given specific values of GBW, SR and Ceq, equation (5.11) and equation (5.13) indicate the corresponding value of gm and IO of the OTA. However, estimating OTA power consumption is not only determined by these three design parameters, but also decided by chosen OTA topology. The merits of three OTA topologies here are examined: telescopic OTA, folded-cascode OTA, and two-stage Miller-compensated OTA. Their simplified circuit schematics would be presented in Fig. 5.3 (a), (b) and (c), respectively.
Fig. 5.3 (a) Telescopic OTA
For telescopic OTA, the slew-rate is
9 D
eq
SR I
C (5.14)
Then, the bias current ID9 corresponded to SR is defined as
9( )
D SR eq
I SR C (5.15)
The close-loop -3dB bandwidth for the integrator is
1
Combing (5.17) with the transcoductance equation in strong region inversion region,
9
The bias current ID9 corresponded to ω-3dB is defined as
9( ) 3 1 2 1
D GBW dB eq OV eq OV
I C V GBW C V (5.18)
where VOV1 is the transistor overdrive voltage of the differential pair.
Equation (5.15) and equation (5.18) indicate that the telescopic OTA bias current ID9 depends on VOV1. The designer could assume that VOV1 has a range (such as 0.1v~0.3v) when calculating ID9. If VOV1 is in the range, it would be self adjusted to make following
equation hold.
9( ) 9( )
B D SR D GBW
I I I (5.19)
If VOV1 is out of range, it would be stuck at the extreme value of the range and the following equation would be hold.
9( ), 9( )
B D SR D GBW
I Max I I (5.20)
Finally, the telescopic OTA power consumption is
DD B
PCV I (5.21)
where VDD donates the supply voltage.
Fig. 5.3 (b): Folded-Cascode OTA
For folded-cascode OTA, the slew-rate is
11 D
eq
SR I
C (5.22)
Then, the bias current ID11 corresponded to SR is defined as
11( )
D SR eq
I SR C (5.23)
Notice that the value of ID9 and ID10 is set to 1.2∙ID11 to avoid zero current in cascades when OTA is slewing [25], and slew limiting occurs only in the input stage of the circuit.
The close-loop -3dB bandwidth for the SC integrator is
1
Combing (5.24) with the transcoductance equation in strong region inversion region, the bias current ID11 corresponded to ω-3dB is defined as
11( ) 3 1 2 1
D GBW dB eq OV eq OV
I C V GBW C V (5.25)
Equation (5.23) and equation (5.25) indicate that the folded-cascode OTA bias current ID11
depends on VOV1. The designer could assume that VOV1 has a range when calculating ID11. If VOV1 is in the range, it would be self adjusted to make following equation be hold.
11( ) 11( )
B D SR D GBW
I I I (5.26)
If VOV1 is out of range, it would be stuck at the extreme value of the range and the following equation would be hold.
11( ), 11( )
B D SR D GBW
I Max I I (5.27)
Finally, the folded-cascode OTA power consumption is 2.4 DD B
PC V I (5.28)
Fig. 5.3 (c): Two-stage Miller-compensated OTA
For the two-stage Miller-compensated OTA, the slew-rate is
7 2 9
6
And the unit-gain bandwidth is
1
0.16CO, and the internal slew-rate SRint is the limiting factor.
Then, the close-loop gain -3dB bandwidth is
1
where Ceq for two-stage Miller-compensated OTA is expressed as
1 S P
Combing (5.33) with the transcoductance equation in strong region inversion region, the bias current ID7 corresponded to ω-3dB is defined as
7( ) 3 1 2 1
D GBW dB eq OV eq OV
I C V GBW C V (5.35)
Besides, the bias current ID7 corresponded to SR is defined as
7( )
D SR C
I SR C (5.36)
Equation (5.35) and equation (5.36) indicates that the two-stage Miller-compensated OTA bias current ID7 depends on VOV1. The designer could assume that VOV1 has a range when calculating ID7. If VOV1 is in the range, it would be self adjusted to make following equation be hold.
7( ) 7( )
B D SR D GBW
I I I (5.37)
If VOV1 is out of range, it would be stuck at the extreme value of the range and the following
As OTA topology is selected, the total OTA power consumption for SDM is approximated as
OTA SDM
PC K PC (5.40)
where KSDM represent the ratio between the total power consumption of all the OTAs and OTA in first stage.