Organization of This Dissertation

To solve the challenges in ESD protection design for RF front-end circuits, several new designs are proposed and verified in this dissertation. This dissertation consists of eight chapters and an appendix. In Chapter 2, the published ESD protection designs for RF front-end circuits and high-speed I/O interface circuits are overviewed to analyze the features of each design. The bond pad is the most peripheral devices of the IC, and its parasitic capacitance affects the signal. Thus, the bond-pad capacitance needs to be reduced to mitigate the high-frequency performance degradation. In Chapter 3, a new ultra low-capacitance bond pad structure is proposed to reduce the bond-pad capacitance. Novel distributed ESD protection design for a 1-to-10 GHz distributed amplifier is proposed in Chapter 4. Chapter 5 proposes the co-design of 5-GHz differential LNA and ESD protection circuit. Several new ESD protection schemes for differential I/O pads are proposed and verified. Besides ESD protection design for RF front-end circuits, ESD protection design methodology for gigahertz high-speed I/O interface circuits is presented in Chapter 6. Board-level CDM ESD issue in IC products is investigated in Chapter 7. Chapter 8 gives the conclusions and future works of this dissertation. The outlines of each chapter are summarized below. In the appendix, a draft of the test standard for board-level CDM ESD robustness of ICs is proposed.

Chapter 2 overviews the published ESD protection designs for high-frequency applications, including RF front-end circuits and high-speed I/O interface circuits. The designs are categorized with their individual advantages and disadvantages clearly analyzed.

The RF performance degradation caused by ESD protection devices are illustrated with measured results. Besides, the I-V curves of ESD protection devices in the high-current regime are also characterized. The measured device characteristics show that there is a trade-off between ESD robustness and RF performance. The published low-capacitance ESD protection designs are categorized into three groups, which are the circuit solution, layout solution, and process solution. The design complexity, improved parasitic effect, ESD robustness, and area efficiency of all reported designs are compared in this chapter.

In Chapter 3, a new ultra low-capacitance bond pad structure is proposed in a 130-nm CMOS process. The equivalent bond-pad capacitance has been verified to be reduced due to the parallel LC resonant network formed by the added inductor and the overlapped capacitance between the bond-pad metal plate and substrate. Three kinds of stacked inductors under the pad are used to realize different inductances. By designing the inductance and capacitance in the proposed bond pad structure, the frequency band in which the bond-pad

capacitance is reduced can be adjusted. Experimental results have shown that the extracted bond-pad capacitance is reduced to almost 0 fF from 4.3 to 4.8 GHz. The new proposed bond pad structure is fully process-compatible to general CMOS processes without any extra process modification.

In Chapter 4, two distributed ESD protection schemes are proposed to protect distributed amplifiers against ESD stresses. Fabricated in a 0.25-μm CMOS process, the distributed amplifier with the equal-sized distributed ESD (ES-DESD) protection scheme, contributing an extra 300 fF parasitic capacitance to the circuit, can sustain the HBM ESD level of 5.5 kV and MM ESD level of 325 V, while exhibits the flat-gain of 4.7 ± 1 dB from1 to 10 GHz.

With the same total parasitic capacitance, the distributed amplifier with the proposed decreasing-sized distributed ESD (DS-DESD) protection scheme achieves better ESD robustness, where the HBM ESD level is over 8 kV and MM ESD level is 575 V. The flat-gain of 4.9 ± 1.1 dB over the 1 to 9.2-GHz band is achieved. With these two proposed wideband ESD protection schemes, good wideband RF performances and high ESD robustness of the distributed amplifier can be successfully achieved simultaneously.

In Chapter 5, several new ESD protection schemes are proposed and applied to a 5-GHz differential LNA in a 130-nm CMOS process. This is the first work which investigates the pin-to-pin ESD robustness of differential LNAs. The differential LNA with the conventional double-diode ESD protection scheme has also been designed and fabricated, and it has 2.5-kV HBM and 200-V ESD robustness. Experimental results have demonstrated that the pin-to-pin ESD test is the most critical ESD test mode for the differential LNA with the conventional ESD protection scheme. With the proposed double silicon-controlled rectifier (SCR) ESD protection scheme, the HBM and MM ESD levels are significantly improved to 6.5 kV and 500 V, respectively. Another proposed design uses an ESD bus between the differential input pads, which has 3-kV HBM and 100-V ESD robustness. Besides, a novel design using cross-coupled SCR devices between the differential input pads has been proposed. By applying the cross-coupled SCR devices, not only ESD protection for a single input pad but also pin-to-pin ESD protection can be achieved without adding any extra devices. Its HBM and MM ESD levels are 1.5 kV and 150 V, respectively. By using other diodes beside the cross-coupled SCR devices, the turn-on efficiency of ESD protection devices can be enhanced. With the double diodes and the cross-coupled SCR devices, the ESD-protected differential LNA achieves 4-kV HBM and 300-V MM ESD robustness. Both ESD robustness and RF performance of all fabricated LNAs with and without ESD protection have been measured and compared and in this chapter.

Chapter 6 presents the ESD protection design for gigahertz high-speed I/O interface circuits. After investigating the ESD levels and parasitic capacitances of the ESD protection diodes with different dimensions, the double-diode ESD protection scheme is applied to the dummy receiver NMOS and the dummy transmitter NMOS. Since the connection of the dummy receiver NMOS (dummy transmitter NMOS) is similar to that of the NMOS transistor in a receiver (transmitter) interface circuit, the ESD robustness of the dummy receiver NMOS (dummy transmitter NMOS) can be used to predict the ESD robustness of the high-speed interface circuit with this ESD protection scheme. This whole-chip ESD protection scheme is also applied to a 2.5-Gb/s high-speed I/O interface circuit, and the ESD robustness is larger than 3 kV in HBM with the parasitic capacitance of less than 250 fF. By replacing the N+/P-well diode between the input pad and VSS with the SCR, the ESD robustness can be further improved. In the ESD protection schemes in Chapter 6, the ESD protection devices and part of the ESD detection circuit is placed under the I/O pad to reduce the chip area and the parasitic capacitance on the signal path.

The board-level CDM ESD issues in IC products are investigated in Chapter 7. The mechanism of board-level CDM ESD event is introduced first. Based on this mechanism, an experiment has been performed to investigate the board-level CDM ESD current waveforms under different sizes of PCBs, charged voltages, and series resistances in the discharging path.

Experimental results have shown that the discharging current strongly depends on the PCB size, charged voltage, and series resistance. Moreover, chip-level and board-level CDM ESD levels of several test devices and test circuits fabricated in CMOS processes have been characterized and compared. Test results have shown that the board-level CDM ESD level of the test circuit is lower than the chip-level CDM ESD level, which indicates that the board-level CDM ESD event is more critical than the chip-level CDM ESD event. In addition, failure analysis reveals that the failure on the test circuit under board-level CDM ESD test is much severer than that under chip-level CDM ESD test. To provide board-level CDM ESD protection, the solution using the ESD discharger has been proposed. The ESD discharger, which consists of series resistances in the order of MΩ, can be used to slowly discharge the static charges in the module and to prevent the IC chips from being damaged by board-level CDM ESD events.

Chapter 8 summarizes the main results of this dissertation. Some suggestions for the future works are also addressed in this chapter. Since the standard for the board-level CDM ESD test is not established so far, the proposal of the “Test standard for board-level charged-device-model electrostatic discharge robustness of integrated circuits” (in Chinese) is

presented in the appendix. In the proposal, the test methodology and test conditions are clearly defined.

Chapter 2

Overview on ESD Protection Design for

Radio-Frequency/High-Speed I/O Interfaces

As discussed in Chapter 1, the performance of radio-frequency (RF) front-end circuits and high-speed input/output (I/O) interface circuits is degraded by the parasitic effects of the electrostatic discharge (ESD) protection devices on the signal path. If the ESD protection device is realized by the PN-junction, MOS transistor, BJT, or silicon-controlled rectifier (SCR), it is capacitive. For the RF front-end circuits, the parasitic capacitance causes signal loss from the I/O pads to the AC ground nodes. Consequently the power gain is lowered and the noise figure is increased. If an inductor is used as the ESD protection device, it exhibits inductive impedance under normal circuit operating conditions. Therefore, the impedance matching conditions are changed. As a result, the center frequency will be shifted if the inductive impedance is not considered in the impedance matching network design. For the high-speed I/O interface circuit, the ESD protection devices are mainly realized with capacitive devices. To mitigate the high-speed performance degradation, the parasitic capacitance of ESD protection devices must be as low as possible. After explaining the trade-off between ESD robustness and high-frequency circuit performance, the reported low-capacitance ESD protection designs are overviewed in this chapter [20], [21].

2.1. Trade-Off Between ESD Robustness and High-Frequency Circuit Performance

To apply the electrostatic discharge (ESD) protection devices to radio-frequency (RF) front-end circuits, the RF performance degradation caused by the ESD protection devices should be characterized carefully. To practically investigate the negative impacts caused by the ESD diode on RF performance, three shallow-trench-isolation (STI) N+/P-well diodes with different device dimensions had been fabricated in a 0.25-μm CMOS process [22]. The N+ diffusion (cathode) and P+ diffusion (anode) are separated by the STI. When the

N+/P-well diode is used as the ESD protection device, the N+ diffusion and the P+ diffusion are connected to the I/O pad and VSS, respectively. The N+/P-well diodes with different N+

diffusion widths of 50 μm, 100 μm, and 150 μm were fabricated in the test chip to investigate their impacts on power gain and noise figure. The measured power gains (S21-parameters) and noise figures of the STI N+/P-well diodes with different device dimensions in the frequency band of 1.2–6 GHz are compared in Fig. 2.1(a) and (b), respectively. The measurement setups of S-parameter and noise figure measurements are also illustrated in the insets of Fig. 2.1.

(a)

(b)

Fig. 2.1. Measured (a) power gains (S21-parameters) and (b) noise figures of the STI N+/P-well diodes with different device dimensions in a 0.25-μm CMOS process.

The measured results showed that the power gain of the STI diode with the same device dimension is decreased when the operating frequency increases. The power gain is decreased drastically by the STI diodes with larger device dimensions in higher frequency bands.

Moreover, the differences of the power gain loss of the STI diodes between different device dimensions become larger in higher frequency bands. This demonstrated that the parasitic capacitance of the ESD protection device losses RF signal to ground and degrades power gain.

Since the power gain loss is larger for larger STI diodes, the larger STI diodes exhibit higher noise figure, as shown in Fig. 2.1(b). On the other hand, ESD robustness is higher as the size of STI diode is increased. The HBM ESD robustness of the stand-alone STI diode is improved from 5.8 kV to over 8 kV as the width is increased from 50 μm to 100 μm. The STI diodes with 50-μm and 100-μm width have the MM ESD robustness of 125 V and 250 V, respectively.

The measured results demonstrated the trade-off between the ESD robustness and RF performance. Devices with larger dimensions have higher ESD level, but they cause more performance degradation. Therefore, how to design an effective on-chip ESD protection circuit for RF front-end and high-speed I/O interface circuits operating in gigahertz frequency bands with minimum performance degradation is a challenge, which must be solved. If high ESD robustness with very slight high-frequency performance degradation is preferred, several low-capacitance ESD protection strategies were reported to be effective. The reported designs are overviewed in the following sections.

2.2. ESD Protection Designs by Circuit Solutions

To mitigate the performance degradation due to ESD protection circuits, circuit design techniques had been used to reduce the parasitic capacitance from the ESD protection device.

With the extra circuit design, the parasitic capacitance of the ESD protection device can be significantly reduced or even cancelled. Furthermore, no process modification is needed by using the circuit design techniques to reduce the parasitic capacitance. However, the silicon area may be increased due to the additional components of extra circuit design. In this section, the ESD protection designs by circuit solutions in standard CMOS processes are overviewed.

2.2.1. Stacked ESD Protection Devices

Although conventional double-diode ESD protection design shown in Fig. 1.6 can be applied to RF frond-end circuits, it is only suitable for small ESD protection devices [23]. In

order to reduce the performance degradation caused by the parasitic capacitances from the ESD diodes at I/O pad, the device dimensions of ESD diodes should be reduced to reduce the parasitic capacitance. However, the minimum device dimensions of ESD diodes can not be shrunk unlimitedly because ESD robustness needs to be maintained. In order to further reduce the parasitic capacitance from ESD diodes without sacrificing ESD robustness, the ESD diodes in stacked configuration had been proposed, as shown in Fig. 2.2 [24], [25]. If the parasitic capacitance of each ESD protection device is CESD and n ESD protection devices are stacked, the overall equivalent parasitic capacitance will theoretically becomes CESD / n Thus, more stacked ESD devices lead to the more significant parasitic capacitance reduction.

Besides reducing parasitic capacitance, the leakage current of ESD diodes under normal circuit operating conditions can be also reduced by using the stacked configuration. Although stacked ESD protection devices can reduce the parasitic capacitance and leakage current, the overall turn-on resistance and the voltage across the stacked ESD protection devices during ESD stresses are increased as well, which is adverse to ESD protection.

Fig. 2.2. ESD protection design with stacked ESD diodes to reduce the capacitance from I/O pad to AC ground nodes.

2.2.2. Impedance Cancellation Technique

Besides, several ESD protection designs with inductor to reduce or cancel the equivalent parasitic capacitance of ESD protection devices had been proposed. Fig. 2.3 shows an ideal parallel LC resonator and the simulated S21-parameter under different frequencies. In a parallel LC resonator composed of the inductance L and capacitance C, the resonant frequency (ω0) is

0

1

ω = LC . (2.2) At the resonant frequency, the signal loss is ideally zero, which denotes that the equivalent capacitance is infinite. Based on this concept, the ESD protection circuit with a parallel inductor had been proposed, as shown in Fig. 2.4 [26]–[30]. The inductance of L1 was designed to resonate with the parasitic capacitance of the ESD protection device at the operating frequency of the RF front-end circuit. With the parallel LC network resonating at the operating frequency, the shunt impedance of L1 and the ESD protection device becomes very large, which can effectively suppress signal loss. Therefore, the ESD protection design using impedance-cancellation technique can mitigate the impacts on circuit performance for circuits operating in a narrow frequency band. L1 can be realized either by the on-chip spiral inductor or by utilizing the bond wire in the package [26]–[29]. Furthermore, the inductor L1

can not only resonates with the parasitic capacitance of the ESD protection device but also serves as an ESD protection device by itself. In this configuration, the DC biases must be equal on both sides of L1. Otherwise, there will be steady leakage current flowing through L1

under normal circuit operating conditions.

Fig. 2.3. Simulated S₂₁-parameter of an ideal parallel LC resonator under different frequencies.

Another ESD protection design using a parallel inductor to cancel the parasitic capacitance of the ESD diode is shown in Fig. 2.5 [31]. Since VDD is an AC ground node, the inductor LP is connected between the I/O pad and VDD to form a parallel LC resonator with the ESD protection device between the I/O pad and VSS. The inductor LP also serves as an ESD protection device between I/O pad and VDD. The inductor and the parasitic

capacitance of the ESD protection device are designed to resonate at the operating frequency of the RF front-end circuit to minimize performance degradation caused by the ESD protection device. With an inductor directly connected between the I/O pad and VDD, the ESD protection device is reverse biased with the largest possible DC voltage under normal circuit operating conditions, which leads to the minimum the parasitic PN-junction capacitance in the ESD protection device. The placement of the inductor and the ESD protection device can be interchanged to provide the same function. In this design, a DC blocking capacitor Cblock is required to provide a separated DC bias for the internal circuits.

Fig. 2.4. ESD protection design with the parallel LC resonator.

Fig. 2.5. ESD protection circuit using the impedance-cancellation technique. The inductor L_P cancels the parasitic capacitance from ESD protection device and provides ESD current path between VDD and the I/O pad.

2.2.3. Impedance Isolation Technique

The low-capacitance ESD protection design utilizing the impedance isolation technique had been reported [22], [32]–[36]. As shown in Fig. 2.6, an LC-tank, which consists of the inductor LP and the capacitor C1, is placed between the I/O pad and VDD. Another LC-tank consisting of the inductor LN and the capacitor C2 is placed between the I/O pad and VSS.

The ESD diodes DP and DN are used to block the steady leakage current path from VDD to VSS under normal circuit operating conditions. At the resonant frequency of the LC-tank, there is ideally infinite impedance from the signal path to the ESD diode. Consequently, the parasitic capacitances of the ESD diodes are isolated, and the impacts of the ESD diodes can be significantly reduced. During ESD stresses, ESD current is discharged through the inductors and the ESD diodes. With the power-rail ESD clamp circuit providing a discharge path between VDD and VSS, the ESD diodes are operated in the forward-biased condition to achieve high ESD robustness under all ESD test modes. Furthermore, the capacitors C1 and C2 can also be directly realized with ESD protection devices to provide other ESD paths apart from the inductors.

Fig. 2.6. ESD protection design with LC-tanks.

Besides only one LC-tank, the modified design with stacked LC-tanks connected between the signal path and the ESD diode had also been proposed, as shown in Fig. 2.7 [32]–[35]. In Fig. 2.7, two or more LC-tanks are stacked to provide better impedance isolation at resonance, which can further mitigate the parasitic effects from the ESD diodes.