Considerations of ESD Protection Design for Radio-Frequency

Although using power-rail ESD clamp circuit between VDD and VSS does not cause any effect on the internal circuits, applying ESD protection devices at the I/O pads inevitably introduce some negative impacts to circuit performance due to their parasitic effects. The

main parasitic effect caused by ESD protection devices which deteriorates the high-frequency performance is the parasitic capacitance. Since the input signal swing is small at the RF input pad, it is sensitive to the shunt parasitic capacitance of ESD protection devices. Therefore, the parasitic capacitance of the ESD protection device at the RF input pad is strictly limited. For the RF transmitter, the devices in the output stage are implemented with large dimensions to transmit the output signals with large enough signal power. With proper design, the devices in the RF output stage can be used to protect the RF output pad against ESD stresses. Thus, ESD protection design for the input pad of the RF receiver is more challenging than that for the output pad of the RF transmitter.

A typical request on the maximum loading capacitance of ESD protection device for a 2-GHz RF input pin was specified as only ~200 fF, which includes the parasitic capacitances of bond pad and ESD protection device [10]. Recently, the negative impacts of ESD protection devices to RF circuit performance had been investigated [11], [12], which had demonstrated that the RF performance such as power gain and noise figure are significantly degraded by the parasitic capacitance of ESD protection devices. The impacts become more serious as the operating frequency of RF front-end circuits and high-speed I/O interface circuits increases. Thus, the parasitic capacitance of ESD protection device must be minimized in ESD protection design for high-frequency applications. Generally, ESD protection circuits cause RF performance degradation with several undesired effects, which are will be discussed in the following.

Parasitic capacitance is one of the most important design considerations for RF ICs and high-speed I/O interface circuits operating in gigahertz frequency bands. Conventional ESD protection devices with large dimensions have the parasitic capacitance which is too large to be tolerated for RF front-end circuits. As shown in Fig. 1.8, the parasitic capacitance of ESD protection devices causes signal loss from the pad to ground. Moreover, the parasitic capacitance also changes the input matching condition. Consequently, the noise figure is deteriorated and the power gain is decreased.

Noise figure is one of the most important merits for RF receivers. Since the RF receiver is a cascade of several stages, the overall noise figure of the RF receiver can be obtained in terms of the noise figure and power gain of each stage in the receiver. For example, if there are m stages cascaded in the RF receiver, the total noise figure of the RF receiver can be expressed as [13]

( )

According to (1.1), the noise figure contributed by the first stage is the dominant factor to the total noise figure of the RF receiver (NFtotal). With the ESD protection circuit added at the input pad to protect the RF receiver IC against ESD damages, the ESD protection circuit becomes the first stage in the RF receiver IC, which is shown in Fig. 1.9. For simplicity, only the first two stages, which are the ESD protection circuit and the low-noise amplifier (LNA), are taken into consideration, as shown in Fig. 1.10. The overall noise figure (NFLNA_ESD) of the LNA with ESD protection circuit is

( )

where L is the power loss of the ESD protection circuit, and NFLNA and NFESD denote the noise figures of the LNA and ESD protection circuit, respectively. Since the ESD protection circuit is a passive reciprocal network, NFESD equals L. This implies that if the ESD protection circuit has 1-dB power loss, the noise figure of the LNA with ESD protection will directly increase 1 dB as well. Thus, the power loss of the ESD protection circuit must be minimized, because it directly increases the total noise figure of the RF receiver and the increased noise figure can not be suppressed by the power gains of succeeding stages.

Moreover, the signal loss due to the ESD protection circuit would also cause power gain degradation in RF circuits.

Fig. 1.8. IC chip with ESD protection devices at the input and output pads.

Another negative impact caused by the ESD protection circuit is the input impedance mismatching, which is particularly critical for narrow band RF circuits. With the ESD

protection circuit added at the input node, the original input matching condition is changed by the parasitic capacitance from the ESD protection circuit. As a result, the center frequency of the narrow band RF circuit is shifted and the power gain is decreased due to impedance mismatching. The impedance mismatching due to ESD protection devices can be mitigated by co-designing the ESD protection circuit and the input matching network. With the co-design of ESD protection scheme and input matching network, the operating frequency can be tuned to the desired frequency. However, the noise figure is definitely increased after ESD protection circuit is added because more devices indicate more noise sources.

Fig. 1.9. Block diagram of an ESD-protected RF receiver.

Fig. 1.10. Block diagram of an LNA with ESD protection circuit. V_S, R_S, and R_L denote the source voltage, source resistance, and load resistance, respectively.

Besides the impacts caused by ESD protection device on RF front-end circuits, the parasitic capacitance of the ESD protection device lowers the operating speed of the high-speed I/O interface circuits, because it takes more time to charge or discharge the input or output nodes to the predefined level. Moreover, the parasitic capacitance of ESD protection devices causes signal loss from the pad to ground, which decreases the signal swings. Moreover, RC delay is another impact caused by the ESD protection circuit. With the ESD protection circuit added to the input and output pads, the parasitic capacitance and parasitic resistance from the ESD protection device and the interconnection introduce RC delay to the input and output signals. Thus, the rising and falling time of the signals at the I/O

pads with ESD protection become longer. As a result, the eye closure is reduced and the inter-symbol interference (ISI) is deteriorated [14].

In addition to parasitic capacitance, the requirements of ESD protection device characteristics under ESD stresses introduce some design considerations. To provide effective ESD protection, the voltage across the ESD protection device during ESD stresses should be carefully designed. First, the trigger voltage and holding voltage of ESD protection device must be designed lower than the gate-oxide breakdown voltage of MOS transistors to prevent the internal circuits from damage before the ESD protection device is turned on during ESD stresses. Second, the trigger voltage and holding voltage of the ESD protection device must be higher than the power-supply voltage of the IC to prevent the ESD protection devices from being mis-triggered under normal circuit operating conditions. Moreover, the turn-on resistance of ESD protection device should be minimized in order to reduce the joule heat generated in the ESD protection device and the voltage across the ESD protection device during ESD stresses. As CMOS process is continuously scaled down, the power-supply voltage is decreased and the gate oxide becomes thinner, which leads to reduced gate-oxide breakdown voltage of MOS transistor. Typically, the gate-oxide breakdown voltage is decreased to only ~5 V in a 90-nm CMOS process with gate-oxide thickness of ~15 Å. As a result, the ESD design window, defined as the difference between the gate-oxide breakdown voltage of the MOSFET and the power-supply voltage of the IC, becomes narrower in nanoscale CMOS technologies [15]. Furthermore, ESD protection circuits need to be quickly turned on during ESD stresses in order to provide efficient discharge paths in time. In summary, ESD protection design in nanoscale CMOS technologies has encountered more challenges.