Biasing Technique

In the conventional I/O buffers, the gate-grounded NMOS (GGNMOS) and gate-VDD PMOS (GDPMOS) are used to provide ESD protection, as shown in Fig. 2.25. To reduce the parasitic capacitance, the ESD protection design with increased reverse-biased voltages across the PN-junctions in the ESD protection devices had been proposed, as shown in Fig.

2.26 [55]. In Fig. 2.26, the PMOS MP2 is used instead of the GGNMOS MN1 in Fig. 2.25. The four diodes DSP1, DDP1, DSP2, and DDP2 denote the parasitic source-to-well and drain-to-well PN-junction diodes in MP1 and MP2, respectively. Since the source and gate terminals of MP1

and MP2 are at equal potentials, MP1 and MP2 are kept off under normal circuit operating conditions. During PD-mode ESD stresses, MP1 is turned on as a diode-connected PMOS to discharge ESD current, and the parasitic diodes DDP1 and DSP2 are forward biased to provide ESD path from the I/O pad to VDD. During NS-mode ESD stresses, MP2 is turned on as a diode-connected PMOS to discharge ESD current. As compared with the GGNMOS MN1 in Fig. 2.26, the parasitic PN-junction diodes of MP2 are reversed biased with larger voltages, which results in smaller parasitic junction capacitance. This is because the cathodes of the parasitic PN-junction diodes are biased to the highest potential in the circuit under normal circuit operating conditions.

(a)

(b)

(c)

Fig. 2.24. Matching loci of (a) ES-DESD, (b) DS-DESD, and (c) π-DESD protection schemes in the Smith chart.

If the voltage across a capacitor can be kept at zero, the effective capacitive loading effect can be ideally eliminated. An ESD protection design utilizing the feedback technique to keep the voltage across the parasitic capacitance to zero had been proposed [56]. As shown in Fig. 2.27, an amplifier in unity-gain configuration is used to keep the voltages across the

base-emitter junctions of Q1 and Q2 to zero. During PD-mode ESD stresses, the base-emitter junction Q1 is forward biased to provide ESD current. During NS-mode ESD stresses, ESD current is discharged from VSS through D2 and the base-emitter junction of Q2. Since the amplifier provides unity-gain feedback across the I/O pad and the bases of Q1 and Q2, ideally a zero voltage is kept across the base-emitter junctions of Q1 and Q2. Thus, the effective parasitic capacitances of the base-emitter junction diodes of Q1 and Q2 are ideally eliminated from the I/O pad.

Fig. 2.25. Traditional ESD protection circuit with GDPMOS and GGNMOS.

Fig. 2.26. ESD protection circuit with increased reverse-bias voltage to reduce the parasitic PN-junction capacitance.

Fig. 2.27. ESD protection circuit utilizing the unity-gain amplifier to keep the voltage across the parasitic capacitance to zero.

2.2.10. Substrate-Triggering Technique

If no extra trigger circuit is added, the parasitic BJTs in MOSFET and SCR are turned on when the avalanche breakdown occurs in the PN-junction. Devices with such a slow turn-on speed and high trigger voltage can not efficiently protect the internal circuit against ESD stresses. To solve the problem, the substrate-triggering technique had been proposed to turn on the ESD protection devices quickly [57]–[59]. The substrate-triggering current is injected into the base of the parasitic BJT in the ESD protection device, which is the substrate or well region in an integrated circuit. Fig. 2.28 shows a low-capacitance ESD protection design utilizing the substrate-triggering technique [60], [61]. During PS-mode ESD stresses, a large current proportional to the transient voltage change flows through the MOS capacitor M2, which can be expressed as

2 2

M M

I C dv

= dt (2.9) where IM2 is the current flow through the MOS capacitor M2, and CM2 is the capacitance of MOS capacitor M2. The current IM2 boosts the gate potential of M6, and turns on M6. With the drain current of M6 flowing into the bulk of M1, the voltage across Rwell rises. When the voltage across Rwell exceeds the cut-in voltage of the bulk-to-source junction diode (which is the base-emitter junction diode of the parasitic BJT), the parasitic BJT in the multi-finger NMOS M1 is uniformly turned on to discharge ESD current. M4 and M5 are used to prevent M6 from being turned on under normal circuit operating conditions. R3 and M7 form the secondary ESD protection circuit, which clamps the voltage at the I/O pad during ESD stresses. In order to eliminate non-linear capacitive load on the I/O pad under different signal

voltages, the diode D1 is added. D1 with a positive coefficient and M6 and M7 with negative voltage coefficients can be co-designed to obtain a constant capacitive load on the I/O pad. In this design, the parasitic junction capacitance of M1 is isolated by D1, so the noise from substrate is significantly reduced. Moreover, adding D1 also reduces capacitive load on the I/O pad because the parasitic capacitances of D1 and M1 are in series configuration.

Fig. 2.28. ESD protection design with the substrate-triggering circuit to turn on the ESD protection device.

Apart from substrate-triggered MOSFET, the whole-chip ESD protection circuit with substrate-triggered SCRs had been proposed, as shown in Fig. 2.29 [62]. As mentioned in section 2.2.1, since the ESD protection diodes between the I/O pad and the power-rails are in series configuration, the parasitic capacitance is reduced. Fig. 2.30 shows the equivalent circuit of Fig. 2.29, in which the SCR is replaced by a PNP and a NPN BJT. During PS-mode ESD stresses, DP2, D1b, the base-emitter junction diode of the NPN BJT in SCR1, and D1a are forward biased, injecting trigger current into the NPN BJT in SCR1. Consequently, SCR1 is turned on, and ESD current is bypassed through two current paths. The first ESD path is through DP2, D1b, the base-emitter junction diode of the NPN BJT in SCR1 and D1a. The second ESD path is through DP2, DP1, SCR1, and D1a. Similarly, the base-emitter junction

Fig. 2.29. Whole-chip ESD protection scheme with the substrate-triggered SCRs and series diodes.

Fig. 2.30. Equivalent circuit of the whole-chip ESD protection scheme of Fig. 2.29.

diode of the PNP BJT in SCR2, D2b, and DN1 are forward biased during ND-mode ESD stresses, injecting trigger current into the PNP BJT in SCR2. With the turned-on SCR2, two ESD current paths are formed during ND-mode ESD stresses. The first ESD path is through D2a, the base-emitter junction diode of PNP BJT in SCR2, D2b, and DN1. The second ESD path is through D2a, SCR2, DN2, and DN1. When the IC is under VDD-to-VSS ESD stresses, eight forward-biased diodes form the discharge path from VDD to VSS, which includes D2a, the base-emitter junction diode of the PNP BJT in SCR2, D2b, DN1, DP2, D1b, the base-emitter junction diode of the NPN BJT in SCR1, and D1a. If the holding voltage of SCR is lower than the power-supply voltage, diodes (D1a and D2a in this design) can be connected in series with the SCR to increase the holding voltage. Otherwise, lachup issue will exist in this circuit.

2.3. ESD Protection Designs by Layout Solutions

Besides circuit solutions, layout solutions had also been utilized to reduce the parasitic capacitance of ESD protection devices. By utilizing layout solutions, some silicon area might be shared to lower the total chip area. Furthermore, no process modification is needed and the ESD protection scheme does not need to be changed by using layout solutions.

2.3.1. Low-Capacitance Layout Structure for MOSFET

The layout structure for MOSFET with low parasitic capacitance had been proposed [63]. The layout top view is shown in Fig. 2.31. The P-well region is defined between the two dotted rectangles in Fig. 2.31. Fig. 2.32 shows the cross-sectional view of the low-capacitance MOSFET.

Fig. 2.31. Layout top view of the low-capacitance NMOS transistor.

Fig. 2.32. Cross-sectional view of the low-capacitance NMOS transistor.

The dotted line in Fig. 2.32 denotes the depletion region edge of the PN-junction under the drain region. The P-well is designed not to lie below most of the drain area, which is connected to the I/O pad. Since the P-well does not exist under the N+ drain region of the NMOS transistor, the space charge region between the N+ drain diffusion and the P-substrate is larger than that of the N+/P-well junction. Thus, the parasitic capacitance is reduced by eliminating the P-well from existing under the drain region. During ESD stresses, the snapback breakdown occurs in the NMOS transistor, which turns on the parasitic NPN BJT in the NMOS transistor to sink ESD current. Because of the relatively low doping level in the PN-junction, the breakdown voltage of the drain-to-substrate junction is higher than that of the drain-to-well junction, resulting in degraded ESD robustness. Thus, a tradeoff exists between the parasitic capacitance and ESD robustness in this design.

2.3.2. Low-Capacitance Layout Structure for SCR

SCR had been demonstrated to be suitable for ESD protection for high-frequency applications, because it has both high ESD robustness and low parasitic capacitance under a small layout area [64], [65]. Layout structures which can reduce the parasitic capacitance of SCR had been investigated [66]–[69]. The layout top view and cross-sectional view of the low-capacitance SCR proposed in [66]–[68] are shown in Fig. 2.33(a) and (b), respectively.

The SCR structure in Fig. 2.33(b) is similar to that of the low-voltage triggering SCR (LVTSCR) [70], [71]. With a low trigger voltage, the LVTSCR can be quickly turned on to protect the internal circuits against ESD damage. During PS-mode ESD stresses, the snapback breakdown occurs in the embedded NMOS, which turns on the parasitic NPN BJTs Q2a and Q2b (formed by the N+ diffusion, P-well, and N+ diffusion) in the embedded NMOS.

The current boosts the base voltage of Q2a and Q2b because of the voltage drop across the P-well resistance (RWell). As the voltage across RWell exceeds the cut-in voltage of the base-emitter junction diodes in the parasitic NPN BJTs Q3a and Q3b, which are formed by the N-well, P-well, and N+ diffusion, Q3a and Q3b are turned on. Consequently, Two SCRs composed of Q1a and Q3a, and Q1b and Q3b are turned on to sink ESD current. With some area overhead, the ESD protection capability can be ideally doubled by splitting the current paths.

The parasitic capacitance of the SCR primarily comes from the N-well/P-well junction and from the N+ diffusion (drain of the NMOS) to P-well junction. In order to reduce the parasitic capacitance, the shallow-trench isolation (STI) has been utilized in the modified design [69]. As shown in Fig. 2.34, the inserted STI reduces the drain-to-well sidewall area

and the N-well-to-P-well boundary area, which leads to reduced parasitic capacitance.

(a)

(b)

Fig. 2.33. Low-capacitance SCR: (a) layout top view, and (b) cross-sectional view.

Fig. 2.34. Cross-sectional view of the modified low-capacitance SCR with STI.

Another ESD protection design utilizing the parasitic SCR is shown in Fig. 2.35(a) [72].

The cascoded NMOS transistors M1 and M2 are used for mixed-voltage I/O applications, which can receive 2×VDD input signal by using only 1×VDD devices without the gate-oxide reliability issue [73], [74]. The diode D1 is used to provide ESD current path from the I/O pad to VDD. The cross-sectional view of this ESD protection design is shown in Fig. 2.35(b), where the NMOS transistors M1 and M2 are realized with multi-finger structure. The P+

(a)

(b)

Fig. 2.35. ESD protection design with a parasitic SCR: (a) circuit schematic, and (b) cross-sectional view.

diffusion, N-well, and P-substrate form the vertical PNP BJT Q1, and the N-well, P-substrate, and N+ diffusion form the lateral NPN BJT Q2. In such a layout structure, the P+ diffusion, N-well, P-substrate, and N+ diffusion form the parasitic SCR to provide ESD current path from the I/O pad to VSS. Since the base terminal of Q1 is biased to VDD, which is the highest potential in the IC, the reverse-biased base-emitter junction capacitance of Q1 is reduced.

Moreover, the emitter, base, and collector and base terminals of Q2 are connected to the AC ground nodes VDD or VSS. Thus, the parasitic capacitance of Q2 does not have any impact to the internal circuits.

2.3.3. Waffle Layout Structure

To save the silicon area and reduce the parasitic capacitance, the MOSFETs realized with the waffle structure had been studied [75]. Similarly, the ESD protection devices had been realized with the waffle structure to optimize ESD robustness [76]–[81]. The ESD protection device with the maximum ratio of perimeter to area is preferred, because it has the maximum ratio of ESD robustness to parasitic capacitance. The ESD protection diode realized with the waffle structure had been proposed [77]–[79]. To maximize the ratio of perimeter to area, small square diffusions are used. The layout top view and cross-sectional view of the P+/N-well waffle diode are shown in Fig. 2.36(a) and (b), respectively. The arrows in Fig. 2.36 show the ESD current paths. The P+ diffusion is implemented in the N-well region and surrounded by the N+ diffusion. Thus, ESD current can be discharged through four directions from the P+ diffusion. To scale the ESD protection capability, multiple P+ diffusions can be connected in parallel to form the waffle diode structure. Under the same ESD robustness, the waffle diode has the reduced parasitic capacitance than that of the traditional ESD diode.

(a) (b)

Fig. 2.36. P+/N-well waffle diode: (a) layout top view, and (b) cross-sectional view.

Besides waffle diodes, SCR with waffle layout structure had been reported [80], [81].

The layout top view and cross-sectional view of the substrate-triggered SCR are shown in Fig.

2.37(a) and (b), respectively. Compared with the waffle diode, the layout of waffle SCR is more complicated, especially the metal routing with multiple waffle SCRs in parallel. It had been verified that the waffle SCR can achieve smaller parasitic capacitance under the same ESD robustness.

(a)

(b)

Fig. 2.37. Waffle SCR: (a) layout top view, and (b) cross-sectional view.

2.3.4. ESD Protection Device Under I/O Pad

To reduce the chip area, ESD protection devices can be placed under the I/O pad, as shown in Fig. 2.38(a) [82]. The contacts in Fig. 2.38(a) connect the diffusion regions to the

(a)

(b)

Fig. 2.38. ESD protection device under the I/O pad proposed in [82]: (a) layout top view, and (b) schematic circuit diagram.

I/O pad. Fig. 2.38(b) illustrates the schematic circuit diagram. The parasitic diodes D1 and D2

provide ESD current paths during PD- and NS-mode ESD stresses, respectively. During PS-mode ESD stresses, the BJT Q3 is turned on when breakdown occurs in the reverse-biased base-collector junction. After Q3 is turned on, the SCR formed by Q3 and Q4 is turned on to discharge ESD current. Similarly, the SCR composed of Q1 and Q2 is turned on during ND-mode ESD stresses to provide ESD protection. With the ESD protection circuit under the bond pad, the parasitic capacitances of the bond pad and ESD protection circuit are series connected from the I/O pad to substrate, resulting in reduced equivalent parasitic capacitance.

Thus, the total parasitic capacitance of the I/O pad and ESD protection circuit is reduced, as compared with the ESD protection device placed beside the I/O pad.

Another ESD protection circuit under the bond pad had been proposed, with its layout top view shown in Fig. 2.39(a) [83]. Fig. 2.39(b) shows the schematic circuit diagram. The diode D1 is formed by the P-well/N-well junction. The PNP BJT Q1 is formed by the P+

diffusion, N-well and P-well, and the NPN BJT Q2 is formed by the N-well, P-well, and N+

diffusion. Q1 and Q2 form an SCR from the I/O pad to VSS. During PS-mode ESD stresses, the junction breakdown occurs in D1, which turns on the SCR to discharge ESD current. The parasitic capacitance connected to the I/O pad is only the P+/N-well junction capacitance, which is the base-emitter junction capacitance of Q1. Moreover, the parasitic capacitance from the I/O pad to the grounded P-well region is reduced because the ESD protection circuit is placed under the bond pad.

(a) (b)

Fig. 2.39. ESD protection device under the I/O pad proposed in [83]: (a) layout top view, and (b) schematic circuit diagram.

2.4. ESD Protection Designs by Process Solutions

The third approach to reduce the parasitic capacitance from the ESD protection device is to modify the fabrication process. Besides standard CMOS processes, ESD protection devices fabricated in some modified processes had been reported to reduce the parasitic capacitance.

However, chip fabrication cost will be increased because of process modification.

2.4.1. Symmetrical SCR Structure

Fig. 2.40(a) shows the cross-sectional view of a symmetrical SCR structure in the process with the N+ buried layer and P- layer [84]. With the high-concentration N+ buried layer, the clamping voltage of the SCR is reduced, which leads to more efficient ESD protection. Moreover, the deep-trench isolation separates the symmetrical SCR structure from the internal circuits, which is beneficial for latchup prevention. In the ESD protection device, the anode and cathode sides are junction-isolated, which reduces the parasitic capacitance.

The overall reduction in parasitic capacitance is due to its smaller junction area and the series-connected parasitic capacitances of the two P-well/N+ buried layer junctions. Fig.

2.40(b) shows the schematic circuit diagram of this ESD protection device, in which the anode is connect to the I/O pad, and the cathode is connected to VSS. P-Well_1, N+ buried layer, P-Well_2, and N+ diffusion form the first SCR from anode to cathode. P-Well_2, N+

buried layer, P-Well_1, and N+ diffusion form the second SCR from cathode to anode. The N+ diffusion which is connected to anode, P-Well_1, and N+ buried layer form the NPN BJT Q4. The N+ diffusion which is connected to cathode, P-well_2, and N+ buried layer form the NPN BJT Q2. The N+ buried layer and N-well form the base of the BJT Q1, and the P-Well_1 and P-Well_2 form the emitter and collector of the BJT Q1, respectively. The first vertical BJT Q5 is formed by the P- layer, N+ buried layer, and P-Well_1. The second vertical BJT Q3

is formed by the P- layer, N+ buried layer, and P-Well_2. During PS-mode ESD stresses, The avalanche breakdown occurs at the N+ buried layer/ P-Well_2 junction in Q1, increasing current through Q1. As current flows through the parasitic resistance in P-Well_2 (RPwell_2), the voltage across the base-emitter junction of Q2 increases. When the voltage across the base-emitter junction of Q2 exceeds its cut-in voltage, Q2 is turned on, and the SCR composed of Q1 and Q2 is turned on to sink ESD current. Similarly, the SCR composed of Q1

and Q4 is turned on to sink ESD current during NS-mode ESD stresses.

(a)

(b)

Fig. 2.40. ESD protection device with symmetrical SCR: (a) cross-sectional view, and (b) schematic circuit diagram.

2.4.2. Low-Capacitance MOSFET

In section 2.3.1, it has been mentioned that the parasitic capacitance can be reduced by lowering the concentration of the PN-junction. The similar idea using an extra mask to lower the concentration at the drain-to-well junction had been proposed [85]. The cross-sectional

view of the low-capacitance PMOS transistor is shown in Fig. 2.41. The drain and source regions are surrounded by the lightly-doped P-type (P-) regions. The N- region under the drain is counter-doped with P-type material to reduce the effective N-type concentration.

Since the depletion region of the P+/N- junction is larger than that of the P+/N-well junction, the parasitic capacitance is reduced.

Fig. 2.41. Cross-sectional view of the low-capacitance PMOS proposed in [85].

2.5. Discussion and Comparison

The comparison among various ESD protection designs for RF front-end circuits and high-speed I/O interface circuits is summarized in Table 2.1. The evaluated parameters are explained as following.

z Design Complexity:

− “Low”: The stand-alone ESD protection device is the ESD protection circuit without extra auxiliary component.

− “Moderate”: The stand-alone ESD protection device is the ESD protection circuit without extra auxiliary component, but the layout of the ESD protection device needs careful consideration.

− “Moderate”: The stand-alone ESD protection device is the ESD protection circuit without extra auxiliary component, but the layout of the ESD protection device needs careful consideration.