Chapter 1 Introduction
1.3 Organization of This Thesis
This thesis is divided into four chapters.
In Chapter 2, we briefly describe the key process flow for fabricating the NMOS
devices with buffer layers. In order to verify the effect of buffer layers under hot carrier
stress, splits with different buffer layers were fabricated and characterized. In addition,
we present the characterization method and the stress conditions.
In Chapter 3, we show and discuss the improvement on device performance with
buffer layer. The effectiveness of the buffer layers on alleviating the hot-carrier
degradation of the locally strained devices with buffer layers is evaluated and addressed.
Finally, important conclusions generated from our experimental results are
summarized, and some recommendations and suggestions for future work are given in
Chapter 4.
Chapter 2
Device Fabrication and Measurement Setup
2.1 Device Fabrication and Process Flow
The NMOSFETs were fabricated on 6-inch p-type (100) Si wafers with resistivity
of 15~25Ω-cm and thickness of 655~695 μm. Additional p-type substrate doping was
performed first by BF2+ implantation at 100 keV and 1×10-13 cm-2. Next, standard local
oxidation of silicon (LOCOS) process with channel stop implant (by BF2+
implantation
at 120 KeV and 4×10-13 cm-2) was used for device isolation. Threshold voltage
adjustment and anti-punch through implantation were done by implanting 40 KeV BF2+
and 35 KeV B+, respectively. After the growth of 3 nm thick thermal gate oxide, a
150nm undoped poly-Si layer was deposited by low-pressure chemical vapor deposition
(LPCVD), followed by gate etch process to pattern the poly-Si film. The Source/drain
(S/D) extension regions were then formed by As+ implantation at 10 KeV and 5×10-14
cm-2. After an 80nm TEOS spacer formation, S/D regions were formed by P+
implantation at 15 KeV and 5×10-15 cm-2. Then the patterning of the substrate doping
regions was performed through lithography and etching processes, followed by a BF2+
implantation at 40 KeV and 5×10-15 cm-2. Rapid thermal anneal (RTA) was subsequently
carried out in a nitrogen ambient at 900°C for 30 sec to activate dopants in the gate, S/D,
and substrate regions.
Afterwards, some samples were capped with a TEOS or a poly-Si to serve as the
buffer layer. The thickness of the buffer layer is 10 nm. Then a SiN capping layer
(contact-etch-stop-layer, CESL) of 300nm was deposited on some wafers both with or
without the buffer layer. The SiN deposition was performed at 780 ℃ with SiH2Cl2
and NH3 as the reaction precursors using low-pressure chemical vapor deposition
(LPCVD) system. After the SiN capping, a 300nm TEOS passivation layer was
deposited by an LPCVD system.
To simulate the effect of deposition temperature during the SiN deposition, the
control devices (i.e., without SiN capping) received a placebo treatment (i.e., the same
temperature and treatment time as that used in the SiN deposition) in N2 ambient. After
contact hole etching, normal metallization was carried out for all samples. The final step was a forming gas anneal performed at 400°C for 30 min to mend dangling bonds and
reduce interface state density in the gate oxide/Si interface. Cross-sectional view of the
fabricated device was shown in Fig. 2.1.The five split conditions stated above are
summarized in Table 2.1.
2.2 Electrical Measurement Setup
Current-voltage (I-V) and capacitance-voltage (C-V) characteristics were evaluated
by an HP4156A precision semiconductor parameter analyzer and an HP4284 LCR meter,
respectively. Temperature-regulated hot chucks were used to maintain the measurement temperature at 25°C.
2.3 Charge Pumping Measurement 2.3.1 Basic Theory
The charge pumping principle for MOSFETs has been applied to characterize the
fast interface traps in MOSFETs. The original charge pumping method was introduced
by Brugler and Jespers [32], and the technique was then developed by Heremans [33].
This technique is based on a recombination process at the Si/SiO2 interface involving
the surface traps. It consists of applying a constant reverse bias at the source and drain,
while sweeping the base level of the gate pulse train from a low accumulation level to a
high inversion level. The frequency and the rise/fall time are kept constant. When the
base level is lower than the flat-band voltage while the top level of the pulse is higher
than the threshold voltage, the maximum charge pumping current occurs. This means
that a net amount of charge is transferred from the source and drain to the substrate via
the fast interface traps each time the device is pulsed from inversion toward
accumulation. The charge pumping current is caused by the repetitive recombination at
interface traps. As a result, the recombination current measured from the bottom
(substrate) is the so-called charge pumping (CP) current [34]. The CP current can be
given by:
ICP = q · f · W · L · Nit. (2.1)
According to this equation, the current is directly proportional to the interface trap
density in the channel, the frequency, and the area of the device. However, when the top
level of the pulse is lower than the flat-band voltage or the base level is higher than the
threshold voltage, the fast interface traps are permanently filled with holes in
accumulation or the electrons in inversion in NMOSFETs. As a result, there is no
recombination current and no charge pumping current can be detected.
2.3.2 Basic Measurement Setup
The basic setup of charge pumping measurement is shown in Fig. 2.2. In this
thesis, “fixed amplitude sweep” is used to calculate interface trap density, and “fixed
base sweep” is used to analyze the lateral distribution of interface trap, respectively. The
source and drain are biased at 50mV. The substrate electrodes of tested devices are
grounded. A 1MHz (the frequency can be modulated for different devices) square pulse
waveform provided by HP8110A with fixed amplitude is applied to the NMOS gate.
The base voltage is varied to let surface condition switch from inversion to
accumulation, while keeping the pulse amplitude at 1.5V. In our measurement setup,
Vbase is varied from -2V to -0.2V in step of 0.05V. The parameter analyzer HP4156A is
used to measure the charge pumping current (ICP).
2.4 Hot Carrier Reliability Measurement Setup
In our reliability measurement, the device was stressed with the drain voltage at a
highly positive voltage, and the gate terminal biased at the voltage where maximum Isub
occurs to accelerate the degradation. So we must first measure the Isub-VG with a fixed
drain bias to find VG@Isubmax, before stressing the device. To monitor the degradation
caused by the hot electrons, the ID-VG characteristics at VDS = 0.05 V (linear region) and
charge pumping current were measured before and after the stress. The degradations in terms of threshold voltage shift (∆Vth), interface trap density degradation (∆Nit), and
transconductance degradation (∆Gm), were recorded in the accelerated stress test.
2.5 Extraction Procedure of Lateral Distribution of Nit
The lateral distribution of interface state after hot carrier stress of all splits was also
discussed in this work. This method builds on [35] and the measurement setup is shown
in Fig. 2.3. The experimental procedures are described below.
(1) Measure the Icp-Vh curve on a virgin MOSFET from the drain junction (with the
source junction floating), and from which the relationship between Vh and Vth(x) near
the junction of interest is established [36].
(2) Record the Icp-Vh curve after hot-carrier injection.
(3) The hot-carrier-induced interface state distribution, Nit(x), is obtained from the
difference of the Icp-Vh curves before and after the stress.
Chapter 3
Experimental Results and Discussion
3.1 Electrical Characteristics of Locally Strained NMOSFETs with Buffer Layer
3.1.1 Fundamental Electrical Characteristics
First of all, our goal is to investigate the effect of thermal budget associated with
the SiN deposition. So, for the placebo split, we deliberately added an additional
thermal treatment step in N2 with an identical temperature and treatment time as those
used in the SiN deposition (i.e., at 780℃ ambient for 3 hours) before the TEOS
passivation layer deposition. Samples which were skipped both the SiN deposition and
the thermal N2 annealing steps were also fabricated for comparison, denoted as the REF
(reference) split. Fig.3.1 shows the effect of such placebo thermal treatment on the
capacitance-voltage(C-V) characteristics of devices without SiN capping. In this figure,
the device with the additional thermal budget (placebo split) shows apparent
poly-depletion effect. We believe this is caused by the temperature-dependent solid
solubility of dopants in poly gates [37], as shown in Fig. 3.2. In other words, the
original solid solubility (approaching the equilibrium value at 900℃, which is caused
by the rapid thermal anneal (RTA) step) is lowered by the furnace SiN deposition step
due to the additional thermal budget. The placebo split shows larger threshold voltage
due to the reduction of fixed charge in gate oxide. The C-V characteristics of
MOSFETS are also important in verifying the oxide quality and the equivalent oxide
thickness (EOT). Fig. 3.3 exhibits C-V characteristics of NMOSFETs for all splits (i.e.
placebo (thermal budget), SiN, TEOS/SiN, POLY/SiN). The curves of four splits are
basically identical. It gives an equal ground to compare the performance of all splits. So
the split with placebo thermal budget (i.e., the placebo split) serves the role of the
control split, and will also be called the control split interchangeably. Fig. 3.4 shows
cumulative probability distributions of the sheet resistance of the poly gate for all splits.
The REF (i.e., W/O thermal budget) split has lower sheet resistance values, while the
other four splits exhibit almost same distribution of sheet resistance. This demonstrates
that the additional thermal treatment step used in the SiN deposition indeed results in
worse poly-depletion effect.
The Id-Vg characteristic of the split conditions are shown in Fig. 3.5. From the
figure, there is no obvious difference in the transconductance (Gm) among all samples
except the placebo split, clearly revealing the enhancement of transconductance by the
strained technology. The off-state leakage current and the subthreshold slope show no
distinguishable difference in Fig. 3.5, indicating that the devices with strained channel
do not show major influence on the fundamental properties. Fig. 3.6 depicts the
subthreshold swing for all splits, and the results indicate that the values are confined in
a narrow range between 74~75 mV/decade. The output characteristics of all splits are
shown in Fig. 3.7. It is seen that the insertion of the buffer layer prior to SiN deposition
(i.e., TEOS/SiN, POLY/SiN) does not degrade the current enhancement. Consistent with
previous literature report [38], the NMOS drive current can be enhanced by a thicker
SiN etch-stop layer which is tensile in nature.
Fig. 3.8 shows the percentage increase of the transconductance among different
splits relative to the placebo devices (i.e., w/o SiN capping). The transconductance
enhancement reaches about 29% and 33% at a channel length of 0.5µm and 0.4µm,
respectively. We can see that when the channel length decreases, the strain effect
enhances. In other words, the strain is distributed locally inside the channel and
concentrated near the source and drain. As a result, the transconductance enhancement
becomes more prominent with decreasing channel length. This is explained by the
splitting of the degeneracy at the conduction band edges under uniaxial strain [24] as
mentioned above. Fig. 3.9 exhibits the percentage increase of the saturation current for
the split samples relative to the placebo devices (i.e., w/o SiN capping). From Fig. 3.9,
it can be seen that similar trend to that shown in Fig. 3.8 is observed.
Fig. 3.10 shows the results of charge pumping measurement for some splits (i.e.,
placebo (thermal budget), REF, and SiN). First, we focus on the impact of thermal
budget associated with the SiN deposition. From the figure, we find that a large amount
of interface states is generated during SiN capping process as compared with the
samples without the capping layer, implying that the channel strain indeed causes the
increase of interface states at the Si/SiO2 interface. Nevertheless, it is well known that
hydrogen species can effectively passivate the dangling bonds at the Si/SiO2 interface.
For the LPCVD system used for SiN deposition in this study, SiH2Cl2 and NH3 were
employed as the reaction precursors, so the reaction chamber would be filled with
hydrogen species during the deposition process. The hydrogen species would in turn
passivate the interface trap states at the Si/SiO2 interface. Although this factor should
not be ignored, in this figure such effect obviously is masked by the channel strain. In
other words, the number of interface states passivated by the hydrogen species is much
less than that generated by the channel strain.
On the other hand, the figure also proves that the annealing performed in N2 tends
to reduce the interface states density, indicating this factor (thermal budget of the
deposition) alone is beneficial for improving the interface properties. From Fig. 3.10,
impacts of the three factors, namely, channel, incorporated hydrogen species, and the
thermal budget, on interface state density are identified.
Comparisons of charge pumping current between the strain and placebo samples
are shown in Fig. 3.11. The placebo sample exhibits the lowest charge pumping current
among all splits, while the device with TEOS buffer layer exhibits the highest. The
curve of the device with POLY/SiN is slightly higher than that with SiN, but less than
that with TEOS buffer layer. The results indicate that the TEOS buffer layer can
effectively block the diffusion of hydrogen into the channel region, while such barrier
effect seems to be reduced for the POLY buffer layer. It has been pointed out previously
that the poly-silicon is a diffusion barrier of the hydrogen [39]. But it should be noted
that, the precursor gas (SiH4) for deposition is also H-containing. Before the SiN
deposition, the abundant hydrogen species may have spread to the Si/SiO2 interface to
passivate the interface states. In summary, TEOS buffer layer has been shown to be
more effective in blocking the hydrogen diffusion into the Si/SiO2 interface.
3.1.2 Short Channel effect
Threshold voltage (Vth) roll-off characteristics of the placebo (thermal budget) and
REF splits are shown in Fig. 3.12. The results are obtained at VDS = 0.05 V. From the
figure, both splits depict reverse-short-channel-effect (RSCE). This can probably be
explained by boron segregation at the implant-damaged regions located near the edge of
the channel [40]. Devices with additional thermal budget show improved
reverse-short-channel-effect [40]. It might be related to the redistribution of dopants that
effectively reduces the boron segregation effect, explaining the suppression of the
RSCE shown in Fig. 3.12.
In Fig. 3.13, it is worth noting that the placebo samples depict the
reverse-short-channel-effect (RSCE). However, this phenomenon is not observed on
three SiN-capped splits (SiN, TEOS/SiN, POLY/SiN). Instead, theses three splits
exhibit similar and significant threshold voltage roll-off trend. It is believed that the
bandgap narrowing effect is the culprit to accelerate the Vth roll-off in the strained
channel device [28, 41]. The strain stress may also result in the channel dopants
redistribution [42, 43]. In brief, the channel strain associated with the SiN capping
devices (SiN, TEOS/SiN, POLY/SiN) would lead to aggravated Vth roll-off.
Drain induced barrier lowing (DIBL) is another pointer in evaluating the short
channel effects. We use the interpolation method to calculate DIBL effect for all splits.
The results are shown in Fig. 3.14. It is clearly seen that there is no distinguishable
difference among all splits. It appears that devices with SiN capping and buffer layers
will not complicate the DIBL effect of the samples.
3.2 Hot Carrier Degradation of Locally Strained NMOSFETs with Buffer Layer
A hot carrier with sufficient energy can create more charge carriers through impact
ionization. For NMOSFET devices, holes generated by impact ionization are collected
by the substrate. Fig. 3.15 shows the substrate current (Isub) versus gate voltage for all
splits of devices at VD of 4.6 V. It can be seen that the three strained-channel splits
exhibit almost identical maximum substrate current which are much higher than that of
placebo sample. This result shows clearly that the channel strain plays an important part
in affecting the generation of channel hot electrons and the associated impact ionization
process. Bandgap narrowing and mobility enhancement, both due to channel strain, are
mainly responsible for enhancing the ionization rate [44]. So the SiN-capped devices
show larger substrate current than the placebo samples.
Hot-carrier effects and the induced degradation were investigated to study the
impact of the SiN capping and buffer layers. As discussed above, it is expected that the
split with SiN capping (i.e. SiN) would show aggravated hot carrier degradation. Fig.
3.16 and Fig. 3.17 show threshold voltage shift and increased interface state density,
respectively, as a function of stress time for all splits that received hot-electron stressing
at VDS = 4.6 V and VGS at maximum substrate current. All devices are with channel
width/length = 10µm/0.5µm. As expected, the split with SiN capping shows the worst
hot carrier degradation, and the use of buffer layer apparently improves hot carrier
degradation. We assume that the bandgap narrowing effect and the increased carrier
mobility in the strained channel devices [44, 45] are the two primary culprits for the
aggravated hot carrier degradations. These two factors may increase the substrate
current in the device, as evidenced in Fig. 3.15, and lead to higher degradation.
The H-passivated bonds at the interface also play a role in the hot-carrier
degradation process. Since the hot carriers tend to break the Si-H bonds during the
process, the higher the amount of the Si-H density, the severer the degradation. The
TEOS buffer layer can block the diffusion of hydrogen species into the channel region,
less broken Si-H bonds and thus less interface states are generated during the stressing
as compared with the SiN-capped devices. As a consequence, better reliability is
achieved, as evidenced in Fig. 3.16 and Fig. 3.17. For the devices with POLY buffer
layer, less improvement is achieved due to higher amount of Si-H bonds, as stated
above. Fig. 3.18 illustrates the 10-year reliability projections for the four splits. Lifetime
is defined as 40mV of ΔVth. The observed trend is the same as that shown in Fig. 3.16.
Strained devices show poor hot carrier reliability than placebo device, although the use
of buffer layer can alleviate hot carrier degradation.
Typical results of hot-electron stressing for the four splits of samples are shown in
Fig. 3.19 and Fig. 3.20. Channel width and length of the test devices are 10μm and 0.5
μm, respectively. The devices are stressed at VDS = 4.9 V and VGS at maximum
substrate current. The ID-VG characteristics at VDS = 0.05 V are measured before and
after the stress to evaluate the degradation caused by the hot electrons. As shown in Fig.
3.19 and Fig. 3.20, the degradation is the worst in the SiN-capped sample without buffer
layer among the four splits. The aggravation is alleviated in the devices with buffer
layer (i.e. TEOS/SiN, POLY/SiN), though the resultant degradation is still worse than
that of the placebo counterpart.
3.3 Analysis of the Lateral Distribution of Interface Trap Density
The measurement methods presented in Section 2.5 was used to extract lateral
distribution of interface trap state. It should be noted that the local Vth and Vfb, across
the channel of MOSFET, are not uniform due to the lateral doping variation, as shown
in Fig. 3.21. In order to detect the interface state, the voltage pulses applied during
measurement must undergo alternating accumulation and inversion cycles. Therefore,
there should be no Icp when the high-level voltage (Vh) is lower than the minimum Vth
under the gate. Only after Vh starts to exceed the local Vth in the channel will Icp begin
to grow. Before Vh reaches the maximum local Vh in the channel, only interface states
residing near the drain side will contribute to Icp, as the needed electrons cannot yet
flow to the drain side from the source.
We choose the placebo split as an example. If we assume that the interface state
density is spatially uniform along the channel, which can be written as
ICP = q · f · W · L · Nit. (3-1)
where f is the gate pulse frequency, W is the channel width, and L is the channel
length. Since Vth is not uniformly distributed, when Vh reaches the maximum local Vth
in the channel, only interface state residing near the drain side (i.e., the shadow region