Analysis of the Lateral Distribution of Interface Trap Density 24

Chapter 3 Experimental Results ans Discussion

3.3 Analysis of the Lateral Distribution of Interface Trap Density 24

The measurement methods presented in Section 2.5 was used to extract lateral

distribution of interface trap state. It should be noted that the local Vth and Vfb, across

the channel of MOSFET, are not uniform due to the lateral doping variation, as shown

in Fig. 3.21. In order to detect the interface state, the voltage pulses applied during

measurement must undergo alternating accumulation and inversion cycles. Therefore,

there should be no Icp when the high-level voltage (Vh) is lower than the minimum Vth

under the gate. Only after Vh starts to exceed the local Vth in the channel will Icp begin

to grow. Before Vh reaches the maximum local Vh in the channel, only interface states

residing near the drain side will contribute to Icp, as the needed electrons cannot yet

flow to the drain side from the source.

We choose the placebo split as an example. If we assume that the interface state

density is spatially uniform along the channel, which can be written as

ICP = q · f · W · L · Nit. (3-1)

where f is the gate pulse frequency, W is the channel width, and L is the channel

length. Since Vth is not uniformly distributed, when Vh reaches the maximum local Vth

in the channel, only interface state residing near the drain side (i.e., the shadow region

in Fig. 3.21) will contribute to Icp. In Fig. 3.22, the corresponding Icp(Vh) comes from

the interface state distributed in the region between the gate edge and the position where

its local Vth equals Vh, i.e.,

( )

cp h it

I V =q f N W x (3-2)

where x represents the distance from the gate edge to the position where Vth (x) = Vh.

Comparing (3-1) and (3-2), we can derive

( )

Fig.3.23 shows the local Vth versus distance x of the placebo sample. The local Vth

decreases sharply as x is smaller than 0.09 µm. We can therefore presume that the drain

junction is near x = 0.09 µm.

After subjecting to 100 second of hot carrier stress (VG@Isubmax and VDS = 4.9 V), the incremental charge pumping current (∆Icp), as shown in Fig. 3.24, at a given Vh is

proportional to the number of generated interface traps from the gate edge to the point x.

∆Icp can be written as

Therefore, the Nit(x) generated by the hot carrier stress can be expressed as

follows:

The relationship of dV^h

dx versus x can be derived from V_h versus x, so the lateral distribution, Nit (x), could be obtained from the procedure mentioned above.

By the same procedure, the derived profiles of the interface states for all splits of

devices could be extracted by Eq.(3-5), and the result are shown in Fig. 3.25. From this

figure we can directly probe the position-dependent damage characteristics by

calculating the amount of interface states generated by the hot-carrier stress at different regions. We can see that the major damage region is confined within 0.1 µm near the

drain edge in all splits. This is reasonable since the hot-carrier effect is known to be

localized in nature. It is obviously seen that the interface state generation sharply

increases in SiN-capped sample (i.e. SiN, TEOS/SiN, POLY/SiN) near the drain region,

but the buffer layer samples show smaller degradation than the SiN-capping split

without buffer layer. These results are consistent with those mentioned above in Section

3.2. In short, channel strain is responsible for the aggravated hot carrier degradations

observed in SiN-capped samples. However, the devices with buffer layer show

alleviated hot carrier degradation and improved device reliability.

Chapter 4 Summary and Conclusion

4.1 Summary and Conclusion

In this thesis, the effects of LPCVD SiN layer and the associated deposition

process on the device characteristics and hot-electron degradation are investigated. A

novel scheme involving the insertion of a buffer layer between the SiN and the gate for

improving the device reliability was proposed and demonstrated. Several important

phenomena are observed and summarized as follows:

(1) The buffer layer before SiN deposition would not degrade the device

performance. For example, the enhancement ratio of transconductance in the device

with the buffer layer is found to be around to 33% at a channel length of 0.4μm, which

is essentially identical to the enhancement ratio observed in the SiN-capped device.

(2) The thermal budget associated with the deposition of the SiN capping layer

could reduce the interface states and alleviate the reverse short-channel effect, although

the poly-depletion effect becomes worse. The bandgap narrowing effect due to the

channel strain may result in further lowering in Vth as the channel length is shortened.

(3) The TEOS buffer layer could prevent hydrogen species from diffusion during

to the use of the H-containing precursor (e.g. SiH4) in the deposition step.

(4) Hot-electron degradation is adversely affected when the SiN is deposited over

the gate as compared with the placebo samples. When a buffer layer is capped prior to

the SiN deposition, although still worse than the placebo ones, significant improvement

over that without the buffer could be obtained. From the measurement of the

distribution of interface trap density, enhance edge effects caused by the hot carrier

stress are resolved.

In this work, we found that hydrogen species is the primary culprit for aggravated

reliabilities in strained devices. The insertion of a buffer layer serves to alleviate the

device hot-carrier degradations. Optimization of SiN deposition process and/or use of

the new buffer layer (e.g., high-k film) are thus essential for the implementation of the

uniaxial strain in NMOS devices.

Reference:

[1] S.H. Olsen, K.S.K. Kwa, L.S. Driscoll, S. Chattopadhyay and A.G. O’Neill, “Design, fabrication and characterisation of strained Si/SiGe MOS transistors”, IEE Proc.-Circuits Devices Syst., Vol. 151, No. 5, October 2004.

[2] J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald, D.

A. Antoniadis, “Strained silicon MOSFET technology”, in IEDM Tech. Dig., pp.

23-26, 2002.

[3] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K.

Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M.

Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors”, in IEDM Tech. Dig., pp. 978-980, 2003.

[4] S. Pidin, T. Mori, K. Inoue, S. Fukuta, N. Itoh, E. Mutoh, K. Ohkoshi, R. Nakamura, K. Kobayashi, K. Kawamura, T. Saiki, S. Fukuyama, S. Satoh, M. Kase, and K.

Hashimoto, “A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films”, in IEDM Tech.

Dig., pp. 213-216, 2004.

[5] C. Y. Lu, H. C. Lin, Y. F. Chang, and T. Y. Huang, “Device characteristics and aggravated negative bias temperature instability in PMOSFETs with uniaxial compressive strain”, int. Conference on Solid State Devices and Materials, pp.

874-875, 2005.

[6] E. Li, E. Rosenbaum, J. Tao, and P. Fang, “projecting lifetime of deep submicron MOSFETs”, IEEE Trans. on Electron Devices, vol. 48, pp. 671-678, April 2001.

Katsumata, and H. Iwai, “A study of hot-carrier degradation in n- and p-MOSFETs with ultra-thin gate oxides in the direct-tunneling regime”, in IEDM Tech. Dig., pp.

453-456, 1997.

[8] A. Schwerin, W. Hansch, and W. Weber, “The relationship between oxide charge and device degradation: A comparative study of n- and p- channel

MOSFET's”, IEEE Trans. on Electron Devices, vol. ED-34, pp. 2493-2500, December 1987.

[9] P. Heremans, R. Bellens, G. Groeseneken, and H. Maes, “Consistent model for the hot-carrier degradation in n-channel and p-channel MOSFETs”, IEEE Trans. on Electron Devices, vol. 35, pp. 2194-2209, December 1988.

[10] C. Y. Lu, “A Study of Drive Current Enhancement Methods and Related Reliability Issues for MOSFETs”, A Dissertation in Department of Electronics Engineering &

Instisute of Electronics in NCTU, pp. 122-148, July 2006

[11] S. Takagi, T. Mizuno, T.Tezuka, N. Sugiyama, T. Numata, K.Usuda, Y. Moriyama, S. Nakaharai, J. Koga, A. Tanabe, N. Hirashita, and T. Maeda, “Channel structure

design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs”, in IEDM Tech. Dig., pp.57-60, December 2003.

[12] S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R, Chau, G. Glass, T, Hoffman, J. Klaus, Z. Ma, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El-Mansy, “A logic nanotechnology featuring strained-silicon”, IEEE Electron Device Lett., vol. 25, pp.191-193, April 2004.

[13] W. Zhao, J.He, R. E. Belford, L. Wernersson, and A. Seabaugh, “Partially depleted SOI MOSFETs under uniaxial tensile strain”, IEEE Trans. Electron Devices, vol. 51, pp.317-323, March 2004.

and D. A. Antoniadis, “Straind silicon MOSFET technology”, in IEDM Tech. Dig., pp.23-26,December 2002.

[15] A. Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, H. Sato, and F. Ootsuka, “Local mechanical-stress control (LMC): A new technique for CMOS-performance enhancement”, IEDM Tech. Dig., pp. 433-436, December 2001.

[16] G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, “NMOS Drive current reduction caused by transistor layout and trench isolation induced stress”, IEDM Tech. Dig., pp.827-830, December 1999.

[17] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K.

Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M.

[18] A. Steegen, M. Stucchi, A. Lauwers, and K. Maex, “Silicide induced pattern density and orientation dependent transconductance in MOS transistors”, IEDM Tech. Dig., pp.497-500, December 1999.

[19] S. Maikap, M. H. Liao, F. Yuan, M. H. Lee, C. Huang, S. T. Chang, and C. W.

Liu, ”Package-strain-enhanced device and circuit performance”, IEDM Tech. Dig., pp.233-236, December 2004.

[20] C. Hu, “Device challenges and opportunities”, in Symp. VLSI Tech. Dig., pp.4-5, 2004

[21] S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, S.

Kuroki,N.Ikezawa, T. Suzuki, T. Saitoh, and T. Horiuchi, “Mechanical stress effect

Tech. Dig., pp.247-250, December 2000.

[22] C. Zhi-Yuan, M. T. Currie, C. W. Leitz, G. Taraschi, E. A. Fitzgerald, J. L. Hoyt, and D. A. Antoniadis, “Electron mobility nhancement in strained-Si n-MOSFET fabricated on SiGe-on-insulator (SGOI) substrates”, IEEE Electron Device Lett., vol.22, pp.321-323, July 2001.

[23] S. E. Thompson, G. Sun, K. Wu, J. Kim, and T. Nishida, “Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs”, IEDM Tech. Dig., pp.221-224, December 2004.

[24] B. M. Haugerud, L. A. Bosworth, and R. E. Belford, “Mechanically induced strain enhancement of metal--oxide--semiconductor field effect transistors”, J. Appl.

phys., Vol.94, pp.4102-4107, 2003

[25] M.D.Giles, M.Armstrong, C.Auth, S.M.Cea, T.Ghani, T.Hoffmann, R.Kotlyar, P.Matagne, K.Mistry, R.Nagisetty, B.Obradovic, R.Shaheed, L.Shifren, M.Stettler, S.Tyagi, X.Wang, C.Weber, K.Zawadzki, “Understanding stress enhanced performance in Intel 90nm CMOS technology”, VLSI Symp. Tech. Dig., pp.118-119, 2004

[26] C. W. Leitz, M. T. Currie, M. L. Lee, Z. -Y. Cheng, D. A. Antoniadis and E. A.

Fitzgerald, “Hole mobility enhancements and alloy scattering-limited mobility in tensile strained Si/SiGe surface channel metal–oxide–semiconductor field-effect transistors”, J. Appl. phys., Vol.92, pp.3745-3751, 2002

[27] M. V. Fischetti, Z. Ren , P. M. Solomon, M. Yang, and K. Rim, “Six-band k·p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness”, J. Appl. phys., Vol.94, pp.1079-1095, 2003

[28] J. Goo, Q. Xiang, Y. Takamura, F. Arasnia, E. N. Paton, P. Besser, J. Pan, and M.

Electron Device Lett., Vol. 24, pp.568-570, September 2003.

[29] E. Li, E. Rosenbaum, J. Tao, and P. Fang, “Projecting lifetime of deep Submicron MOSFETs”, IEEE Trans. on Electron Devices, vol. 48,pp. 671-678, April 2001.

[30] H. S. Momose, S. Nakamura, T. Ohguro, T.Yoshitomi, E. Morifuji, T. Morimoto, Y.

Katsumata, and H. Iwai, “A study of hot-carrier degradation in n- and p-MOSFETs with ultra-thin gate oxides in the direct-tunneling regime”, in IEDM Tech. Dig., pp.453-456, 1997.

[31] H. Hazama, M. Iwase, and S. Takagi, “Hot-carrier reliability in deep submicrometer MOSFETs”, in IEDM Tech. Dig., pp.569-572, 1990.

[32] J.S. Brugler, and P.G.A. Jespers, “Charge Pumping in MOS Devices”, IEEE Trans.

on Electron Devices, vol. 16, pp. 297-302, March 1969.

[33] P. Heremans, J. Witters, G. Groeseneken,and H. E. Maes, “Analysis of the charge pumping technique and its application for the evaluation of the MOSFET Degradation”, IEEE Tran. Electron Devices, Vol. 36, No. 7, pp. 1318-1335, 1989.

[34] G. Groeseneken, H. E. Maes, N. Beltran, and R. F. De Kecrsmaecker, “A reliable approach to charge-pumping measurements in MOS transistors”, IEEE Trans.

Electron Devices, Vol. ED-31, pp. 42-53, 1984.

[35] C. Chen, and T. P. Ma, “Direct lateral profiling of hot-carrier-induced oxide charge and interface traps in thin gate MOSFET’s”, IEEE Electron Devices, vol.45, pp.512-520, February 1998.

[36] M. Tsuchiaki, H. Hara, T. Morimoto, and H. Iwai, “A new charge pumping method for determining the spatial distribution of hot-carrier induced fixed charge in p-MOSFET’s”, IEEE Trans. Electron Devices, vol. 40, pp. 1768–1778, October 1993.

[37] S.M.Sze, Physics of Semiconductor Devices, 2ndEdition, pp. 69, July 1985.

Murthy, J. Sandford, R. Shaheed, K. Zawadzki, K. Zhang, S. Thompson, M. Bohr,

“Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology”, VLSI Symp. Tech. Dig., pp. 50-51, June 2004.

[39] W. B. Jackson, N. WI. Johnson, C. C. Tsai, L-W. Wu, A. Chiang, and D. Smith,

“Hydrogen diffusion in polycrystalline silicon thin films”, American Institute of Physics, pp. 1670-1672, October 1992.

[40] H. I. Hanafi, W. P. Noble, R. S. Bass, K. Varahramyan, Y. Lii, and A. J. Dally, “A model for anomalous short-channel behavior in submicron MOSFETs”, IEEE Electron Device Lett., vol. 14, pp. 575-577, Decmber 1993.

[41] J.-S. Lim, S.E. Thompson, J.G. Fossum, “Comparison of threshold voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs”, IEEE Electron Device Letters, vol. 25, pp. 731-733, November 2004.

[42] S. T. Dunham, M. Diebel, C. Ahn, and C. L. Shih, “Calculations of effect of anisotropic stress/strain on dopant diffusion in silicon under equilibrium and nonequilibrium conditions”, American Vacuum Society, pp.456-461, January 2006.

[43] L. Lin, T. Kirichenko, B. R. Sahu, G. S. Hwang, and S. K. Banerjee, “Theoretical study of B diffusion with charged defects in strained Si”, The American Physical Society, 2005

[44] M. F. Lu, S. Chiang, A. Liu, S. H. Lu, M. S. Yeh, J. R. Hwang, T.H. Tang, W.T.

Shiau, M. C. Chen and T. Wang, “Hot carrier degradation in novel strained-Si nMOSFETs”, in Proc. Int. Reliability Physics Symp., pp. 18-22, 2004.

[45] N. Sano, M. Tomizawa, and A. Yoshii, “Temperature dependence of hot carrier effects in short-channel Si-MOSFETs”, IEEE Trans. on Electron Devices, vol. 42, pp. 2211-2216. December 1995.

Gate

Buffer

Layer CESL PassivationLayer Index

w/o w/o REF

Table 2.1 Split table of buffer layer and CESL.

Fig. 1.1 Gate length scaling as a function of the year of introduction for technology node [1].

CMOS Performance Impact Direction of

Strain Change* NMOS PMOS

X Improve Degrade

Y Improve Improve

Z Degrade Improve

* Strain change = Increased tensile or decreased compressive strain

Drain

Gate

E

Source

Gate Silicide

Process-induced Strain

Fig. 1.3 Splitting of light hole band and heavy hole band with biaxial and uniaxial strains in low electric field (solid line) and high electric field (dash line) [22].

LH HH

ΔELH-EHH

Biaxial Strain Uniaxial Strain

Gate

P-substrate

Source Drain

TEOS TEOS

Buffer Layer Buffer Layer

Gate

P-substrate

Source Drain

TEOS TEOS

Buffer Layer Buffer Layer

Fig. 2.1 Schematic cross section of the locally-strained-channel NMOSFT.

Fig. 2.2 Setup structure for charge pumping measurement.

Fig. 2.3 Measurement setup of single-junction charge pumping measurement.

Floating Icp

n

⁺

Drain n

⁺

Source

n

⁺

Gate

Fixed base mode V

base

=-0.1V, V

=-0.8V ~ 1V V

base

V

p

⁺

Substrate

Fig. 3.1 Capacitance-Voltage(C-V) characteristics of NMOSFETs processed with different thermal budgets. Channel width/channel length = 50μm/50μm.

Gate Voltage(V)

-2 -1 0 1 2

Capacitance(pF)

5 10 15 20 25 30

Placebo (Thermal Budget) REF (W/O Thermal Budget)

Fig. 3.2 Solid solubility of various elements in Si as a function of temperature [37].

Fig. 3.3 Capacitance-Voltage(C-V) characteristics of different splits of NMOSFETs.

Channel width/channel length = 50μm/50μm.

Gate Voltage(V)

-2 -1 0 1 2

Capacitance(pF)

5 10 15 20 25 30

Placebo (Thermal Budget) SiN

TEOS/SiN POLY/SiN

Fig. 3.4 Cumulative probability distribution of poly-gate sheet resistance for all splits of samples. The film thickness is 150nm. Doping was done by As-ion implantation at a dose of 3x10¹⁵ cm^-2 and an energy of 10KeV. All samples received an RTA at 900℃ for 30sec. Note that the REF split skips the thermal treatment associated with the SiN deposition.

Sheet Resistance (Ω/sq)

1000 1200 1400 1600 1800 2000

Cumulative Probability (%) ¹

10 30 50 70 90 99

Placebo (Thermal Budget) REF (W/O Thermal Budget) SiN

TEOS/SiN POLY/SiN

Fig. 3.5 Subthreshold and transconductance characteristics of different splits of NMOSFETs characterized at 25℃. Channel width/channel length = 10μm/0.5μm.

Gate Voltage(V)

Pla ceb o

Subthreshold Swing(mV/dec) ⁷⁰

72 74 76 78 80

SiN

TE OS /Si N

PO LY /Si N

Fig. 3.6 Subthreshold swing for different splits of NMOSFETs. Channel width/channel length = 10μm/0.5μm.

W/L=10µm/0.5µm

Drain Voltage(V)

0.0 0.5 1.0 1.5 2.0

Drain Current(mA)

0 1 2 3 4 5 6

Placebo SiN TEOS/SiN POLY/SiN VG-V

th=0.4~2V, Step=0.8V

Fig. 3.7 Output characteristics of NMOSFETs for different splits, measured at 25℃.

Channel width/channel length = 10μm/0.5μm.

Fig. 3.8 Transconductance enhancement for different splits as a function of channel length, measured at 25°C.

Gate Length(µm)

1 10

∆ G m,max /G m,ma x,co ntro l(%)

0 10 20 30 40

SiN

TEOS/SiN

POLY/SiN

Fig. 3.9 Drain current enhancement for different splits as a function of channel length, measured at 25°C. The saturation current was measured at VG-Vth = 2V and VDS = 2V.

Gate Length(µm)

1 10

∆ I D

,sat /I D ,sat,control (%)

0 5 10 15 20

SiN TEOS/SiN POLY/SiN

ID,sat at VG - Vth = 2V and VDS = 2V

Fig. 3.10 Charge pumping current for the placebo, REF, and SiN splits. Channel width/channel length = 10µm/0.5µm.

Base Voltage

-2.0 -1.5 -1.0 -0.5

Charge P u mping Current(nA)

0.0 0.1 0.2

0.3 Placebo (Thermal Budget)

REF (W/O Thermal Budget) SiN

W/L=10µm/0.5µm

Fig. 3.11 Charge pumping current for different splits of NMOSFETs. Channel width/channel length = 10μm/0.5μm.

Base Voltage

-2.0 -1.5 -1.0 -0.5

Charge P u mping Current(nA)

0.0 0.1 0.2

0.3

^Control

SiN TEOS/SiN POLY/SiN

W/L=10µm/0.5µm

Placebo

Fig. 3.12 Threshold voltage roll-off as a function of channel length for the placebo and REF splits.

Gate Length(µm)

1 10

∆ V th (mV)

-80 -60 -40 -20 0 20 40 60

Placebo (Thermal Budget)

REF (W/O Thermal Budget)

Fig. 3.13 Threshold voltage roll-off as a function of channel length for all splits.

Gate Length(µm)

1 10

∆ V th (mV)

-80 -60 -40 -20 0 20 40 60

Control

SiN

TEOS/SiN

POLY/SiN

Placebo

Fig. 3.14 Drain induced barrier lowing (DIBL) for different splits of NMOSFETs as a function of channel length. DIBL was evaluated by measuring the drain current change as VDS was increased at some fixed gated voltage below threshold voltage.

Gate Length(µm)

1 10

DIBL(mV/V)

0 10 20 30 40 50

Control SiN

TEOS/SiN

POLY/SiN

Placebo

Fig. 3.15 Substrate current versus gate voltage for different splits of NMOSFETs.

Channel width/channel length = 10μm/0.5μm.

Gate voltage(V)

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Substrate Current(mA)

0.0 0.1 0.2 0.3 0.4

Control SiN TEOS/SiN POLY/SiN

W/L=10µm/0.5µm VDS=4.6V

Placebo

Fig. 3.16 Threshold voltage shift after hot-electron stressing performed at VDS=4.9V and VGS at maximum substrate current for all splits of devices with channel width/channel length = 10μm/0.5μm.

Stress Time(sec)

0 1000 2000 3000 4000 5000

∆ Vth(mV)

-50 0 50 100 150 200

Control SiN

TEOS/SiN POLY/SiN

VDS=4.6V , VG@Isub,max W/L=10µm/0.5µm

Placebo

Fig. 3.17 Interface trap density generation measured after hot-electron stressing performed at VDS=4.9V and VGS at maximum substrate current for all splits of devices with channel width/channel length = 10μm/0.5μm.

Stress Time(sec)

0 1000 2000 3000 4000 5000

∆ Nit(10 10 /cm 2 )

0 10 20 30 40

50

Control

SiN TEOS/SiN POLY/SiN

VDS=4.6V , VG@Isub,max W/L=10µm/0.5µm

Placebo

10 years

Fig. 3.18 10-year lifetime projection for the placebo, SiN, TEOS/SiN, and POLY/SiN samples.

(a)

(b)

Fig. 3.19 Subthreshold characteristics and transconductance of devices before and after 5000 sec hot-electron stressing. Channel width/channel length = 10μm/0.5μm. (a) Placebo sample. (b) SiN sample.

Control

(a)

(b)

Fig. 3.20 Subthreshold characteristics and transconductance of devices before and after 5000 sec hot-electron stressing. Channel width/channel length = 10μm/0.5μm. (a) TEOS/SiN sample. (b) Poly/SiN sample.

TEOS/SiN

Fig. 3.21 Variation of local threshold voltage and flat-band voltage across the device channel caused by the variation of lateral doping concentration.

V_th

Vfb

V_h

V_base x

Gate

Fig. 3.22 Derivation of the relationship between local threshold voltage and lateral distance x from the single-junction charge pumping data of the Placebo device.

Peak Voltage (Vh) (V)

-0.5 0.0 0.5 1.0

Icp (pA )

0 20 40 60 80

x (µ m )

0.0 0.1 0.2 0.3 0.4 W/L=10 µm/0.5µm Icp,max 0.5

Vth(x)

Fig. 3.23 Extracted lateral profile of local threshold voltage near the graded drain junction in the placebo sample.

x (µm)

0.00 0.05 0.10 0.15 0.20 0.25 0.30

Local Threshold Voltage (V)

-0.4 -0.2 0.0 0.2 0.4

W/L=10 µm/0.5µm

Fig. 3.24 Charge pumping current before and after 100 second hot-electron stressing (VG@Isubmax and VDS=4.9V). Channel width/channel length = 10μm/0.5μm.

∆Icp

Peak Voltage (Vh) (V)

-0.8 -0.4 0.0 0.4 0.8

Charge pumping Current Icp (pA) ⁰

100 200 300 400

500 Fresh

Stressed

Fig. 3.25 Lateral profile of interface state generation under different split conditions.

W/L=10µm/0.5µm

x ( µm)

0.00 0.05 0.10 0.15 0.20 0.25 0.30

Nit(x) (10 10 cm -2 )

0 20 40 60 80 100 120 140

Control SiN TEOS/SiN POLY/SiN

Center Drain edge

Placebo

簡歷

姓名 : 黃健銘

性別 : 男

生日 : 70.11.23

出生地 : 台北市

籍貫 : 台灣省台北縣

地址 : 台北縣板橋市大勇街 12 巷 3 號 4 樓

學歷 :

台北市立松山高中 1997.09~2000.06

國立成功大學電機工程學系 2000.09~2004.06

國立交通大學電子研究所 2004.09~2006.06

論文題目: 一個用來改善形變通道 N 型金氧半場效電晶體熱載子可靠度的方法

A Novel Approach to Improve Hot Carrier Reliability of Strained-Channel NMOSFETs

在文檔中一個用來改善形變通道N型金氧半場效電晶體 (頁 39-82)

Analysis of the Lateral Distribution of Interface Trap Density 24

Chapter 3 Experimental Results ans Discussion

3.3 Analysis of the Lateral Distribution of Interface Trap Density 24

( )

Chapter 4

Summary and Conclusion

4.1 Summary and Conclusion

Reference:

CMOS Performance Impact Direction of

Strain Change* NMOS PMOS

X Improve Degrade

Y Improve Improve

Z Degrade Improve

Drain

Gate

E

E

E

Source

Gate Silicide

Process-induced Strain

Biaxial Strain Uniaxial Strain

Gate

P-substrate

Source Drain

TEOS TEOS

Gate

P-substrate

Source Drain

TEOS TEOS

Floating Icp

n

Drain n

Source

n

Gate

Fixed base mode V

=-0.1V, V

=-0.8V ~ 1V V

V

p

Substrate

Gate Voltage(V)

-2 -1 0 1 2

Capacitance(pF)

5 10 15 20 25 30

Gate Voltage(V)

-2 -1 0 1 2

Capacitance(pF)

5 10 15 20 25 30

Sheet Resistance (Ω/sq)

1000 1200 1400 1600 1800 2000

Cumulative Probability (%) 1

10 30 50 70 90 99

Gate Voltage(V)

Pla ceb o

Subthreshold Swing(mV/dec) 70

72 74 76 78 80

SiN

TE OS /Si N

PO LY /Si N

W/L=10µm/0.5µm

Drain Voltage(V)

0.0 0.5 1.0 1.5 2.0

Drain Current(mA)

0 1 2 3 4 5 6

Gate Length(µm)

1 10

∆ G m,max /G m,ma x,co ntro l(%)

0 10 20 30 40

SiN

TEOS/SiN

POLY/SiN

Gate Length(µm)

1 10

∆ I D

,sat /I D ,sat,control (%)

0 5 10 15 20

SiN TEOS/SiN POLY/SiN

ID,sat at VG - Vth = 2V and VDS = 2V

Cumulative Probability (%) ¹

Subthreshold Swing(mV/dec) ⁷⁰