Chapter 1 Introduction
1.3 Organization of the Thesis
In the following sections, we will show our research efforts.
In Chapter 2, the electrical characteristics and fabrication processes of low temperature poly-Si TFTs with silicon nitride capping layer will be proposed.
Experimental results reveal that the performance and reliability of our devices have remarkable improvements in comparison with conventional TFTs. Additionally, we
make a detail discussion to explain the results of experimental.
In Chapter 3, the fabrication processes and electrical characteristics of p-channel ploy-Si TFTs with different stripes of channel will be proposed. Experimental results reveal that poly-Si TFTs with multiple channels have better performance and reliability than the conventional TFTs. Then, we will make a complete discussion about the electrical characteristics and reliability issue of poly-Si TFTs with multiple channels.
In Chapter 4, the reliability issue of poly-Si TFTs with different channel geometry will be investigated by applying different drain bias. It is found that Ion degradation under both high and low drain bias of stress conditions has different phenomenon. Then, we will analyze the degradation mechanism under hot carrier stress with wide drain voltage bias for the devices with different channel geometry.
At the end of this thesis, we will make a conclusion in Chapter 5.
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Chapter 2
Performance Enhancement of Low Temperature Polysilicon Thin Film Transistor with Silicon Nitride
Capping layer
2.1 Introduction
In recent years, flexible electronics have been investigated and were paid attention, such as electronic paper, flexible display, sensor skin and electrotextiles. It required building electron device on flexible and deformable substrate [1]-[4].
Therefore, device will be stressed when operating flexible electronics. In this condition, mechanical strain is a major force to stress device.
There are many researches to comprehend effect of mechanical strain in device.
In previous reported, they measured device characteristic when device under mechanical strain. it was found that tensile strain improves the electron mobility and the drain current of n-channel device including MOSFETs and TFTs [5][6]. On the contrary, Compressive strain reduced the electron mobility.
Recently, the strain-Si MOSFETs have become attractive for high speed complementary-metal-oxide-semiconductor (CMOS) device applications [7][8].the improvement of carrier mobility has been intensely studied by introducing strain in the channel region, such as strained-Si on SiGe substrate. However, the fabrication of the strained-Si devices is more complicated, such as forming a relaxed SiGe buffer layer. Previously studied indicated that uniaxial strained channel from contact etch stop silicon nitride (SiN) layer increase current drivability[9][10]. Because silicon
nitride layer has tensile strain and further forming compressively strained polysilicon gate electrode and then give a tensile stress on the channel.
In this chapter, we fabricated poly-Si TFTs with capping silicon nitride layer to created a tensile stress on the channel. It was found that this device have better electrical characteristic than convention poly-Si TFTs. We enhanced electron mobility and on current due to local tensile strain and low source/drain series resistance and then suppressed kink effect, gate induced drain leakage(GIDL) effect and improved reliability due to low horizontal electric field in Capping Nitride poly-Si TFTs. We will make a detail discussion in later section.
2.2 Device Fabrication
Figure 2-1 show the process flow and cross-sectional view of the investigated poly-Si TFT. First, 500-nm-thick thermal oxide was grown on the Si wafer by using a furnace system. All the experimental devices in this study were fabricated on thermally oxidized Si wafers. Then, 50-nm-thick amorphous silicon layers were deposited on the thermal oxide layer using a low-pressure chemical vapor deposition (LPCVD) system at 550°C. Then, amorphous silicon films were recrystallized by solid phase crystallization (SPC) method at 600°C for 24 hours in an N2 ambient to form poly-Si films. Poly-Si films were patterned into active regions by transformer couple plasma (TCP) etching system using mixture gases of Cl2 and HBr.
After RCA cleaning procedure, a 50-nm-thick TEOS oxide was deposited by LPCVD with TEOS and O2 gases at 695°C to form the gate insulator. A 150-nm-thick poly-Si was deposited to serve as the gate electrode by LPCVD at 595°C. Then, the poly-Si film was patterned and etched by TCP etching system to form the gate electrode and the gate oxide on source/drain was removed using dilute HF solution.
The regions of source, drain, and gate were doped by a self-aligned phosphorous ion
implantation at the dosage and energy of 5×1015ions/cm-2 and 20keV, respectively.
The dopant activation was performed by furnace system at 600°C for 12 hours, followed by a deposition of 250nm-thick silicon nitride layer and 300nm-thick passivation oxide using PECVD system at 350°C and the definition of contact holes.
Then, weetched passivation oxide by BOE solution. After removed passivation oxide, 90% silicon nitride layer was etched by dry etching system and utilized oxide layer as a hard mask for etching 10% silicon nitride layer by wet etch in H3PO4 solution.
Finally, a 800-nm-thick Al was deposited by sputter and patterned for metal pads, and devices were passivated by NH3 plasma treatment for 30 minute at 300°C. For comparison, the control samples have no capping nitride layer. It only deposited passivaton oxide using PECVD system at 350°C.
2.3 Method of Device Parameter Extraction
In this thesis, we use Ellipsometer to measure the thickness of poly-Si, amorphous-Si and TEOS oxide films in the fabrication procedure. All the electrical characteristics of proposed poly-Si TFTs were measured by HP 4156B-Precision Semiconductor Parameter Analyzer.
Many methods have been proposed to extract the characteristic parameters of poly-Si TFTs. In this section, those methods are described.
2.3.1
Determination of Threshold VoltageThreshold voltage (Vth) is an important parameter required for the channel length-width and series resistance measurements. However, Vth is not uniquely defined. Various definitions have been proposed and the reason can be found in ID-VGS curves. One of the most common techniques is the linear extrapolation method with the drain current measured as a function of gate voltage at a low drain voltage of
50~100mV to ensure operation in the linear region [17]. The drain current is not zero when VGS below threshold voltage and approaches zero asymptotically. Hence the IDS
versus VGS curve can be extrapolated to ID=0, and the Vth is determined from the extrapolated intercept of gate voltage (VGS) by
2
Equation (2.1) is strictly only valid for negligible series resistance. Fortunately series resistance is usually negligible at the low drain current when threshold voltage measurements are made. The IDS-VGS curve deviates from a straight line at gate voltage below Vth due to subthreshold current and above Vth due to series resistance and mobility degradation effects. It is common practice to find the point of maximum slope of the IDS-VGS curve and fit a straight line to extrapolate to ID=0 by means of finding the point of maximum of transconductance (Gm).
In this thesis, we use a simpler method to determinate the Vth called constant drain current method. The voltage at a specified threshold drain current is taken as the Vth. This method is adopted in the most studied papers of poly-Si TFTs. It can be given a threshold voltage close to that obtained by the complex linear extrapolation method. Typically, the threshold current is specified at (W/L)×10nA for VDS=0.1V and (W/L)×100nA for VDS=5V, where W and L are channel width and channel length, respectively.
2.3.2
Determination of Subthreshold-SwingSubthreshold swing (S.S.) is a typical parameter to describe the control ability of gate toward channel, which reflects the turn on/off speed of a device. It is defined as the amount of gate voltage required to increase/decrease drain current by one order of magnitude.
The S.S. should be independent of drain voltage and gate voltage. However, in reality, the S.S. increases with drain voltage due to channel shortening effect such as charge sharing, avalanche multiplication and punchthrough effect. The subthreshold swing is also related to gate voltage due to undesirable and inevitable factors such as the serial resistance and interface states.
In this thesis, the S.S. is defined as one-third of the gate voltage required to decrease the threshold current by three orders of magnitude. The threshold current is specified to be the drain current when the gate voltage is equal to threshold voltage.
2.3.3
Determination of Field Effect MobilityUsually, field effect mobility (µeff) is determined from the maximum value of transconductance (Gm) at low drain bias. The transfer characteristics of poly-Si TFTs are similar to those of conventional MOSFETs, so that the first order of I-V relation in the bulk Si MOSFETs can be applied to poly-Si TFTs. The drain current in linear region (VDS＜VGS－Vth) can be approximated as the following equation:
( )
2.3.4
Determination of ON/OFF Current RatioOn/off current ratio is one of the most important parameters of poly-Si TFTs since a high-performance device exhibits not only a large on-current but also a small off-current (leakage current). The leakage current mechanism in poly-Si TFTs is not like that in MOSFET. In MOSFET, the channel is composed of single crystalline Si and the leakage current is due to the tunneling of minority carrier from drain region to accumulation layer located in channel region. However, in poly-Si TFTs, the channel is composed of poly-Si. A large amount of trap state densities in grain structure attribute a lot of defect states in energy band gap to enhance the tunneling effect.
Therefore, the leakage current is much larger in poly-Si TFTs than in MOSFET. When the voltage drops between gate voltage and drain voltage increases, the band gap specified as the minimum current when drain voltage equals to 5V.
V
2.3.5
Extraction of Grain Boundary Trap State DensityThe Trap State Density (Nt), which can be determined by the theory established by Levinson et al. [18], which is based on Seto’s theory [19].
For poly-Si TFTs, the drain current IDS can be given as following:
equation with an activated mobility, which depends on the grain-boundary barrier height. Levinson et al. assumed that the channel thickness was constant and equal to induced carrier channel thickness by solving Poisson’s equation for an undoped material and to define the channel thickness (Lc) as a thickness in which 80% of the total charges were induced by the gate. Doing so, one obtains
which varies inversely with (VGS−Vfb). This predicts, by substituting Eq.2.7 into Eq.2.6, that ln[IDS/(VGS−Vfb)] versus 1/(VGS−Vfb)2. We use the gate voltage at which minimum leakage current occurs as flat-band voltage (Vfb). Effective trap-state density (Nt) can be determined from the square root of the slope.
2.4 Results and Discussion
2.4.1 Characteristics of poly-Si TFTs with capping silicon nitride layer
We measured device characteristics while we have done the device fabrication.
Fig. 2-2 shows the transfer characteristics (IDS-VGS) for the control and Capping Nitride poly-Si TFTs. The measurements was performed at drain voltage of VDS=5V.
The measured and extracted parameters from the devices are listed in table 2-1. the threshold voltage, subthreshold swing, on-current (VGS=20V), and off-current (VGS=-10V) were measured at VDS=5V.
In the Fig.2-2, we can see that the Capping Nitride poly-Si TFTs exhibit better on-state characteristics than the control sample. In off-state, under a large negative gate bias, the leakage currents of the Capping Nitride poly-Si TFTs (1.71*10-10) are significant lower than the control poly-Si TFTs (1.61*10-9). It was quite obvious that gate induce drain leakage (GIDL) was suppressed in Capping Nitride poly-Si TFTs.
Moreover, the threshold voltage and subthreshold swing of the Capping Nitride poly-Si TFTs (0.16V & 0.98V/dec.) was found to be superior to the control sample (0.67V & 1.25V/dec.). Fig. 2-3, we compared the field effect mobility between those two samples, the proposed TFTs shows large enhancement of mobility compared with conventional TFTs. They were found to be 23(cm2/V.s) and 32.5(cm2/V.s) for the control and Capping Nitride poly-Si TFTs, respectively. The mobility of Capping Nitride poly-Si TFTs has greatly enhancement by 41.3%. This is due to capping nitride layer has tensile strain and further forming compressively
Moreover, the threshold voltage and subthreshold swing of the Capping Nitride poly-Si TFTs (0.16V & 0.98V/dec.) was found to be superior to the control sample (0.67V & 1.25V/dec.). Fig. 2-3, we compared the field effect mobility between those two samples, the proposed TFTs shows large enhancement of mobility compared with conventional TFTs. They were found to be 23(cm2/V.s) and 32.5(cm2/V.s) for the control and Capping Nitride poly-Si TFTs, respectively. The mobility of Capping Nitride poly-Si TFTs has greatly enhancement by 41.3%. This is due to capping nitride layer has tensile strain and further forming compressively