Summary

We fabricated high performance TFTs with capping silicon nitride layer. The characteristic of proposed TFTs have great improvement, such as higher on-current, higher mobility, lower subthreshold swing, suppressing kink effect and GIDL effect and good reliability. The process of proposed TFTs is uncomplicated and no need of extra mask step. We believe that the proposed TFTs will be candidate in high performance TFTs application.

Reference:

[1] Y. Chen, J. Au, P. Kazlas, A. Ritenour,H. Gates, and J. Goodman, “Ultrathin, high-resolution, flexible electronic ink displays addressed by a-Si active-matrix TFT backplanes on stainless steel foil,” in IEDM Tech. Dig., 2002, pp. 389–392.

[2] M. G. Kane, J. Campi, M. S. Hammond, F. P. Cuomo, B. Greening, C. D. Sheraw, J. A. Nichols, D. J. Gundlach, J. R. Huang, C. C. Kuo, L. Jia, H. Klauk, and T. N.

Jackson, “Analog and digital circuits using organic thin-film transistors on polyester substrates,” IEEE Electron Device Lett., vol. 21, pp. 534–536, Nov.

2000.

[3] J. Engel, J. Chen, C. Liu, B. R. Flachsbart, J. C. Selby, and M. A. Shannon,

“Development of polyimide-based flexible tactile sensing skin,” in Proc. Mat. Res.

Soc. Symp., vol. 736, 2003, pp. D.4.5.1–D4.5.6.

[4] H. Gleskova, S. Wagner, W. Soboyejo, and Z. Suo, “Electrical response of amorphous silicon thin-film transistors under mechanical strain,” J. Appl. Phys.^, vol. 92, pp. 6224–6229, 2002.

[5] S. Maikap, C.-Y. Yu, S.-R. Jan, M. H. Lee, and C. W. Liu, “Mechanically Strained Strained-Si NMOSFETs,” IEEE Electron Device Lett., vol. 25, no. 1 pp.

40–42, 2004.

[6] Pai-hui Iris Hsu , M. Huang, H. Gleskova, Z. Xi, Z. Suo, S. Wagner, and James C.

Sturm, “Effects of Mechanical Strain on TFTs on Spherical Domes” IEEE Trans.

Electron Devices, vol. 51, no. 3, pp. 371-377, 2004

[7] J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald, and D. A. Antoniadis, “Strained Si MOSFET technology,” in IEDM Tech. Dig.^, 2002, p. 23.

[8] K. Rim, S. Narasimha, M. Longstreet, A. Mocuta, and J. Cai, “Low field mobility characteristics of sub-100 nm unstrained and strained Si MOSFETs,” in IEDM Tech. Dig., 2002, pp. 43–46.

[9] C. H. Chen, T. L. Lee, T. H. Hou, C. L. Chen, C. C. Chen, J.W. Hsu, K. L. Cheng, Y. H. Chiu, H. J. Tao, Y. Jin, C. H. Diaz, S. C. Chen, and M. S. Liiang, “Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65 nm high-performance strained-Si device application,” in Symp. VLSI Tech. Dig.^, 2004, pp. 56–57.

[10] S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. A. S. Koyama, S. Kuroki, N.

Ikezawa, T. Saitoh, and T. Horiuchi, “Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design,” in IEDM Tech. Dig.^, 2000, pp. 247–250.

[11] Tsung Yi Lu and Tien Sheng Chao, “Mobility Enhancement in Local Strain Channel nMOSFETs by Stacked a-Si/Poly-Si Gate and Capping Nitride,” IEEE Electron Device Lett., vol. 26, no. 4 pp. 267–269, 2005.

[12] Zhibin Xiong, Haitao Liu, Chunxiang Zhu and Johnny K. O. Sin,

“Characteristics of High-k Spacer Offset-Gated Polysilicon TFTs,” IEEE Trans.

Electron Devices, vol. 51, no. 8, pp. 1304-1308, 2004

(a) Thermal oxidation grown by furnace

(b) Amorphous Si (a-Si) deposited by LPCVD

(c) Recrystallization of a-Si film into poly-Si channel by SPC, active region defined

Si Wafer Thermal Oxide Poly-Si Channel

Si Wafer Thermal Oxide

a-Si

Si Wafer

Thermal Oxide

(d) Deposition of TEOS gate oxide by LPCVD and poly-Si gate by LPCVD

(e) The gate electrode defined and self-align phosphorous ion implantation

Si Wafer Thermal Oxide Poly-Si Channel

Phosphorous self-aligned ion implantation Si Wafer

Thermal Oxide Poly-Si Channel TEOS Gate Oxide

Poly-Si Gate

(f) Dopant activation by excimer laser annealing

(g) Deposition of silicon nitride layer and passivation oxide by PECVD

Si Wafer Thermal Oxide

Poly-Si n

⁺

n

⁺

n

⁺

Si Wafer Thermal Oxide

Poly-Si n

⁺

n

⁺

n

⁺

(h) Contact holes opened and metal pads formation

Fig 2-1 Schematic diagram of fabrication process for Capping Nitride poly-Si TFTs

Si-Wafer Thermal Oxide

Poly-Si n

⁺

n

⁺

n

⁺

Table 2.1 Comparison of device characteristics of the Control and Capping Nitride poly-Si TFTs.

Poly-Si TFTs Control Capping Nitride

V

th

(V) 0.67 0.16

S.S (V/dec.) 1.25 0.98

µ

Eff

(cm

²

/V.s) 23 32.5

I

_on

@ VG=20V 1.08*10

^-4

1.60*10

^-4

I

off

@ VG=-10V 1.61*10

^-9

1.71*10

^-10

Rs ( Ω) 5.83*10

³

1.92*10

³

N

t

(cm

^-2

) 8.32*10

¹²

3.89*10

¹²

10^-12 10^-10 10^-8 10^-6 10^-4

-10 -5 0 5 10 15 20

Control

Capping SiNx

D ra in C ur re nt (A )

Gate Voltage (V)

W/L = 10µµµµm/10µµµµm

V_D = 5V

Fig. 2-2 Transfer characteristics of the Control and Capping Nitride poly-Si TFTs with V_DS=5V

-5 0 5 10 15 20 25 30 35

-10 -5 0 5 10 15 20

Control

Capping SiNx

Fi eld Ef fe ct M ob ili ty , µµµµ

eff

(c m

2

/v .s ec )

Gate Voltage, V

_G

(V)

W/L = 10µµµµm/10µµµµm

Oxide thickness = 50nm V_DS=0.1V

Fig. 2-3 Field-effect mobility of the Control and Capping Nitride poly-Si TFTs with V_DS=0.1V

-20 -19 -18 -17 -16 -15

0 0.002 0.004 0.006 0.008 0.01 0.012

Control

Capping SiNx

ln [I

DS

/(V

GS

-V

FB

)] (ΩΩΩΩ

-1

)

1/(V

_GS

-V

_FB

)

²

(V

^-2

)

Nt=8.32*10¹² cm^-2

Nt=3.89*10¹² cm^-2

Fig. 2-4 Trap state density extraction of the Control and the Capping Nitride poly-Si TFTs

0

Fig. 2-6 Mechanism of reduction of source/drain series resistance

Positive Gate voltage

Source Drain

Electrons

Silicon Nitride

0 1 10^-5 2 10^-5 3 10^-5 4 10^-5 5 10^-5 6 10^-5 7 10^-5

0 5 10 15

Control

Capping SiNx

D ra in C ur re nt (A )

Drain Voltage (V)

W/L = 10µµµµm/5µµµµm

Fig. 2-7 Output characteristic of the Control and the Capping Nitride poly-Si TFTs

0

(a) On-current degradation with stress time

0

(b) Threshold voltage degradation with stress time

Fig. 2-8 (a) on-current and (b) threshold voltage degradation as a function of stress time under hot-carrier stress

Chapter 3

Characteristic and Reliability of P-Channel Poly-Si TFTs with Multi-Channel Structure

3.1 Introduction

P-channel poly-Si TFTs have been used for many applications, such as low-power SRAMs [1], High-Resolution Active Matrix [2] and EEPROM’s [3]. In circuit design, CMOS technique is a very important technique. Because it have many advantage such as low power consumption, fully restored logic and better reliability.

We would like realized CMOS technique by using TFTs device. So P-Channel and N-Channel TFTs are needed for integrated CMOS circuit. We believed that Poly-Si TFTs technology is the most promising candidate for the ultimate goal of building fully integrated flat panel display system-on-glass. Moreover, the stability of p-channel polysilicon TFTs has not been investigated as much as n-channel polysilicon TFTs. So, we discussed characteristic and reliability of P-Channel poly-Si TFTs in this chapter.

It is well know that the characteristics of poly-Si TFTs are dominated by the large trap density in poly-Si film. When channel width scaled down, devices are reported to exhibit better performance such as lower threshold voltage and smaller trap density [4]-[6]. As a result, Poly-Si TFTs with narrow and multiple channels have been proposed to improve device performance [7][8]. Previous reports indicated that the existence regions near the poly-Si pattern edge where the grain boundary trap density is much smaller than elsewhere in the poly-Si film [4]. When channel width

decreasing the effect of poly-Si pattern edge dominates and causes an effective trap density decreasing. Moreover, Due to the formation of active region island the gate electrode layer that climbs across the channel may induce side channels in both sides of the channel region. When channel width scaled down these side-channels become comparable to the main channel, accordingly increasing the effective channel width.

Additionally, in CMOS technology, tri-gate [9] structure has been reported to exhibit superior gate control over the channel than a conventional single-gate MOSFET. Thus, we incorporate multi-channel with different channel widths, and tri-gate structure to achieve the high-performance and high reliability poly-Si TFTs.

Previous reports have demonstrated that n-channel poly-Si TFTs with multi-channel structure can improve device performance [10] and also discussed reliability of n-channel poly-Si TFTs with multi-channel structure. In this chapter, we fabricated p-channel poly-Si TFTs with multi-channel structure. We will analyze and discuss both characteristic and reliability of the proposed poly-Si TFTs in this chapter.

3.2 Experiment

Figure 3-1 shows the process flow of the proposed poly-Si TFTs. First, 500-nm-thick thermal oxide was grown on the Si wafer by using a furnace system. All the experimental devices in this study were fabricated on thermally oxidized Si wafers.

Then, 100-nm-thick amorphous silicon layers were deposited on the thermal oxide layer using a low-pressure chemical vapor deposition (LPCVD) system at 550°C.

Then, amorphous silicon films were recrystallized by solid phase crystallization (SPC) method at 600°C for 24 hours in an N₂ ambient to form poly-Si films. Poly-Si films were patterned into active regions by transformer couple plasma (TCP) etching system using mixture gases of Cl₂ and HBr.

After RCA cleaning procedure, a 50-nm-thick TEOS oxide was deposited by

LPCVD with TEOS and O₂ gases at 695°C to form the gate insulator. A 150-nm-thick poly-Si was deposited to serve as the gate electrode by LPCVD at 595°C. Then, the poly-Si film was patterned and etched by TCP etching system to form the gate electrode and the gate oxide on source/drain was removed using dilute HF solution.

The regions of source, drain, and gate were doped by a self-aligned BF₂ ion implantation at the dosage and energy of 5×10¹⁵ions/cm^-2 and 40keV, respectively.

The dopant activation was performed by furnace system at 600°C for 8 hours, followed by a deposition of 400nm-thick passivation oxide using PECVD system at 350°C and the definition of contact holes. Finally, a 500-nm-thick Al was deposited by sputter and patterned for metal pads, and devices were passivated by NH3 plasma treatment for 30 minutes at 300°C.

Figure 3-2 presents the cross-section of the conventional and multi-channel poly-Si TFTs, which is parallel to the direction of the source and drain electrode.

Figure 3-3 depicts the cross-section perpendicular to the direction of the source and drain electrode. In next section, we will discuss the transfer characteristics of the conventional and proposed TFTs with single,4, 8, 20, and 40 stripes of the same total channel width. The top view of proposed TFTs with different channel strips as shown in Fig. 3-4. The detailed data of these structures were summarized in Table 3-1.

3.3 Results and Discussion

3.3.1 Characteristics of P-Channel Poly-Si TFTs with Multiple Channels

Figure 3-5 shows the transfer characteristics (I_DS-V_GS) for the conventional and proposed TFTs with different stripes of channel. Table 3-2 summarizes the measured and extracted parameters from the devices. The threshold voltage, subthreshold swing, on-state current (VGS=-25V) and the off-state current (VGS=0V) were measured at

V_DS=-5V. It is obvious that the electrical characteristics of the poly-Si TFTs with multiple channels are significantly improved. In this figure, we can see that on-state current increases with channel stripes increasing. This is due to side wall effect and the better gate control capability in the multi-channel structure TFTs. The side wall effect means that we gain extra channel width in multi-channel structure TFTs as shown in Fig. 3-3 and then the better gate control capability is due to the poly-gate climb across channel region to form the tri-gate structure in multi-channel TFTs.

Threshold voltage and subthreshold swing decreased with the stripes of channel increased is also due to the better gate capability in multi-channel TFTs.

Fig. 3-6 shows the field effect mobility of P-type multi-channel poly-Si TFTs with different stripes of channel. It can be seen that the field effect mobility increases when stripes of channel increases. Because we extracted filed effect mobility from transfer characteristics at V_DS=-0.1, the enhancement of mobility can be also explained to the side wall effect and the better gate control capability in the multi-channel structure TFTs. Fig. 3-7 shows the distribution of threshold voltage and field effect mobility of the proposed multi-channel poly-Si TFTs with different stripes of channel. The vertical bars indicate the minimum and maximum value of the devices characteristics and the squares are the average values. In this figure, we can clear see the threshold voltage decreased when stripes of channel increased and the mobility increased as stripes of channel increased. In this figure, we also found that we gained better uniformity in proposed poly-Si TFTs due to better gate control capability.

It has been reported that the grain boundary trap state density in the channel regions near the pattern edge is much lower than elsewhere in the poly-Si channel [6].

In order to verify if the trap state density reduced or not, the effective trap state density (Nt) was calculated. Figure 3-8 shows the effective trap state density

extraction of the poly-Si TFTs with various stripes of channel. This figure shows the plot of ln[I^DS/(VGS−Vfb)] versus 1/(VGS−Vfb)² and we fitted line for each different stripes. We can see that the slop decreased with the stripes of channel increased and then we utilized this slop to calculated effective trap state density. The effective trap state density for S1, M4, M8, M20, and M40 are 6.42×10¹²cm^-2, 6.28×10¹²cm^-2, 6.18×10¹²cm^-2, 5.46×10¹²cm^-2,and 4.87×10¹² ,respectively. This is because the better gate control capability causes the lower potential barrier locating at the grain boundary and easy to passivate trap state in the grain boundary when we done plasma treatment. Fig. 3-9 shows the plot of trap state density versus different strips of channel. We can see that trap state density decreases with channel stripes increasing obviously. However, from Fig. 3-10, we can see that the increase ratios of the on-state current for M4, M8, M20, and M40 are 2.17%, 4.62%, 17.1% and 35.3%, respectively, and they are much larger than the increase ratio of the effective channel width.

Therefore, we demonstrated the channel sidewall effect was not the only factor to improve the electrical characteristics of multiple channel poly-Si TFTs. The better gate control capability is another factor to improve the on-current and field effect mobility because there are many corner in the multiple channel structure, the corner’s electrostatic focusing is very strong and caused high carrier concentration in the channel region.

Figure 3-11 shows the output characteristics of the conventional and proposed poly-Si TFTs with different stripes of channel under V_G－Vth=-1; -2; -3V. It can be seen that the floating body effect was suppressed with the increase of the stripes of poly-Si channels. The better gate control ability, the larger depletion region existed in the channel, and therefore the fewer electrons accumulated within the channel region.

So, it can be concluded that the floating body effect suppression was attributed to the improvement of gate control capability.

3.3.2 Reliability of P-Channel poly-Si TFTs with multiple channels

Finally, the reliability issue of the conventional and the proposed poly-Si TFTs with single, 2, 4, 10, and 20 stripes of the same total channel width were discussed.

The hot-carrier stress test was performed at V_D,stress=-15V, V_G,stress=-15V, and source electrode grounded for 500sec to investigate the device reliability. Figure 3-12 shows the variations of the on-state current (I_on) and threshold voltage (V_th) over hot carrier stress time. The variations of Ion and Vth, were defined as (Ion,stressed －－－－ I_on,initial)/I_on,initial×100% and (Vth,stressed－－－－Vth,initial)/V_th,initial×100%, respectively, where Ion,stressed, Vth,stressed, Ion,initial, and Vth,initial, represent the measured values before and after electrical stress. In this figure, we can see that the degradation rate of the on-state current and threshold voltage improved with the increase of the stripes of poly-Si channel. This is due to better gate control capability in multiple channel structure. The depletion region in channel region becomes large so that fewer electron accumulation in the channel region. The floating body effect and effect of parasitic bipolar junction transistor will be suppressed. So, the reliability of multiple channel poly-Si TFTs were improved.

3.4 Summary

The effects of the numbers of the channel strips in P-type multi-channel TFTs on the performance and reliability have been investigated. As the stripes increased, the electrical characteristics and reliability of devices were improved significantly due to the enhancement of gate control capability. The n-type multi-channel TFTs have been investigated in previous reports. So, we might integrate n-type and p-type multi-channel TFTs to CMOS application. Furthermore, using CMOS technique applies to 3-D circuit applications.

Reference:

[1] H. Kuriyama, Y. Ishigaki, Y. Fujii, S. Maegawa, S. Maeda, S. Miyamoto, K.

Tsutsumi, and H. Miyoshi, “A C-Switch Cell for Low-Voltage Operation and High-Density SRAMs,” in IEDM Tech. Dig., pp. 279-282, 1996.

[2] A. Mimura, J. I. Ohwada, Y. Hosokawa, T. Suzuki, H. Kawakami, and K. Miyata,

“A High-Resolution Active Matrix Using p-Channel SO1 TFT’s,” IEEE Trans.

Electron Devices, vol. 35, no. 4, pp. 418-425, 1988.

[3] Nae-In Lee, Jin-Woo Lee, Hyoung-Sub Kim, and Chul-Hi Han,

“High-Performance EEPROM’s Using N- and P-Channel Polysilicon Thin-Film Transistors with Electron Cyclotron Resonance N O-Plasma Oxide”

IEEE Electron Device Lett., Vol. 20, no. 1, pp. 15-17, 1999.

[4] N. Yamauchi, J-J. J. Hajjar, Rafael Reif, Kenji Nakazawa, and Keiji Tanaka,

“Characteristics of narrow-channel polysilicon thin-film transistors,” IEEE Trans.

Electron Devices, vol. 38, no. 11, pp. 1967-1968, 1991.

[5] D. N. Yaung, Y. K. Fang, K. C. Hwang, K. Y. Lee, K. H. Wu, J. J. Ho, C. Y. Chen, Y. J. Wang, M. S. Liang, J. Y. Lee, and S. G. Wuu, “Narrow width effects of bottom-gate polysilicon thin film transistors,” IEEE Electron Device Lett., vol. 19, PP, 429-431, 1988.

[6] H. W. Zan, T. C. Chang, P. S. Shih, D. Z. Peng, T. Y. Huang, and C. Y. Chang,

“Analysis of Narrow Width Effects in polycrystalline Silicon Thin Film Transistors,” Jpn. J. Appl. Phys., vol. 42, part 1, no. 1, pp. 28-32, 2003.

[7] T. Unagami, “High-voltage poly-Si TFT’s with multichannel structure,” IEEE Trans. Electron Devices, vol. 35, no. 12, pp. 2363-2367, 1991.

[8] T. Takeshita, T. Unagami, and O. Kogure, “Study on narrow-strip polycrystalline silicon thin film transistors,” J. Appl. Phys., vol. 27, no. 10, pp. 1937-1941, 1988.

[9] B. S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A.

Murthy, R. Rios, and R. Chau, “High Performance Fully-Depleted Tri-Gate CMOS Transistors,” IEEE Electron Device Lett., vol. 24, no. 4, PP. 263-265, 2003.

[10] Y. C. Wu, T. C. Chang, P. T. Liu, C. S. Chen, C. H. Tu, H. W. Zan, Y. H. Tai, and C. Y. Chang, “Effects of Channel Width on Electrical Characteristics of Polysilicon TFTs With Multiple Nanowire Channels,” IEEE Trans. Electron Devices, vol. 52, no. 10, pp. 2343-2346, 2005.

Fig. 3-1 Process flow of the conventional and multi-channel poly-Si TFTs.

• Wet oxide 5000 Å by furnace

• a - Si channel 1000 Å by LPCVD

• _{Poly - Si} channel formation by SPC

• Gate oxide 500 Å by LPCVD

• Poly Gate 1500 Å by LPCVD

• S/D formation by ion implantation

• Passivation by PECVD

• _{Metal pad}

Fig. 3-2 Cross-section of the conventional and multi-channel poly-Si TFTs is parallel to the direction of the source and drain electrode.

Poly-Gate

G1 G1

G2 G3

G3

Gox Gox

Channel Channel

Fig. 3-3 Cross-section of the conventional and multi-channel poly-Si TFTs is perpendicular to the direction of the source and drain electrode.

Si Wafer

Buffer Thermal Oxide P

⁺

^Poly-Si P

⁺

P

⁺

(a) Conventional TFT with single channel (S1)

(b) Multi-channel TFT with 4 stripes (M4)

(c) Multi-channel TFT with 8 stripes (M8)

S D

G

S D

G

S D

G

S D G

(d) Multi-channel with 20 stripes (M20)

S D

G

(e) Multi-channel with 40 stripes (M40)

Fig. 3-4 Top view of the conventional and multi-channel poly-Si TFTs in (a), (b), (c), and (d). (The effective channel width Weff = 40μm ; channel length L = 2μ m.)

Table 3-1 Summary of the dimensions of S1, M4, M8, M20 and M40 TFTs. All devices have the same active channel thickness 100nm, gate TEOS-oxide thickness 50nm, and total channel width 40µ m

S1 M4 M8 M20 M40

Gate length (µm) 2 2 2 2 2

Channel number 1 4 8 20 40

Each channel width (µm) 40 10 5 2 1

Table 3-2 Summary of device parameters of the conventional and the proposed p-channel multi-channel poly-Si TFTs (W/L = 40µ m/2µ m) with different stripes of channel.

S1 M4 M8 M20 M40

V

th

(V) -11.5 -11.0 -10.5 -9.7 -8.9 S.S(V/dec.) 1.287 1.276 1.204 1.123 1.143 µ

_eff

(cm2/V.s) 14.1 14.5 15.0 16.3 18.6 I

_on

@ V

_G

=25V(A) 8.95*10

^-4

9.14*10

^-4

9.36*10

^-4

1.05*10

^-3

1.21*10

^-3

I

off

@ V

G

=0V(A) 6.67*10

^-9

7.65*10

^-9

1.04*10

^-8

1.10*10

^-8

1.37*10

^-8

ON/OFF Ratio 1.34*10

⁵

1.20*10

⁵

0.9*10

⁵

0.96*10

⁵

0.88*10

⁵

Nt (cm

^-2

) 6.42*10

¹²

6.28*10

¹²

6.18*10

¹²

5.46*10

¹²

4.87*10

¹²

-10^-12 -10^-11 -10^-10 -10^-9 -10^-8 -10^-7 -10^-6 -10^-5 -10^-4

-25 -20 -15 -10 -5 0

S1M4 M8M20 M40

D ra in C ur re nt (A )

Gate Voltage (V)

W/L = 40µµµµm/2µµµµm

V_DS=-0.1V

Fig. 3-5 Transfer characteristics of the conventional and the proposed p-channel multi-channel poly-Si TFTs with different stripes of channel.

0 5 10 15 20

-25 -20 -15 -10 -5 0

S1M4 M8M20 M40

Gate Voltage (V)

W/L =40µµµµm/2µµµµm V_DS = 0.1V

Fi el d E ff ec t M ob ili ty , µµµµ

eff

(c m

2

/V .s ec )

Fig. 3-6 Field effect mobility of the conventional and the proposed p-channel multi-channel poly-Si TFTs with different stripes of channel.

Threshold Voltage (V)

(b) Field effect mobility distribution

Fig. 3-7 Distribution of (a) Threshold voltage and (b) Field effect mobility of the proposed p-channel multi-channel poly-Si TFTs with different stripes of channel. The vertical bars indicate the minimum and maximum value of the devices characteristics and the squares are the average values

-17.5 -17 -16.5 -16 -15.5 -15 -14.5 -14 -13.5

0 0.005 0.01 0.015 0.02

S1M4 M8M20 M40

y = -13.083 - 221.28x R= 0.99804 y = -13.119 - 211.53x R= 0.99883 y = -13.123 - 205.11x R= 0.99901 y = -13.156 - 159.9x R= 0.99888 y = -13.095 - 127.35x R= 0.99802

1/(V

_GS

-V

_FB

)

²

(V

^-2

) ln [ I

DS

/(V

GS

-V

FB

) ] (ΩΩΩΩ

-1

)

Fig. 3-8 Trap state density extraction of the conventional and the proposed p-channel multi-channel poly-Si TFTs with different stripes of channel.

4.5 10¹² 5 10¹² 5.5 10¹² 6 10¹² 6.5 10¹²

0 10 20 30 40 50

Tr ap S ta te D en si ty (c m

-2

)

Number of Channel Stripe

Fig. 3-9 Trap state density of the proposed p-channel multi-channel poly-Si TFTs with different stripes of channel.

0 5 10 15 20 25 30 35 40

0 10 20 30 40 50

Effective channel width On-State Current

E nh an ce p er ce nt ag e (% )

Number of Channel Stripe

W/L = 40µµµµm/2µµµµm

On-State current measured at V_DS=5V ; V_GS=20V

Fig. 3-10 Increasing ratio of the effective channel width and the on-state current as a function of number of channel stripes.

0 2 10^-5 4 10^-5 6 10^-5 8 10^-5 10^-4

-10 -8 -6 -4 -2 0

S1M4 M8M20 M40

D ra in C ur re nt , I

D

(A )

Drain Voltage, V

_D

(V)

W/L = 40µµµµm/2µµµµm V_G-V_th = -1 ;- 2 ;- 3V

Fig. 3-11 Output characteristics of the conventional and the proposed p-channel poly-Si TFTs with different stripes of channel. (V_G – V_th = 1; 2; 3V)

0

(a) On-state current degradation with stress time

-2.5

(b) Threshold voltage degradation with stress time

Fig. 3-12 (a) on-current, and (b) threshold voltage degradation as a function of stress time under hot-carrier stress.

Chapter 4

Investigated the lifetime of low temperature poly-Si TFTs with different dimension of channel

4.1 Introduction

Poly-Si TFTs have received much attention in recent years because of their applications. , such as active matrix liquid crystal displays (AMLCDs) [1] , active matrix organic light emitting displays (AMOLEDs) [2] , high density static random access memories (SRAMs) [3], electrical erasable programming read only memories (EEPROM) [4] and candidate for 3-dimenstion ICs’ applications [5] . Although, it have many studies to improve performance of poly-Si TFTs. However, the lifetime issues of poly-Si TFTs are not well studied. Because body contact is a lack of poly-Si TFTs, the floating body effect will influence the reliability of device. To date, there still does not exit a clear consensus on the hot-carrier effect of these devices compared to bulk. For this reason, we interest in studying of lifetime of poly-Si TFTs.

The investigated of lifetime issue in MOSFET have been well-studied. For MOSFET, drain-avalanche-hot-carrier (DAHC) injection, based on impact ionization near the drain, causes the severest damage on the device’s characteristics. The device’s degradation depends on the trap states generation, which is also proportional

The investigated of lifetime issue in MOSFET have been well-studied. For MOSFET, drain-avalanche-hot-carrier (DAHC) injection, based on impact ionization near the drain, causes the severest damage on the device’s characteristics. The device’s degradation depends on the trap states generation, which is also proportional

在文檔中 低溫複晶矽薄膜電晶體之遷移率與可靠度之研究 (頁 35-0)