Reliability of P-Channel poly-Si TFTs with Multiple Channels

Finally, the reliability issue of the conventional and the proposed poly-Si TFTs with single, 2, 4, 10, and 20 stripes of the same total channel width were discussed.

The hot-carrier stress test was performed at V_D,stress=-15V, V_G,stress=-15V, and source electrode grounded for 500sec to investigate the device reliability. Figure 3-12 shows the variations of the on-state current (I_on) and threshold voltage (V_th) over hot carrier stress time. The variations of Ion and Vth, were defined as (Ion,stressed －－－－ I_on,initial)/I_on,initial×100% and (Vth,stressed－－－－Vth,initial)/V_th,initial×100%, respectively, where Ion,stressed, Vth,stressed, Ion,initial, and Vth,initial, represent the measured values before and after electrical stress. In this figure, we can see that the degradation rate of the on-state current and threshold voltage improved with the increase of the stripes of poly-Si channel. This is due to better gate control capability in multiple channel structure. The depletion region in channel region becomes large so that fewer electron accumulation in the channel region. The floating body effect and effect of parasitic bipolar junction transistor will be suppressed. So, the reliability of multiple channel poly-Si TFTs were improved.

3.4 Summary

The effects of the numbers of the channel strips in P-type multi-channel TFTs on the performance and reliability have been investigated. As the stripes increased, the electrical characteristics and reliability of devices were improved significantly due to the enhancement of gate control capability. The n-type multi-channel TFTs have been investigated in previous reports. So, we might integrate n-type and p-type multi-channel TFTs to CMOS application. Furthermore, using CMOS technique applies to 3-D circuit applications.

Reference:

[1] H. Kuriyama, Y. Ishigaki, Y. Fujii, S. Maegawa, S. Maeda, S. Miyamoto, K.

Tsutsumi, and H. Miyoshi, “A C-Switch Cell for Low-Voltage Operation and High-Density SRAMs,” in IEDM Tech. Dig., pp. 279-282, 1996.

[2] A. Mimura, J. I. Ohwada, Y. Hosokawa, T. Suzuki, H. Kawakami, and K. Miyata,

“A High-Resolution Active Matrix Using p-Channel SO1 TFT’s,” IEEE Trans.

Electron Devices, vol. 35, no. 4, pp. 418-425, 1988.

[3] Nae-In Lee, Jin-Woo Lee, Hyoung-Sub Kim, and Chul-Hi Han,

“High-Performance EEPROM’s Using N- and P-Channel Polysilicon Thin-Film Transistors with Electron Cyclotron Resonance N O-Plasma Oxide”

IEEE Electron Device Lett., Vol. 20, no. 1, pp. 15-17, 1999.

[4] N. Yamauchi, J-J. J. Hajjar, Rafael Reif, Kenji Nakazawa, and Keiji Tanaka,

“Characteristics of narrow-channel polysilicon thin-film transistors,” IEEE Trans.

Electron Devices, vol. 38, no. 11, pp. 1967-1968, 1991.

[5] D. N. Yaung, Y. K. Fang, K. C. Hwang, K. Y. Lee, K. H. Wu, J. J. Ho, C. Y. Chen, Y. J. Wang, M. S. Liang, J. Y. Lee, and S. G. Wuu, “Narrow width effects of bottom-gate polysilicon thin film transistors,” IEEE Electron Device Lett., vol. 19, PP, 429-431, 1988.

[6] H. W. Zan, T. C. Chang, P. S. Shih, D. Z. Peng, T. Y. Huang, and C. Y. Chang,

“Analysis of Narrow Width Effects in polycrystalline Silicon Thin Film Transistors,” Jpn. J. Appl. Phys., vol. 42, part 1, no. 1, pp. 28-32, 2003.

[7] T. Unagami, “High-voltage poly-Si TFT’s with multichannel structure,” IEEE Trans. Electron Devices, vol. 35, no. 12, pp. 2363-2367, 1991.

[8] T. Takeshita, T. Unagami, and O. Kogure, “Study on narrow-strip polycrystalline silicon thin film transistors,” J. Appl. Phys., vol. 27, no. 10, pp. 1937-1941, 1988.

[9] B. S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A.

Murthy, R. Rios, and R. Chau, “High Performance Fully-Depleted Tri-Gate CMOS Transistors,” IEEE Electron Device Lett., vol. 24, no. 4, PP. 263-265, 2003.

[10] Y. C. Wu, T. C. Chang, P. T. Liu, C. S. Chen, C. H. Tu, H. W. Zan, Y. H. Tai, and C. Y. Chang, “Effects of Channel Width on Electrical Characteristics of Polysilicon TFTs With Multiple Nanowire Channels,” IEEE Trans. Electron Devices, vol. 52, no. 10, pp. 2343-2346, 2005.

Fig. 3-1 Process flow of the conventional and multi-channel poly-Si TFTs.

• Wet oxide 5000 Å by furnace

• a - Si channel 1000 Å by LPCVD

• _{Poly - Si} channel formation by SPC

• Gate oxide 500 Å by LPCVD

• Poly Gate 1500 Å by LPCVD

• S/D formation by ion implantation

• Passivation by PECVD

• _{Metal pad}

Fig. 3-2 Cross-section of the conventional and multi-channel poly-Si TFTs is parallel to the direction of the source and drain electrode.

Poly-Gate

G1 G1

G2 G3

G3

Gox Gox

Channel Channel

Fig. 3-3 Cross-section of the conventional and multi-channel poly-Si TFTs is perpendicular to the direction of the source and drain electrode.

Si Wafer

Buffer Thermal Oxide P

⁺

^Poly-Si P

⁺

P

⁺

(a) Conventional TFT with single channel (S1)

(b) Multi-channel TFT with 4 stripes (M4)

(c) Multi-channel TFT with 8 stripes (M8)

S D

G

S D

G

S D

G

S D G

(d) Multi-channel with 20 stripes (M20)

S D

G

(e) Multi-channel with 40 stripes (M40)

Fig. 3-4 Top view of the conventional and multi-channel poly-Si TFTs in (a), (b), (c), and (d). (The effective channel width Weff = 40μm ; channel length L = 2μ m.)

Table 3-1 Summary of the dimensions of S1, M4, M8, M20 and M40 TFTs. All devices have the same active channel thickness 100nm, gate TEOS-oxide thickness 50nm, and total channel width 40µ m

S1 M4 M8 M20 M40

Gate length (µm) 2 2 2 2 2

Channel number 1 4 8 20 40

Each channel width (µm) 40 10 5 2 1

Table 3-2 Summary of device parameters of the conventional and the proposed p-channel multi-channel poly-Si TFTs (W/L = 40µ m/2µ m) with different stripes of channel.

S1 M4 M8 M20 M40

V

th

(V) -11.5 -11.0 -10.5 -9.7 -8.9 S.S(V/dec.) 1.287 1.276 1.204 1.123 1.143 µ

_eff

(cm2/V.s) 14.1 14.5 15.0 16.3 18.6 I

_on

@ V

_G

=25V(A) 8.95*10

^-4

9.14*10

^-4

9.36*10

^-4

1.05*10

^-3

1.21*10

^-3

I

off

@ V

G

=0V(A) 6.67*10

^-9

7.65*10

^-9

1.04*10

^-8

1.10*10

^-8

1.37*10

^-8

ON/OFF Ratio 1.34*10

⁵

1.20*10

⁵

0.9*10

⁵

0.96*10

⁵

0.88*10

⁵

Nt (cm

^-2

) 6.42*10

¹²

6.28*10

¹²

6.18*10

¹²

5.46*10

¹²

4.87*10

¹²

-10^-12 -10^-11 -10^-10 -10^-9 -10^-8 -10^-7 -10^-6 -10^-5 -10^-4

-25 -20 -15 -10 -5 0

S1M4 M8M20 M40

D ra in C ur re nt (A )

Gate Voltage (V)

W/L = 40µµµµm/2µµµµm

V_DS=-0.1V

Fig. 3-5 Transfer characteristics of the conventional and the proposed p-channel multi-channel poly-Si TFTs with different stripes of channel.

0 5 10 15 20

-25 -20 -15 -10 -5 0

S1M4 M8M20 M40

Gate Voltage (V)

W/L =40µµµµm/2µµµµm V_DS = 0.1V

Fi el d E ff ec t M ob ili ty , µµµµ

eff

(c m

2

/V .s ec )

Fig. 3-6 Field effect mobility of the conventional and the proposed p-channel multi-channel poly-Si TFTs with different stripes of channel.

Threshold Voltage (V)

(b) Field effect mobility distribution

Fig. 3-7 Distribution of (a) Threshold voltage and (b) Field effect mobility of the proposed p-channel multi-channel poly-Si TFTs with different stripes of channel. The vertical bars indicate the minimum and maximum value of the devices characteristics and the squares are the average values

-17.5 -17 -16.5 -16 -15.5 -15 -14.5 -14 -13.5

0 0.005 0.01 0.015 0.02

S1M4 M8M20 M40

y = -13.083 - 221.28x R= 0.99804 y = -13.119 - 211.53x R= 0.99883 y = -13.123 - 205.11x R= 0.99901 y = -13.156 - 159.9x R= 0.99888 y = -13.095 - 127.35x R= 0.99802

1/(V

_GS

-V

_FB

)

²

(V

^-2

) ln [ I

DS

/(V

GS

-V

FB

) ] (ΩΩΩΩ

-1

)

Fig. 3-8 Trap state density extraction of the conventional and the proposed p-channel multi-channel poly-Si TFTs with different stripes of channel.

4.5 10¹² 5 10¹² 5.5 10¹² 6 10¹² 6.5 10¹²

0 10 20 30 40 50

Tr ap S ta te D en si ty (c m

-2

)

Number of Channel Stripe

Fig. 3-9 Trap state density of the proposed p-channel multi-channel poly-Si TFTs with different stripes of channel.

0 5 10 15 20 25 30 35 40

0 10 20 30 40 50

Effective channel width On-State Current

E nh an ce p er ce nt ag e (% )

Number of Channel Stripe

W/L = 40µµµµm/2µµµµm

On-State current measured at V_DS=5V ; V_GS=20V

Fig. 3-10 Increasing ratio of the effective channel width and the on-state current as a function of number of channel stripes.

0 2 10^-5 4 10^-5 6 10^-5 8 10^-5 10^-4

-10 -8 -6 -4 -2 0

S1M4 M8M20 M40

D ra in C ur re nt , I

D

(A )

Drain Voltage, V

_D

(V)

W/L = 40µµµµm/2µµµµm V_G-V_th = -1 ;- 2 ;- 3V

Fig. 3-11 Output characteristics of the conventional and the proposed p-channel poly-Si TFTs with different stripes of channel. (V_G – V_th = 1; 2; 3V)

0

(a) On-state current degradation with stress time

-2.5

(b) Threshold voltage degradation with stress time

Fig. 3-12 (a) on-current, and (b) threshold voltage degradation as a function of stress time under hot-carrier stress.

Chapter 4

Investigated the lifetime of low temperature poly-Si TFTs with different dimension of channel

4.1 Introduction

Poly-Si TFTs have received much attention in recent years because of their applications. , such as active matrix liquid crystal displays (AMLCDs) [1] , active matrix organic light emitting displays (AMOLEDs) [2] , high density static random access memories (SRAMs) [3], electrical erasable programming read only memories (EEPROM) [4] and candidate for 3-dimenstion ICs’ applications [5] . Although, it have many studies to improve performance of poly-Si TFTs. However, the lifetime issues of poly-Si TFTs are not well studied. Because body contact is a lack of poly-Si TFTs, the floating body effect will influence the reliability of device. To date, there still does not exit a clear consensus on the hot-carrier effect of these devices compared to bulk. For this reason, we interest in studying of lifetime of poly-Si TFTs.

The investigated of lifetime issue in MOSFET have been well-studied. For MOSFET, drain-avalanche-hot-carrier (DAHC) injection, based on impact ionization near the drain, causes the severest damage on the device’s characteristics. The device’s degradation depends on the trap states generation, which is also proportional to the substrate current (Isub) [6]. Therefore, DAHC-induced Isub is used to monitor the device degradation and to predict the device lifetime. Under the severest DAHC stress, the empirical model for the lifetime prediction has been reported. It showed a single slope lifetime projection.

Due to the lack of body terminal in poly-Si TFT, holes generated during impact ionization will be recombined with electron as they flow to the channel, or they will accumulate in the substrate near the source. The injection of holes into the body will lowers the potential barriers between the source and the channel. When the voltage drop across the body-source junction is large enough, the parasitic bipolar transistors (PBT) will be turned on. The action of PBT will enhance the on-current and then increase the device degradation rate [7]. Therefore, PBT should be considered as predicting the lifetime of poly-Si TFTs. In this chapter, we used the conventional empirical extrapolating method of MOSFETs to predict the lifetime of poly-Si TFTs.

However, there was apparent dual slop lifetime versus the reciprocal drain voltage behavior in wide range drain stress voltages (V_DS). Typically, extrapolation of the lifetime to low drain voltages can be made from results obtained by stressing at large drain voltages. So, it will make wrong lifetime extraction in poly-Si TFTs. We also investigated influence of channel dimension about lifetime in poly-Si TFTs. It showed different phenomena in short and long channel device due to PBT effect. We will discuss this in detail in a later section.

4.2 Experiment

Figure 4-1 and 4-2 show the process flow and cross-sectional view of the investigated poly-Si TFT. First, 500-nm-thick thermal oxide was grown on the Si wafer by using a furnace system. All the experimental devices in this study were fabricated on thermally oxidized Si wafers. Then, 100-nm-thick amorphous silicon layers were deposited on the thermal oxide layer using a low-pressure chemical vapor deposition (LPCVD) system at 550°C. Then, amorphous silicon films were recrystallized by solid phase crystallization (SPC) method at 600°C for 24 hours in an N2 ambient to form poly-Si films. Poly-Si films were patterned into active regions by

transformer couple plasma (TCP) etching system using mixture gases of Cl₂ and HBr.

After RCA cleaning procedure, a 50-nm-thick TEOS oxide was deposited by LPCVD with TEOS and O₂ gases at 695°C to form the gate insulator. A 150-nm-thick poly-Si was deposited to serve as the gate electrode by LPCVD at 595°C. Then, the poly-Si film was patterned and etched by TCP etching system to form the gate electrode and the gate oxide on source/drain was removed using dilute HF solution.

The regions of source, drain, and gate were doped by a self-aligned phosphorous ion implantation at the dosage and energy of 5×10¹⁵ions/cm^-2 and 30keV, respectively.

The dopant activation was performed by rapid thermal annealing (RTA) system at 700°C for 30sec, followed by a deposition of 400nm-thick passivation oxide using PECVD system at 350°C and the definition of contact holes. Finally, a 500-nm-thick Al was deposited by sputter and patterned for metal pads, and devices were passivated by NH₃ plasma treatment for 1 hour at 300°C. The transfer characteristics of the poly-Si TFT is shown in Fig. 4-3.

4.3 Result and Discussion

Impact ionization near the drain is a main mechanism to cause substantial trap states at the interface for MOSFETs under a hot carrier stress. From the empirical model, the I_on degradation can be expressed as

n

increase of trap states, which are also proportional to the number of electron-hole pairs generated by impact ionization, can be also expressed in the same dependency [8][9].

N ∝ it Isub ∝ α ∝ ^{exp −}

(

^{c /E}

)

^{∝ exp −}

(

^{c /VDS}

)

^{∝ Ac/a} --- (Eq. 4.3) where α is the impact ionization factor, c is a constant, and E is the local electric field near the drain. Using (Eq. 4.2), (Eq. 4.3), and (Eq. 4.4), the lifetime (τ ) of the MOSFET under a certain criterion can be expressed as:

τ

∝ ^exp

(

^bVDS

)

--- (Eq. 4.4)

where b is also a constant. In equation 4-4, we can see that the lifetime proportional to the reciprocal drain voltage at log-scale and only single lifetime projection in this conventional empirical model. In this chapter, we will use this conventional empirical model to investigate the lifetime of poly-Si TFTs.

First, we define the worst case of hot carrier stress of poly-Si TFTs. It has been demonstrated that the worst-case hot carrier degradation for MOSFET is known to be under V_G=1/2 V_D [10]. However, due to the PBT action, the worst-case degradation for SOI-MOSFETs is V_G≈V^th [11]. However, the worst-case hot carrier degradation for poly-Si TFTs have not been investigated well and few reports emphasized the relationship between the worst-case hot carrier degradation and the channel dimension.

Fig. 4-4 shows the on-current degradation under stress conditions of V_G=1/2V_D and VG=Vth at VDS=16V for different channel geometry. Fig. 4-4(a) shows the on-current degradation rate of the channel length L=10_µm and the channel width W=10_µm. In this channel geometry, we found that the VG=1/2VD cause severest damage of poly-Si TFTs. Fig.4-4(b) shows the on-current degradation rate of the channel length L=2_µm and the channel width W=10_µm. In this channel geometry, we found that the VG= Vth

cause severest damage of poly-Si TFTs. Fig.4-4(c) shows the on-current degradation

rate of the channel length L=2_µm and the channel width W=2_µm. In this channel geometry, we found that the VG= Vth also cause severest damage of poly-Si TFTs. We make a conclusion that the worst-case hot carrier degradation for poly-Si TFTs relate to the channel length significantly. In short channel device, the worst-case condition is V_G= V_th

.

However, the worst-case condition is V_G=1/2 V_Din long channel device.

Following, the DC stress VG= Vth , wide drain voltage and source grounded was performed for 1000sec with different channel geometry. Fig. 4-5 shows the lifetime extraction of poly-Si TFTs with channel length of 10µ m and channel width of 10µ m.

The on-current variation is a function of stress time with various V_DS as shown in Fig.

4-5(a). As can be seen, the slope n, in log-log plot depends on the V^DS strongly.

Obviously, two sets of slopes can be observed. The slopes for high V_DS stress conditions are higher than the low VDS stress conditions’. Fig. 4-5(b) presents the lifetime (τ ) as function of the reciprocal V^DS. The lifetime is defined as the time taken for 10% Ion degradation. We found the dual slopes lifetime projection in wide drain voltage. The slopes for high drain voltage regionare lower than the low drain voltage region’s. This indicated that high drain voltage region cause severest damage of poly-Si TFTs. This phenomenon will be discussed later. Fig. 4-6 shows the lifetime extraction of poly-Si TFTs with channel length of 2µ m and channel width of 10µ m.

The on-current variation is a function of stress time with various V_DS as shown in Fig.

4-6(a). It also can be found that the slope n depends on the V^DS and two sets of slopes appeared in this figure. The slopes for low V_DS stress conditions are higher than the high VDS stress conditions’. A similar tendency has been investigated in SOI MOSFETs [12][13] . Fig. 4-6(b) presents the lifetime (τ ) as function of the reciprocal VDS. We can see the dual slopes lifetime projection in wide drain voltage. The slopes for low drain voltage region are lower than the high drain voltage region’s. This illustrated that low drain voltage region cause severest damage of poly-Si TFTs. We

are also interested in the lifetime issues of different channel width. Fig. 4-7 shows the lifetime extraction of poly-Si TFTs with channel length of 2µ m and channel width of 2µ m. Fig 4-7(a) shows the on-current variation as a function of stress time with various VDS. Fig. 4-7(b) presents the lifetime (τ ) as function of the reciprocal V^DS. It is obviously that Fig. 4-6 and Fig. 4-7 have the same tendency. We deduced that the lifetime issue greatly depends on channel length. We explained these phenomenons of above as following.

So, when predicting the lifetime of poly-Si TFTs, the PBT phenomenon must be considered. Figure 4-8 shows the current generation in the poly-Si TFTs with a floating body. In this figure, the intrinsic drain current (ID) induces a hole current (Isub) due to impact ionization near the drain side, and the I_sub, which flows to the source induces a bipolar electron current (Ie), can be expressed as:

( )

^D

sub M I

I = −1 --- (Eq. 4.5) The bipolar electron current (Ie) can be expressed as:

( )

^sub

( )( )

^D

e I M I

I = β +1 = β+1 −1 --- (Eq. 4.6) where β is the bipolar current gain, and M is the impact-ionization multiplication factor, which can be expressed as:

(

^{M −1}

)

⁼

∫

^αdy --- (Eq. 4.7)

Then, I_e which injects into the channel will enlarge I_D, and enhance impact ionization near the drain to generate higher Isub.

( )( )

( ) [ ( ) ( ) ]

is proportional to the reciprocal Isub. So, it can be expresses as:

τ

∝ ¹

(

^β+1

) (

^{A0 M −1}

)

^B0 --- (Eq. 4.11)

where A₀ and B₀ are constant. As can be seen, this form shows the lifetime prediction including both impact ionization and PBT effects.

Moreover, it has been investigated by using simulation method that β varies condition, the PBT action must be considered. So, we can see that low drain voltage region cause severest damage of poly-Si TFTs for short channel device as shown in Fig. 4-6 and Fig. 4-7. However, it has opposite tendency in long channel device as shown in Fig. 4-5. We illustrated that as following. Impact ionization occurs near the drain side and electron flows into drain electrode. However, hole flows to bottom of channel and source side due to vertical electric field and lateral electric field, respectively. Recombination mechanism will occurs when hole flows in the channel.

Then, the hole that flows to the source side decreases due to moving in the long channel. However, a small number of the hole near the source side can’t raise potential enough to turn on the parasitic BJT. As this condition, the increasing of lateral electric field will make the number of the hole that flows to the source side increasing. The parasitic BJT will be turned on as drain voltage increasing. So, Fig.

4-5 shows that high drain voltage region cause severest damage of poly-Si TFTs. This is also due to parasitic BJT effect.

4.4 Summary

The Lifetime issue of poly-Si TFTs with different channel geometry has been investigated. The worst-case of stress conditions is under V_G≈V^th not V_G=1/2 V_D in short channel poly-Si TFTs. Moreover, I_on degradation under both high and low V_D of stress conditions has different phenomena. This is due to not only impact ionization but also parasitic bipolar junction transistor effect to degradation poly-Si TFTs. Then, it is found that lifetime extraction of poly-Si TFTs is not the same with that of MOSFETs. There are dual slopes lifetime projections in wide drain voltage. We can’t use the high drain voltage to accelerate degradation of poly-Si TFTs as before because this method will extract wrong lifetime.

References:

[1] Y. Oana, “Current and future technology of low-temperature poly-Si TFT-LCDs,”

Journal of the SID, vol. 9, pp. 169-172, 2001.

[2] Mark Stewart, Robert S. Howell , Leo Pires, Miltiadis K. Hatalis, Webster Howard, and Olivier Prache, “Polysilicon VGA active matrix OLED displays – technology and performance”, in IEDM tech, Dig., 1998,pp.871-874

[3] S. Batra, “Development of drain-offset (DO) TFT technology for high density SRAM’s,” Extended Abstracts, vol.94-2, in Electrochemical Soc. Fall Mtg., Miami Beach, FL, Oct. pp. 677,1994.

[4] N. D. Young, G. Harkin, R. M. Bunn, D. J. McCulloch, and I. D. French, “The fabrication and characterization of EEPROM arrays on glass using a low temperature poly-Si TFT process,” IEEE Trans. Electron Devices, vol. 43, pp.

1930-1936, 1996.

[5] K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, “3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and system-on-chip integration,” Proceedings of the IEEE, vol.89, pp. 602-633, 2001.

[6] C. M. Hu, S. C. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan, and K. W. Terrill, “Hot electron induced MOSFET degradation_—model, monitor, and improvement,”

IEEE Trans. Electron Devices, vol. 32, no. 2, pp. 375-385, 1985.

[7] G. A. Armstrong, S. D. Brotherton, and J. R. Ayres, “A comparison of the kink effect in polysilicon thin film transistors and silicon on insulator transistors,” Solid State Electronics, vol. 39, no. 9, pp. 1337-1346, Sept. 1996.

[8] T. Y. Chan, P. K. Ko, and C. Hu, “A simple method to characterize substrate current in MOSFET’s,” IEEE Electron Device lett., vol. 5, no. 12, pp. 505-507, 1984.

[9] E. Takeda, H. Kume, T. Toyade, and S. Asai, “Submicrometer MOSFET structure for minimizing hot-carrier generation,” IEEE Trans. Electron Devices, vol. 29, no.

4, pp. 611-617, 1982.

[10] P. H. Worelee, C. Juffermans, H. Lifka, W. Manders, F. M. Oude Lansink, G. M.

Paulzen, P. Sheridan, and A. Walker, “A half-micron CMOS technology using ultra-thin silicon on insulator,” in IEDM Tech. Dig., pp. 583-586, 1990.

[11] L. T. Su, H. Fang, J. E. Chung, and D. A. Antoniadis, “Hot-carrier effects in fully-depleted SOI nMOSFETs,” in IEDM Tech. Dig., pp. 349-352, 1992.

[12] J. W. Ratkovic, W. M. Huang, B. Y. Hwang, M. Racanelli, J. Forestner, and J.

Woo, “Novel device lifetime behavior and hot-carrier degradation mechanisms under VGS≈V^TH stress for thin-film SOI nMOSFETs,” in IEDM Tech. Dig., pp.

639-642, 1995.

[13] J. W. Ratkovic, W. M. Huang, B. Y. Hwang, M. Racanelli, J. Forestner, and J.

Woo, “Lifetime reliability of thin-film SOI nMOSFET’s,” IEEE Electron Device

Woo, “Lifetime reliability of thin-film SOI nMOSFET’s,” IEEE Electron Device

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