Orientation Dependent Etching - 矽質奈米級電子元件的研究

Chapter 1 Introduction

1.4 Orientation Dependent Etching

Orientation dependent etching (ODE) is one of the anisotropic wet etching methods.

The different etching rate may be due to the resistivity-dependant selectivity [23], doping type different and so on. ODE in single crystal silicon can always make (111) facet. The slow etch rate in <111> directions is a consequence of the diamond lattice. A (111) plane is a double layer bound together by more atomic bounds than are found between other planes, as illustrated is Figure 1.5 [24].

Because the high selective etching in different planes, (i.e. for TMAH the etching rate between (111) and (100) is about 50) high aspect ratio pattern can be easily formed by ODE method [25].

Compared to the other widely used wet etching etchant KOH, although TMAH has lower etching rate but take advantage of higher etching selectivity to oxide [26], (oxide to Si (100) etching ratio is above 3000) and less mobile ion (K⁺) pollution. The later issue is very important in VLSI device processing. Figure 1.6 show the idea of anisotropic etching pattern on silicon wafer with different surface orientations.

Chapter 1 References

1. R. Feynman’s talk: “There’s plenty of room at the bottom,” December 29,1959.

http://www.zyvex.com/nanotech/feynman.html

2. K. S. You. “”Fabrication technique and characterization of silicon nanowire divice”, Ph. D dissertation, NCTU ((2004)

3. K. Drlica “Understanding DNA and Gene Cloning: A Guide for the Curious,” John Wiley & Sons, Inc, 1997

4. http://www.sandia.gov/media/NewRel/NR2000/labchip.htm

5. N. Shmma, ”A method of correction of proximity effect in optical lithography,” KTI Microlithography Seminar Interface 1991, p. 145.

6. W. Arden and L. Made. SPIE Proc. Vol. 539, Adv. In Resist Technol. and Processing II, 219 (1985)

7. J. Hu, R.G. Beck, T. Deng, R.M. Westervelt, K.D. Mararnowski. Appl. Phys. Lett. 71, 14 (1997)

8. S. Wolf, “Silicon processing for the VLSI era, Vol. 1: process technology,” Lattice Press, 2nd. Chapter 13. (2000)

9. H. Xiao, “Introducton to semiconductor manufacturing technology,” Prentice Hall.

Chapter 6. (2001)

10. S. Y. Chou, P. R. Krauss, and P. J. Renstrom. Science 272, 85 (1996); Appl. Phys. Lett.

67, 3114 (1995).

11. G. Stix, Scientific American, pp34-35, July 2002.

12. J. A. Dagata, J. Schneir, H. H. Harary, C. J. Evans, M. T. Postek, and J. Bennett. Appl.

Phys. Lett. 56, 2001 (1990); J. A. Dagata, Science 270, 1625 (1995).

13. G. Binning, G. H. Rohrer, Ch. Gerber, and E. Weibel. Phys. Rev. Lett. 50, 120 (1983) 14. G. Binning, Ch. Gerber, and E. Stoll, T. R. Albrecht, and C. F. Quate. Europhys. Lett. 3,

120 (1987)

15. J. A. Dagata, T. Inoue, J. Itoh, K. Matsumoto, and H. Yokoyama. J. Appl. Phys. 84, 6891 (1998).

16. H. Sugimura, T. Uchida, N. Kitamura, and H. Masuhara. J. Phys. Chem. 98, 4352 (1994)

17. S. Gwo, C.-L. Yeh, P.-F. Chen, Y.-C. Chou, T. T. Chen, T. S. Chao, S.-F. u, and T.-Y.

Huang, Appl. Phys. Lett. 74, 1090 (1999)

18. F. S. -S. Chien, C.-L. Wu, Y.-C. Chou, T. T. Chen, and S. Gwo, W.-F. Hsieh. Appl.

Phys. Lett. 75, 2429 (1990)

19. G. Binning, C. F. Quate, Phys. Rev. Lett. 56, 930 (1986) 20. G. Meyer, and N. M. Amer. Appl. Phys. Lett. 53, 1045 (1988) 21. Manuscript of AFM M5-type Park Scientific instrument (PSI)

22. G. Abadal, N. Barniol, and X. Aymerich, Appl. Phys. A66, S791 (1988)

23. Runyan. “Semiconductor measurements and instrumentation,” McGraw-Hill (1975) 24. http://www.shef.ac.uk/chemistry/web-elements

25. F. S.-S. Chiena) and W.-F. Hsieh, S. Gwo, A. E. Vladar and J. A. Dagata. J. Appl.

Phys. 91, 12 (2002).

26. W. R. Runyan and K. E. Bean. ”Semiconductor integrated circuit processing technology.” Addison-Wesley (1990)

Table 1.1 COMPARISONS BETWEEN DIFFERENT LITHOGRAPHY METHODS

Parameters EUV X-Ray E-beam Ion-Beam AFM

Light Source In Development In Development Mature Mature None Mask

Fabrication

Mature Very Difficult Mature Mature None

Lens

Resolution High High High High High

Cost High High High High Medium

Throughput High High High Low Low*

Reference: H. Xiao, “Introduction to Semiconductor Manufacturing Technology”, Prentice Hall (2001).

* IBM use tips array to overcome this problem [50].

Table 1.2 COMPARISONS BETWEEN THE CHARACTERISTICS OF OPTICAL MICROSCOPY,

SCANNING ELECTRON MICROSCOPIC AND SCANNING TUNNELING MICROSCOPE.

Parameters Optical Microscopy Scanning Electron Microscopy

Vacuum Ambient air, liquid or vacuum

Little Little to substantial Little or none

Characteristics Required of Sample

Sample must not be completely

transparent to light wavelength used

Surface must not build up charge and must be vacuum compatible

Sample must not have local variations in surface height >

10 um

Figure 1.1 Main components to set up atomic force microscopic

Figure 1.2 Vander Waals force versus distance graph illustrating various types of forces being accessed by the tip at the sample surface.

Figure 1.3 Schema of AFM local oxidation process.

Figure 1.4 Oxide produced by SPL is used as etching mask.

(a) (100) surface (b) (110) surface (c) (111) surface Figure 1.5 Atoms arrangement in diamond structure seen by different directions.

(a) Pits formation after anisotropic etching on (110) surface.

(b) Pits on (100) Wafer, (c) pits on (111) Wafer

Figure 1.6 Anisotropic etching on wafer with different surface orientations, (a) (110) surface, (b) (100) surface, (c) (111) surface.

Chapter 2 Device Fabrication

We use scanning probe lithography and orientation dependent etching methods to fabricate many different nanostructures. There are some other methods to fabricate silicon based nanometer scale devices like nano-imprinting (Figure 2.1 [1]), e-beam lithography plus RIE (Figure .2.2 [2]), two-angle evaporation (Figure 2.3), vertical pattern-dependent method (Figure 2.4 [3]), and break junction (Figure 2.5 [5]). The most benefit of our procedure is its relative low cost, high controllability and flexibility to researchers. A brief comparison is summarized in Table 2.1.

General Fabrication Process

2.1 Wafer preparation

All experiments were performed with intrinsic (110)-oriented Uni-bond SOI wafer, where the initial silicon on insulator is 72.1 nm + 2.3 nm, and the box oxide is 2326 nm + 1.9 nm. Samples are prepared with following processes.

2.2 Define Active Area Regions

2.2.1 Standard RCA Clean and Dry Oxidation

Oxide layer is used as an ion implantation mask layer. During the dry oxidation process, we also thin the top silicon layer to our designed thickness.

2.2.2 Ion Implantation

2.2.3 Define AA region with Mask 1.

2.3 Define Desired Nanostructures

We use AFM to induce local anodic oxidation as hard mask, and orientation dependent wet etching with TMAH to etch top silicon layer in AA region.

2.4 Passivation (Optional)

According to different usage, we can choose different kind of passivation methods.

(Grow thermal oxide, deposit silicon nitride or do nothing). Through this thesis, right now, we only use thermal oxide as a passivation layer.

2.5 Contact Formation

2.5.1: Define Contact Plug with Mask 2 (without P/R remove)

Since passivation is not necessary in the experiment, we didn’t remove photo resist immediately after contact plug formation to avoid Al diffuse into silicon. Photo resist is removed after step 2.5.4.

2.5.3: Coating Aluminum with Thermal Coater 2.5.4: Define Contact Pad with Mask 3

2.5.5 Al sintering

The full schema of process flow is given in Figure 2.6. The AFM pictures of our devices are displayed in Figure 2.7 to Figure 2.11, SEM images are given in Figure 2.12.

Figure 2.7 shows single electron transistor structures, associated properties are given in section 3.2. Figure 2.8 shows the schema of bio detector device, details will be described in section 3.3. Structure in Figure 2.9 is designed to see how the influence of the corner in the nano-scale devices. We want to tell if the back scattering is a dominant factor in such device (particle behavior) or the current is a dependent issue to the field we applied in drain

(wave like). Figure 2.10 shows the idea about quantum influence [6] device. Due to the wave property of the electron, we wish to discover the influence behavior by measuring source-drain current with sweeping control gate voltage. Figure 2.11 displays the prototype of point contact device, some properties of point contact device can be find in reference [7]

and [8]. SEM images in Figure 2.12 confines our ability in both device structure and dimension control.

Chapter 2 References

1. J. C. Love, Scientific American, pp39-47. (2001)

2. D. H. Kim, S. K. Sung, K. R. Kim, J. D. Lee, and B. G. Park, J. Vac. Sci. Technol. B 20.

(2002)

3. Y. C. Liao, S. Y. Lin and S. C. Lee, "Spherical SiGe Quantum Dots Prepared by Thermal Evaporation Method", Appl. Phys. Lett., 77, pp. 4328-4329. (2000)

4. Y. Ono, Y.Takahashi, K. Yamazaki, M. Nagasw, H. Namatusu, K. Murase, IEDM 99-367. (1999)

5. M. A. Reed, Appl. Phys. Lett. 67. (1995)

6. Y. Aharnov and D. Bohm. Phys. Rev. 115, 485 (1959)

7. H. Ishikuro and T. Hiramoto. Appl. Phys. Lett., 74, pp. 1126-1128. (1999)

8. Y. T. Tan, T.Kaymiya, Z. A. K. Durrani, and H. Ahmed. J. Appl. Phys. 94, pp. 633-37.

(2003)

Figure 2.1 Schema of nano-imprinting method

Figure 2.2 E-beam lithography plus reactive ion etching

Figure 2.3 Schema of two-angle evaporation method

Figure 2.4 Schema of vertical pattern-dependent oxidation (V-PADOX) method

Figure 2.5 Schema of break junction method

Figure 2.6 Process Flow

(a) (b)

(e)

(a)

(b)

(a)

(b) Figure 2.8 AFM image of bio detector device

Figure 2.9 AFM image of scattering influence device

Figure 2.10 AFM image of quantum influence device

Figure 2.11 AFM image of point contact device

Figure 2.12 SEM images

Chapter 3 Experiment 2 – Device Characteristics

3.1 Mesoscopic Phenomena

When devices scale down to the size comparable with the electron’s Fermi wavelength of its composed material (i.e. The Fermi wavelength in metal is at the scale about 1 nm, but in semiconductors is about 10 to 100 nm), we called such a system a mesoscopic system.

Such system is at a transparency state between macroscopic (bulk material property) and microscopic (atomic level consideration) system. The number of atoms in the system is not large enough for us to apply the statistics to describe it precisely, but is still too huge for us analyzed it with quantum mechanism from bottom up. Weak localization [1] and universal conductance fluctuation [2] are two major characteristics when we describe such a system.

The variety and uncertainty in the mesoscopic system make it an interesting topic for researchers to devote to.

3.2 Single Electron Devices

As described in the section 1.1, nanometer scale devices are interested to numerous researchers in various fields; so many different kinds of device are fabricated with dissimilar operation principles. Depends on the dimensions of the device (0D, 1D, 2D or 3D), the density of state of the device has dramatically changed [3]. Here we only focus on the devices structures that have a small island between two tunneling barriers. The extent of the electrons in the island defines three basic categories of solid-state nanoelectronic devices [4].

- Quantum Dots (QD’s or “artificial atoms”) [5].

Island confines electrons with zero classical degrees of freedom remaining.

- Resonant Tunneling Devices (RTD’s) [6].

Island confines electrons with one or two classical degrees of freedom.

- Single-Electron Transistors (SET’s) [7].

Island confines electrons with three classical degrees of freedom

Figure 3.1 [8] shows the basic idea of device structure. Figures of band diagram and theoretical Is-Vd curve for devices just discussed above are given in Fig 3.2. SET’s characteristic current-voltage curves are displayed in Figure 3.3 [9], and Figure 3.4. Here, we showed many pioneer’s great works in Fig. 3.5 to Fig 3.9 [10,11,12].

3.2.1 Depletion Gate Single Electron Device

Our efforts are mainly on the single electron device. We start to analyze our device with the theory of single electron transistor. The basic ideas of SET are quantum confinement in the island between two tunnel barriers. When the charging energy in the system is larger than quantum uncertainty, coulomb blockade phenomena will be discovered. Detailed theories about SET can read reference [7,9,13,14].

Based on the process we developed in Chapter 2, we fabricated a device operated like SET. We use the depletion gate concept [15] to make a five terminal (bottom gate, side gate, control gate, source, and drain) device (Device diameters are given in Table 3.1). With the interaction among Vbg (bottom gate), Vsg (side gate), and Vg (control gate), we created an island and two tunneling barriers. Device’s structure is present on Figure 3.10, AFM images are given in 2.7, and measured IV curves are showed from Figure 3.11 to Figure 3.22.

Some quantities about quantum effects are given in Table 3.2.

Although the categories of single island device descried above are specified clearly, till now, devices can’t be fabricated just meet one of the objects. We can see that device’s

characteristics are transient among three basic categories.

First, we see Figure 3.11, and Figure 3.12. The device D5 works properly with the theoretical SET’s characteristic Id-Vd and Id-Vg curves. And in Figure 3.13, and Figure 3.14, the device C5 presents resonance tunnel devices’ (RTD) current-voltage relationship.

This may due to the electron’s Fermi wavelength in silicon become longer with lowering temperature (Compare with the same device C5 measured at different temperature). Longer wavelength changed the island dimension seen by electron, for example, from three dimensions to two or one dimension. The Id-Vd’s behavior may be explained by quantum well module. The maximum likelihood to describe electron’s behavior is standing wave like.

The quantized energy levels correspond to the peak transition current. Gate voltage gives the different potential energy in the island, so we see the similar behavior of periodic oscillation current and voltage relationship.

Second, refer to Figure 3.15, and Figure 3.16, both Id-Vd and Id-Vg curves showed staircase. The origin of formation staircase Id-Vd curve is due to the asymmetry resistance of two tunneling barriers. The reason of Id-Vd showed staircase is that control gate Vg not only influent the electron potential in the island but also the number of electrons. Unlike the current is limited by electron tunneling rate of tunneling junction between island and source (Jis), with higher temperature, the tunneling junction has higher tunneling rate (the tunneling rate relates to temperature with the fact exp(-1/kT)). The current now is not limited by tunneling rate of junction Jis but the number of electrons in the island. As the result, we can observed the quantization Id-Vg behavior, each step imply one more electron participated. Based on the Id-Vg curve measured in this experiment, we can calculate the average electron mobility of our system. We find our devices have the mobility around 20500 cm²/V-s at 30 K and 11500 cm²/V-s at 60 K. Our device is phosphorous doped (5*10¹⁵ cm^-3). This result falls in a reasonable range (see Figure 3.23 [16]).

Third, Figure 3.17 to Figure 3.21 showed us another Id-Vg pictures. We suppose that there exist a leakage path from drain to source. This assumption is reasonable, since with increasing control gate voltage, the accumulation region become more and more wider.

Above certain voltage, the accumulation region is wider than depletion region caused by side gate and the tunneling barriers disappeared near control gate (see Figure 3.24). It means that, there exist another path (MOSFET like) for current flow between source and drain. When the effective resistance seen by electron is higher than 25.6 MΩ, the electron confinement phenomenon is still can be observed. As a result, our device at this category performed like a SET parallel with a MOSFET. The periodic oscillation is SET’s characteristics and the increasing current is due to the conducting of parallel MOSFET.

3.2.2 Discussions of Depletion Gate Single Electron Device

After qualitative discusses our device in previous section, we try to describe it in more quantitative way. We start at compare parameters extracting from theoretic calculated (first order approximation) by device dimensions and measured IV curves. We find Cg is at a deviation of 50% (2.42 aF v.s. 5 aF), which is still at an acceptable range, but there exist obvious difference in Cd (5.9 aF v.s. 35.6 aF), more detailed data are given in Table 3.4. In addition, the parameter we extract from measurement shows that we measured the device at a condition out of the device’s operation widow. This is unreasonable. This factor implies using the theory for SET to describe our device is not suitable. The oscillation caused in sweep Vd should not be contributed to single electron charging effect but quantized states in the quantum dot. We use the particle in a box model to estimate the dot dimension, and we find the island is at the size about 20 nm. This result agrees to our control gate dimension (60 nm). Father more, we can see the size of the island is about the half electron’s de Broglie wavelength in the low temperature (refer to Table 3.2), this convinced

that the characteristics we measured are something meaningful. By including the information about the QD size, we re-calculate the Cd and combine measured Cg to get the charging energy and operation window for our device. It shows a self-consistent result. All discussions in previous section are still the same except that the charging energy needs to be replaced by quantized energy level. We try to find the staircase in our device C5 caused by charging energy in the Id-Vd curve but in vain (can refer to Figure 3.25). This may due to there doesn’t exist significant difference in the depletion junction Jis and Jid. Some associated data can be found in Table 3.5.

3.3 Measurement Issues of Single Electron Device

3.3.1 Material Preparation

As we can see in Section 3.2, drain current of single electron device is relative small to traditional MOS device. The current level is at the range at the pico to micron ampere. For device isolation requirement, silicon on insulator substrate is desired. From reference [17], we know the resistivity of thermal oxide is at the range of 10¹²-10¹⁶ Ω-cm (applied field depedent), contact pad dimension of our device is 100 um * 100 um. The allowed leakage current level is about 1 pA at Vd = 2 V. That is, at the worst case, the required buried oxide thickness of the SOI wafer is 2000 nm. At the beginning of our experiment, we use Uni-bond SOI wafer and get some results. But when the wafer is spent, we change to use the SIMOX SOI wafer, and find the leakage current is too huge to achieve single electron device. As a result, most of our proposed structures presented in Chapter 2, cannot be analyzed in this theses. Material preparation is very important.

3.3.2 Ohmic Contact

We cannot observe Coulomb blockade behavior near Vd ~ 0V (Figure 3.3), because our device use aluminum as contact metal, it forms schottky barrier with silicon. If we change the contact metal from Al to Pt or W, the schottky contact can be improved. At the moment, we can observe Coulomb blockade behavior near Vd ~ 0V, electron transport in negative drain bias, hole transport in positive drain bias. It will provide more data to analysis carrier transport phenomena. But as mentioned in 3.3.1, our efforts are all in vain due to the SIMOX SOI leakage.

3.3.3 Sweeping Method

When we sweep drain voltage, we should sweep from zero voltage to positive voltage and from zero voltage to negative voltage (two steps) instead sweep Vd from negative voltage to positive voltage (one step) or vice versa. Because measurement system itself also has resistors, capacitors components will cause RC time delay during measurement. When sweeping drain voltage from positive to negative voltage (or vice versa), we can observe that at Vd = 0 V, the drain current is not close to the zero level of the system (For example, in HP 4155 system, the zero level is about several fA), but some orders larger (see Figure 3.26). The current may at the range of several pA to uA, depends on device structure. This is not a series issue to traditional MOS structure, but when referring to single electron device, it really is a big problem. It makes a false signal at the zero drain bias condition, but this condition is a key point to observe coulomb blockade behavior. Also, when sweeping drain voltage, SOI substrate should be set a value (i.e. zero) to avoid undeserved charging effect at the BOX surfaces (between SOI layer or substrate). The charging and de-charging effect will affect measurement results (so called floating body effect, see ref. 18 and compare Figure 3.26 and Figure 3.27). On the other hand this imperfect phenomenon should be take into consideration when we sweep bottom gate voltage (body voltage, see

Figure 3.28). Same measurement principle should be obeyed in order to obtain more exact device characteristics.

Time setting is also an issue in the measurement. As discussed above, charging and de-charging effect in SOI has significant influence to the device, we should delay the time interval between two measurements to obtain effective results. Also, in order to obtain meaningful results, voltage step in sweep mode should as small as possible, and long integral time is required to eliminate noise in the system.

3.4 Design Issues of Single Electron Device

3.4.1 Room Temperature Operation

Many researchers want to solve this issue by making structure small (i.e. smaller tunneling junction region make smaller capacitance). This is theoretically right, but there still have the other restriction. If we want to see single electron transport phenomenon, we must let the device driving in tunneling limited but drift limited. But refer to Figure 3.23, we see electron mobility at room temperature is quit lower compared to which in the low temperature. It means the current we want to measure is quite small ~ about 0.5 pA, which is really a big challenge. We can refer to our device C5’s performance above 50 K, the

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