Chapter 3 Device Characteristics
3.4 Design Issues of Single Electron Device
3.4.5 Single Crystal Island
Single electron tunneling process is hard to observe in semiconductor material. Because single crystal island is hard to fabricated in semiconductor material than metal, co-tunneling cannot be avoided in such condition. But on the other hand, quantum effect is difficult to see in metal due to shorter Fermi wavelength (at the length near few angstroms about one to two order shorter than that in the semiconductor). Usually, metal dot is fabricated from bottom up (i.e. Figure 2.3), and semiconductor islands are formed from top down method.
Despite what material we choose, we will face the challenge in production technique whether in size control or single crystal island formation.
According to the discussions above, we can conclude that to “optimize” a silicon based single electron device is very difficult due to some conflicts. To avoid some problems we may face, using molecular to replace to the island and two tunneling junctions is the most suitable way. Since molecular are well defined object, with highly consist properties and dimensions between one to another.
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With traditional MOSFET scale down to tens of nanometer diameter, the leakage current due to thin gate oxide and short channel effect may led the off current too large to integrate circuits applications. Single electron transistor has been proposed at 1986, but it faces so many problems (part are discussed just above). The combination of fabrication method both from bottom up (self-assembly molecular) and top down to achieve nanometer scale device are widely surveyed nearby. Single molecular transistor is one of possible solutions. Using our fabrication method with proper over etching may provide a base structure for SMT.
This may be achieved in our future work.
Chapter 3 References
1. G. Bergamn. Phys. Rep. 107, 3 (1984) 2. A. D. Stone, phys. Rev. Lett 56, 2692 (1985)
3. C. Kittel, “Introduction to Solid State Physics”, Chapter 5, pp. 131–145. John Wiley &
Sons. 7th ed. (1996)
4. D. G. Gordon, M. S. Montemerlo, J .C. Love, G. J. Opiteck, and J. C. Ellenbogen.
Proceeding of the IEEE, Vol. 85, No. 4 (1997)
5. M. A. Reed, “Quantum dots,” Sci. Amer., pp. 118 – 123, Jan. (1993) 6. J. N. Randall, Nanotechnology 4, pp. 41-48 (1993)
7. K. K. Likharev, “SET: Coulomb Blockade Devices,” Nano et Micro Technologies 3 (2003)
8. K. K. Likharev, Proceeding of the IEEE, Vol. 87, No. 4 (1997) 9. J. R. Tucker, J. Appl. Phys. 79, pp. 4399-4413 (1992)
10. M. A. Kastner. Review of Modern Physics, Vol. 64, pp. 849-858 (1992)
11. T. Altebaeumer, S. Amakawa, and H. Ahmed. J. Appl. Phys. Vol. 94, No.5 pp.3194-3120 (2003)
12. D. H. Kim, S. K. Sung, K. R. Kim, J. D. Lee, and B. G. Park, J. Vac. Sci. Technol. B 20.
(2002)
13. D. K. Ferry, and S. M. Goodnick. “Transport in nanostructures”, Cambridge University Press (1997)
14. C. Washuber. “Computational Single-Electronics”, Springer-Verlag Wien (2001) 15. H. Matsuoka and S. Kimra. Appl. Phys. Lett. Vol. 66, pp. 613-615 (1995)
16. C. Jacoboni, C. Canali, G. Ottaviani, and A. A. Quaranta, Solid State Electron., 20, 77 (1977)
17. W. R. Runyan and K. E. Bean. ”Semiconductor integrated circuit processing technology.” Addison-Wesley (1990)
18. S. Krishnan and J. G. Fossum, IEEE CIRCUIT & DEVICES, pp. 32-37, July (1998)
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Table 3.2 REFERENCE QUANTITIES
Doping Desity (cm-3) 5*1015
Table 3.3 PREDICTION OF ELECTRON MOBILITY IN THE EXPERIMENT
C5_30K D5_60K
Vds 1.5 0.8
drift_Id (A) 2E-11 5E-12
Mobility (cm2/V․s) 20500 11160
Table 3.4 DEVICE PARAMETERS
Table 3.5 DEVICE PARAMETERS (MODIFIED)
C5 D5 C5_20K C5_30K D5_60K
Ccg (aF) εSiO2 *W*H/gl 2.42 2.90 5 3.56 5.33 Cd (aF) εSi*W*H /(Sw-QD)/2 6.70 4.94 6.70 6.70 4.90 Ctot (aF) 2*Csg + Ccg 15.82 12.78 18.40 16.96 15.13 Delt Vd (mV) e/Cd 23.87 32.37 23.88 23.88 32.00 ChrE (meV) e2/(Ctot*2) 5.06 6.26 4.35 4.72 5.29 Opr Tmp (K) ChrE / k 58.80 72.77 50.56 54.86 61.47
C5 D5 C5_20K C5_30K D5_16K
Ccg (aF) εSiO2 *W*H/gl 2.42 2.90 5 3.56 5.33 Cd (aF) εSi*W*H/(Sw/2) 5.9 4.42 35.56 35.56 40 Ctot (aF) 2*Csg + Ccg 14.21 11.75 77.04 74.67 85.93
Delt Vd (mV) e/Cd 27.13 36.17 4.50 4.50 4
Delt Vg (mV) e/Ccg 66.22 55.19 32 45 30
ChrE (meV) e2/(Ctot*2) 5.63 6.81 1.05 1.07 0.76
Opr Tmp (K) 65.46 79.20 12.22 12.46 10.90
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Figure 3.1 Schema of Single Electron Transistor [8]
Figure 3.2 Id-Vd curves for three categories of solid-state nanoelectronic devices [4]
Figure 3.3 SET’s Theoretical Id-Vd Curve [9]
Figure 3.4 SET’s Theoretical Id-Vg Curve
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Figure 3.5 (a) Depletion Gate SET and (b) its Id-Vg curve [10]
Figure 3.6 (a) Point Contact SET and its (b) Id-Vd and (c) Id-Vg curves [11]
Figure 3.7 (a) Schema of Depletion Gate SET and its (b) Equilibrium Circuits [13]
Figure 3.8 SEM images for SET with Different Island Diameter [13]
Figure 3.9 Depletion Gate SET’s Id-Vg Curve Measured at Different Conditions [13]
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Figure 3.10 Schema of depletion gate device in this experiment
-2.022 -2.026 -2.030 -2.034
-35.0 -35.5 -36.0 -36.5 -37.0 -37.5 -38.0
Id (pA )
Vd (V)
Id-Vd curve for device D5 Measure at 16 K, Vsg = -4 V, Vg = 1.2 V, and Vbg = 2 V
Figure 3.11 Id-Vd measure at 16 K, Vsg = -4, Vg = 1.2 V, and Vbg = 2 V (D5)
1.107 1.134 1.161 1.188
Id-Vg Curve for Device D5 Measure at 16K, Vsg= -4 V, Vd= -2 V, and Vbg= 2 V
Id (pA)
Vg (V)
Figure 3.12 Id-Vg measure at 16 K, Vsg = -4 V, Vd= -2 V, and Vbg= 2 V (D5)
-2.032 -2.041 -2.050 -2.059 -2.068
-28 -32 -36 -40
Id-Vd Curve for Device C5 Measured at 20 K, Vsg= -4 V, Vbg= 2 V, and Vg= 1.2 V
Id (pA )
Vd (V)
Figure 3.13 Id-Vd measured at 20 K, Vsg = -4 V, Vbg = 2 V, and Vg = 1.2 V (C5)
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Id-Vg Curve for Device C5 Measured at 20 K, Vsg= -4 V,
Id-Vd Curve for Device C5 Measured at 30 K, Vsg= -4 V, Vbg = 2V, and Vg = 1.2V
Id (nA )
Vd (V)
Figure 3.15 Id-Vd measured at 30 K, Vsg = -4 V, Vbg = 2 V, and Vg = 1.2 V (C5)
1.265 1.310 1.355 1.400
Id-Vg Curve for Device C5 Measured at 30 K, Vsg = -4 V,
Id-Vd Curve for Device D5 Measured at 68 K, Vbg = 0 V, Vsg = -4 V, and Vg = 1.9 V
Figure 3.17 Id-Vd measured at 68 K, Vbg = 0 V, Vsg = -4 V, and Vg = 1.9 V (D5)
46
1.80 1.85 1.90 1.95 2.00
-2
Figure 3.18 Id-Vg measured at 60K, Vds= -0.8V, Vsg= -4V, Vbg= 1.5V (D5)
1.90 1.92 1.94 1.96 1.98 2.00
-10
Id-Vg Curve for Device D5 Measured at 65 K, Vds = -0.8 V, Vsg = -4 V, Vbg = 1.5 V
Figure 3.19 Id-Vg measured at 65 K, Vds = -0.8 V, Vsg = -4 V, Vbg = 1.5V (D5)
1.90 1.92 1.94 1.96 1.98 2.00
Id-Vg Curve for Device D5
Measured at 66 K, Vds = -0.8 V,
Id-Vd Curve for Device C5
Measured at 50 K, Vcg = 1.2 V, Vsg = 4 V, Vbg = -2V
Id (pA)
Vd (V)
Figure 3.21 Id-Vd measured at 50 K, Vcg = 1.2 V, Vsg= -4 V, and Vbg = -2V (C5)
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-1.26 -1.40 -1.54 -1.68 -1.82 -1.96
0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2
Id-Vd Curve for Device C5 Measured at 70 K, Vcg = 1.2 V, Vsg = -4 V, Vbg = -2V
Id (nA)
Vd (V)
Figure 3.22 Id-Vd measured at 50 K, Vcg = 1.2 V, Vsg= -4 V, and Vbg = -2V (C5)
Figure 3.23 Mobility of electrons and holes in Si as a function of temperature. [16]
Figure 3.24 Schema of depletion gate device with leakage path in this experiment
-1.0 -1.2 -1.4 -1.6 -1.8 -2.0
-0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8
Id (nA)
Vd (V)
Id - Vd Curve for Device C5 Measured at 30 K, Vsg = -4 V, Vg = 1.2V, and Vbg = 2V
Figure 3.25 Id-Vg curve measured at 30 K, Vsg = -4 V, Vg = 1.2 V, and Vbg = 2V.
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0.9 Three terminal device on SOI with source biased at 0 V, and Vg at 0 V measured at Vd = 0 V is 40 nA. Interval between two measurements is 20 s. These two measurements show highly reliability.
-3 -2 -1 0 1 2 3
Three terminal device on SOI with source biased at 0 V, and floating body
Id (mA )
Vd (V)
1st sweep 2nd sweep
Figure 3.27 Id-Vd curve measured by sweeping Vd from –3 V to 3 V with floating body. Interval between two measurements is 20 s. These two
measurements show the floating body effect.
-3 -2 -1 0 1 2 3 -20
-15 -10 -5 0 5 10
Three terminal device with drain biased at 2 V and source biased at 0 V
Id ( n A)
Vg (V)
one step sweep two step sweep
Figure 3.28 Id-Vg curves measured by sweeping Vg from 0 V to –3 V and 0 V to 3 V (two step sweep), and sweeping Vg from –3 V to 3 V. Two
measurements show different results due to charging effect.
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