Chapter 2 Device Fabrication
2.5 Contact Formation
2.5.1: Define Contact Plug with Mask 2 (without P/R remove)
Since passivation is not necessary in the experiment, we didn’t remove photo resist immediately after contact plug formation to avoid Al diffuse into silicon. Photo resist is removed after step 2.5.4.
2.5.3: Coating Aluminum with Thermal Coater 2.5.4: Define Contact Pad with Mask 3
2.5.5 Al sintering
The full schema of process flow is given in Figure 2.6. The AFM pictures of our devices are displayed in Figure 2.7 to Figure 2.11, SEM images are given in Figure 2.12.
Figure 2.7 shows single electron transistor structures, associated properties are given in section 3.2. Figure 2.8 shows the schema of bio detector device, details will be described in section 3.3. Structure in Figure 2.9 is designed to see how the influence of the corner in the nano-scale devices. We want to tell if the back scattering is a dominant factor in such device (particle behavior) or the current is a dependent issue to the field we applied in drain
(wave like). Figure 2.10 shows the idea about quantum influence [6] device. Due to the wave property of the electron, we wish to discover the influence behavior by measuring source-drain current with sweeping control gate voltage. Figure 2.11 displays the prototype of point contact device, some properties of point contact device can be find in reference [7]
and [8]. SEM images in Figure 2.12 confines our ability in both device structure and dimension control.
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Chapter 2 References
1. J. C. Love, Scientific American, pp39-47. (2001)
2. D. H. Kim, S. K. Sung, K. R. Kim, J. D. Lee, and B. G. Park, J. Vac. Sci. Technol. B 20.
(2002)
3. Y. C. Liao, S. Y. Lin and S. C. Lee, "Spherical SiGe Quantum Dots Prepared by Thermal Evaporation Method", Appl. Phys. Lett., 77, pp. 4328-4329. (2000)
4. Y. Ono, Y.Takahashi, K. Yamazaki, M. Nagasw, H. Namatusu, K. Murase, IEDM 99-367. (1999)
5. M. A. Reed, Appl. Phys. Lett. 67. (1995)
6. Y. Aharnov and D. Bohm. Phys. Rev. 115, 485 (1959)
7. H. Ishikuro and T. Hiramoto. Appl. Phys. Lett., 74, pp. 1126-1128. (1999)
8. Y. T. Tan, T.Kaymiya, Z. A. K. Durrani, and H. Ahmed. J. Appl. Phys. 94, pp. 633-37.
(2003)
Figure 2.1 Schema of nano-imprinting method
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Figure 2.2 E-beam lithography plus reactive ion etching
Figure 2.3 Schema of two-angle evaporation method
Figure 2.4 Schema of vertical pattern-dependent oxidation (V-PADOX) method
Figure 2.5 Schema of break junction method
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Figure 2.6 Process Flow
(a) (b)
(c) (d)
(e)
(a)
(b)
(c) Figure 2.7 AFM image of SET device
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(a)
(b) Figure 2.8 AFM image of bio detector device
Figure 2.9 AFM image of scattering influence device
Figure 2.10 AFM image of quantum influence device
Figure 2.11 AFM image of point contact device
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Figure 2.12 SEM images
Chapter 3
Experiment 2 – Device Characteristics
3.1 Mesoscopic Phenomena
When devices scale down to the size comparable with the electron’s Fermi wavelength of its composed material (i.e. The Fermi wavelength in metal is at the scale about 1 nm, but in semiconductors is about 10 to 100 nm), we called such a system a mesoscopic system.
Such system is at a transparency state between macroscopic (bulk material property) and microscopic (atomic level consideration) system. The number of atoms in the system is not large enough for us to apply the statistics to describe it precisely, but is still too huge for us analyzed it with quantum mechanism from bottom up. Weak localization [1] and universal conductance fluctuation [2] are two major characteristics when we describe such a system.
The variety and uncertainty in the mesoscopic system make it an interesting topic for researchers to devote to.
3.2 Single Electron Devices
As described in the section 1.1, nanometer scale devices are interested to numerous researchers in various fields; so many different kinds of device are fabricated with dissimilar operation principles. Depends on the dimensions of the device (0D, 1D, 2D or 3D), the density of state of the device has dramatically changed [3]. Here we only focus on the devices structures that have a small island between two tunneling barriers. The extent of the electrons in the island defines three basic categories of solid-state nanoelectronic devices [4].
- Quantum Dots (QD’s or “artificial atoms”) [5].
Island confines electrons with zero classical degrees of freedom remaining.
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- Resonant Tunneling Devices (RTD’s) [6].
Island confines electrons with one or two classical degrees of freedom.
- Single-Electron Transistors (SET’s) [7].
Island confines electrons with three classical degrees of freedom
Figure 3.1 [8] shows the basic idea of device structure. Figures of band diagram and theoretical Is-Vd curve for devices just discussed above are given in Fig 3.2. SET’s characteristic current-voltage curves are displayed in Figure 3.3 [9], and Figure 3.4. Here, we showed many pioneer’s great works in Fig. 3.5 to Fig 3.9 [10,11,12].
3.2.1 Depletion Gate Single Electron Device
Our efforts are mainly on the single electron device. We start to analyze our device with the theory of single electron transistor. The basic ideas of SET are quantum confinement in the island between two tunnel barriers. When the charging energy in the system is larger than quantum uncertainty, coulomb blockade phenomena will be discovered. Detailed theories about SET can read reference [7,9,13,14].
Based on the process we developed in Chapter 2, we fabricated a device operated like SET. We use the depletion gate concept [15] to make a five terminal (bottom gate, side gate, control gate, source, and drain) device (Device diameters are given in Table 3.1). With the interaction among Vbg (bottom gate), Vsg (side gate), and Vg (control gate), we created an island and two tunneling barriers. Device’s structure is present on Figure 3.10, AFM images are given in 2.7, and measured IV curves are showed from Figure 3.11 to Figure 3.22.
Some quantities about quantum effects are given in Table 3.2.
Although the categories of single island device descried above are specified clearly, till now, devices can’t be fabricated just meet one of the objects. We can see that device’s
characteristics are transient among three basic categories.
First, we see Figure 3.11, and Figure 3.12. The device D5 works properly with the theoretical SET’s characteristic Id-Vd and Id-Vg curves. And in Figure 3.13, and Figure 3.14, the device C5 presents resonance tunnel devices’ (RTD) current-voltage relationship.
This may due to the electron’s Fermi wavelength in silicon become longer with lowering temperature (Compare with the same device C5 measured at different temperature). Longer wavelength changed the island dimension seen by electron, for example, from three dimensions to two or one dimension. The Id-Vd’s behavior may be explained by quantum well module. The maximum likelihood to describe electron’s behavior is standing wave like.
The quantized energy levels correspond to the peak transition current. Gate voltage gives the different potential energy in the island, so we see the similar behavior of periodic oscillation current and voltage relationship.
Second, refer to Figure 3.15, and Figure 3.16, both Id-Vd and Id-Vg curves showed staircase. The origin of formation staircase Id-Vd curve is due to the asymmetry resistance of two tunneling barriers. The reason of Id-Vd showed staircase is that control gate Vg not only influent the electron potential in the island but also the number of electrons. Unlike the current is limited by electron tunneling rate of tunneling junction between island and source (Jis), with higher temperature, the tunneling junction has higher tunneling rate (the tunneling rate relates to temperature with the fact exp(-1/kT)). The current now is not limited by tunneling rate of junction Jis but the number of electrons in the island. As the result, we can observed the quantization Id-Vg behavior, each step imply one more electron participated. Based on the Id-Vg curve measured in this experiment, we can calculate the average electron mobility of our system. We find our devices have the mobility around 20500 cm2/V-s at 30 K and 11500 cm2/V-s at 60 K. Our device is phosphorous doped (5*1015 cm-3). This result falls in a reasonable range (see Figure 3.23 [16]).
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Third, Figure 3.17 to Figure 3.21 showed us another Id-Vg pictures. We suppose that there exist a leakage path from drain to source. This assumption is reasonable, since with increasing control gate voltage, the accumulation region become more and more wider.
Above certain voltage, the accumulation region is wider than depletion region caused by side gate and the tunneling barriers disappeared near control gate (see Figure 3.24). It means that, there exist another path (MOSFET like) for current flow between source and drain. When the effective resistance seen by electron is higher than 25.6 MΩ, the electron confinement phenomenon is still can be observed. As a result, our device at this category performed like a SET parallel with a MOSFET. The periodic oscillation is SET’s characteristics and the increasing current is due to the conducting of parallel MOSFET.
3.2.2 Discussions of Depletion Gate Single Electron Device
After qualitative discusses our device in previous section, we try to describe it in more quantitative way. We start at compare parameters extracting from theoretic calculated (first order approximation) by device dimensions and measured IV curves. We find Cg is at a deviation of 50% (2.42 aF v.s. 5 aF), which is still at an acceptable range, but there exist obvious difference in Cd (5.9 aF v.s. 35.6 aF), more detailed data are given in Table 3.4. In addition, the parameter we extract from measurement shows that we measured the device at a condition out of the device’s operation widow. This is unreasonable. This factor implies using the theory for SET to describe our device is not suitable. The oscillation caused in sweep Vd should not be contributed to single electron charging effect but quantized states in the quantum dot. We use the particle in a box model to estimate the dot dimension, and we find the island is at the size about 20 nm. This result agrees to our control gate dimension (60 nm). Father more, we can see the size of the island is about the half electron’s de Broglie wavelength in the low temperature (refer to Table 3.2), this convinced
that the characteristics we measured are something meaningful. By including the information about the QD size, we re-calculate the Cd and combine measured Cg to get the charging energy and operation window for our device. It shows a self-consistent result. All discussions in previous section are still the same except that the charging energy needs to be replaced by quantized energy level. We try to find the staircase in our device C5 caused by charging energy in the Id-Vd curve but in vain (can refer to Figure 3.25). This may due to there doesn’t exist significant difference in the depletion junction Jis and Jid. Some associated data can be found in Table 3.5.
3.3 Measurement Issues of Single Electron Device
3.3.1 Material Preparation
As we can see in Section 3.2, drain current of single electron device is relative small to traditional MOS device. The current level is at the range at the pico to micron ampere. For device isolation requirement, silicon on insulator substrate is desired. From reference [17], we know the resistivity of thermal oxide is at the range of 1012-1016 Ω-cm (applied field depedent), contact pad dimension of our device is 100 um * 100 um. The allowed leakage current level is about 1 pA at Vd = 2 V. That is, at the worst case, the required buried oxide thickness of the SOI wafer is 2000 nm. At the beginning of our experiment, we use Uni-bond SOI wafer and get some results. But when the wafer is spent, we change to use the SIMOX SOI wafer, and find the leakage current is too huge to achieve single electron device. As a result, most of our proposed structures presented in Chapter 2, cannot be analyzed in this theses. Material preparation is very important.
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3.3.2 Ohmic Contact
We cannot observe Coulomb blockade behavior near Vd ~ 0V (Figure 3.3), because our device use aluminum as contact metal, it forms schottky barrier with silicon. If we change the contact metal from Al to Pt or W, the schottky contact can be improved. At the moment, we can observe Coulomb blockade behavior near Vd ~ 0V, electron transport in negative drain bias, hole transport in positive drain bias. It will provide more data to analysis carrier transport phenomena. But as mentioned in 3.3.1, our efforts are all in vain due to the SIMOX SOI leakage.
3.3.3 Sweeping Method
When we sweep drain voltage, we should sweep from zero voltage to positive voltage and from zero voltage to negative voltage (two steps) instead sweep Vd from negative voltage to positive voltage (one step) or vice versa. Because measurement system itself also has resistors, capacitors components will cause RC time delay during measurement. When sweeping drain voltage from positive to negative voltage (or vice versa), we can observe that at Vd = 0 V, the drain current is not close to the zero level of the system (For example, in HP 4155 system, the zero level is about several fA), but some orders larger (see Figure 3.26). The current may at the range of several pA to uA, depends on device structure. This is not a series issue to traditional MOS structure, but when referring to single electron device, it really is a big problem. It makes a false signal at the zero drain bias condition, but this condition is a key point to observe coulomb blockade behavior. Also, when sweeping drain voltage, SOI substrate should be set a value (i.e. zero) to avoid undeserved charging effect at the BOX surfaces (between SOI layer or substrate). The charging and de-charging effect will affect measurement results (so called floating body effect, see ref. 18 and compare Figure 3.26 and Figure 3.27). On the other hand this imperfect phenomenon should be take into consideration when we sweep bottom gate voltage (body voltage, see
Figure 3.28). Same measurement principle should be obeyed in order to obtain more exact device characteristics.
Time setting is also an issue in the measurement. As discussed above, charging and de-charging effect in SOI has significant influence to the device, we should delay the time interval between two measurements to obtain effective results. Also, in order to obtain meaningful results, voltage step in sweep mode should as small as possible, and long integral time is required to eliminate noise in the system.
3.4 Design Issues of Single Electron Device
3.4.1 Room Temperature Operation
Many researchers want to solve this issue by making structure small (i.e. smaller tunneling junction region make smaller capacitance). This is theoretically right, but there still have the other restriction. If we want to see single electron transport phenomenon, we must let the device driving in tunneling limited but drift limited. But refer to Figure 3.23, we see electron mobility at room temperature is quit lower compared to which in the low temperature. It means the current we want to measure is quite small ~ about 0.5 pA, which is really a big challenge. We can refer to our device C5’s performance above 50 K, the Id-Vd curve have smell out and hard to observe SET’s characteristic Id-Vd curve.
Quantitative speaking, ΔVd = e / Cd, we wish ΔVd is as larger as possible for circuit design. And Cd∝ (junction and dot contact area) / (junction length). It means that we should product a junction with small junction and dot contact area and longer junction length. Prior requirement is fabrication limited, and later one is physically limited (Tunneling probability is inversely proportional to junction length). Afterwards, if we really
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produce such device, the current we can measured will be very small because electron tunneling rate is positive proportional to Cd. We cannot obtain both largeΔVd and ΔId at the same time.
3.4.2 Random Background Charge Problem [7]
If an impurity is trapped in the insulation environment, the impurity will polarize the island, creating a polarization charge of the order a/r, where ‘r’ is the distance from the impurity to the island, and ‘a’ is the diameter of the island. This charge affects all the characteristics of the single electron transistor.
3.4.3 Universal Conductance Fluctuation at Low Temperature
Considering the island with the scale about 10 nm*10 nm*10 nm (10-16 cm3), and the doping density of the device is 1017 cm-3. We can calculate that the number of dopants (N) in the island is about 10, and the fluctuation of the device is about N-1/2. Which means the device-to-device variation can be as large as 50 percent. And the positions of the dopants give the different current voltage characteristics due to the universal conductance variation.
This phenomenon can also be observed at low temperature. Since at low temperature (freeze out region), the material tend to have the same property as intrinsic ionization rather than doping dependence. But generation-recombination process is occurred all the time.
Thermal statistics tells us the average behavior but the exact situation at certain place and moment. On the other hand, when our device is measured at low temperature, we cannot tell the precise situation about the island properly. Each time the island formed by our manipulating control gate and side gate, it has different inner condition (i.e. the number of electrons in the island is unknown and in variation). Figure 3.12 and Figure 3.22 can assert this assumption. The characteristic I-V curve has the same properties (oscillation and increasing), but the exact relationships are different.
3.4.4 Universal Conductance Fluctuation at Room Temperature
As discussed in 3.3.3, to reduce the non-uniform device operation property due to the variation of dopants in the island, we will wish increase the doping density in the device.
But, higher doping density means higher impurity in the device (For example, for a boron doped device, with more boron in the lattice site caused more silicon in the interstitial site), and the device will tend to be poly-Si like than single crystalline structure. Every grain boundary exists in the island will change the electron transport property of the device.
However, if we use intrinsic silicon, the peripheral resistance near the island will become very large. This will shift the device’s characteristic from tunneling domination (single electron device like) to drift domination (Resistor like).
3.4.5 Single Crystal Island
Single electron tunneling process is hard to observe in semiconductor material. Because single crystal island is hard to fabricated in semiconductor material than metal, co-tunneling cannot be avoided in such condition. But on the other hand, quantum effect is difficult to see in metal due to shorter Fermi wavelength (at the length near few angstroms about one to two order shorter than that in the semiconductor). Usually, metal dot is fabricated from bottom up (i.e. Figure 2.3), and semiconductor islands are formed from top down method.
Despite what material we choose, we will face the challenge in production technique whether in size control or single crystal island formation.
According to the discussions above, we can conclude that to “optimize” a silicon based single electron device is very difficult due to some conflicts. To avoid some problems we may face, using molecular to replace to the island and two tunneling junctions is the most suitable way. Since molecular are well defined object, with highly consist properties and dimensions between one to another.
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With traditional MOSFET scale down to tens of nanometer diameter, the leakage current due to thin gate oxide and short channel effect may led the off current too large to integrate circuits applications. Single electron transistor has been proposed at 1986, but it faces so many problems (part are discussed just above). The combination of fabrication method both from bottom up (self-assembly molecular) and top down to achieve nanometer scale device are widely surveyed nearby. Single molecular transistor is one of possible solutions. Using our fabrication method with proper over etching may provide a base structure for SMT.
This may be achieved in our future work.
Chapter 3 References
1. G. Bergamn. Phys. Rep. 107, 3 (1984) 2. A. D. Stone, phys. Rev. Lett 56, 2692 (1985)
3. C. Kittel, “Introduction to Solid State Physics”, Chapter 5, pp. 131–145. John Wiley &
Sons. 7th ed. (1996)
4. D. G. Gordon, M. S. Montemerlo, J .C. Love, G. J. Opiteck, and J. C. Ellenbogen.
Proceeding of the IEEE, Vol. 85, No. 4 (1997)
5. M. A. Reed, “Quantum dots,” Sci. Amer., pp. 118 – 123, Jan. (1993) 6. J. N. Randall, Nanotechnology 4, pp. 41-48 (1993)
7. K. K. Likharev, “SET: Coulomb Blockade Devices,” Nano et Micro Technologies 3
7. K. K. Likharev, “SET: Coulomb Blockade Devices,” Nano et Micro Technologies 3