Chapter 1 Introduction
1.2 Overview
The main objective of this thesis is to deal with one of important issues in MOSFET noise modeling, it is noise de-embedding. To achieve this goal, detailed information about MOSFET noise in terms of theoretical principle, measurement data and simulation results will be provided. This thesis has been organized into seven chapters as follows:
Chapter 2 gives an introduction to the classification and physical mechanism of noise in MOSFETs. The noise measurement theory and measurement system configuration are also covered. Chapter 3 begins with discussion of as-measured noise parameters and three interesting features identified in this study. In the following, conventional correlation matrix de-embedding method and its usability will be reviewed.
Chapter 4 presents the intrinsic model calibration in terms of I-V characteristics and gate capacitance feature, which were extracted from de-embedded Y-parameters at low frequency.
Key model parameters associated with I-V and C-V in BSIM model are discussed.
Chapter 5 addresses how to build the lossy pad equivalent circuit model associated with various layout structures. The extensive verification on full circuit model will be described.
Good match with the measured extrinsic noise characteristics will be demonstrated. Chapter 6 discusses the equivalent circuit noise de-embedding results in which intrinsic noise performance for sub-100nm MOSFET has been extracted. It helps to identify the truly intrinsic performance of the devices and provide the circuit designers correct guideline for low noise design. Chapter 7 concludes with a summary and suggestions for future work.
Appendices A ~ D provide more detailed explanation of certain contents. Appendix A describes the derivation of noise parameters. Appendix B addresses the Y-factor method for noise figure measurement. Appendix C interprets the noise correlation matrix de-embedding technique. Finally appendix D provides the modified open and short de-embedding method.
Chapter 2 Noise Theory and Noise Measurement Technique
Noise, briefly speaking, can be thought as a kind of signal that is undesirable for a device, circuit, or system. It is generally caused by the fluctuation of voltage or current in an electronic device or component. Noise set the lower limit of measurement or detection which is an important issue for engineering application. In this chapter, noise sources in electronic devices are summarized and high frequency noise in MOSFET, which is dominated by the thermal noise, is focused. Noise theory for noise behavior analysis of two-port network will be covered. Finally, high frequency noise characterization and analysis are provided in the end of the chapter.
2.1 Noise Sources
The most important sources of noise in electronic devices are shot noise, generation-recombination noise, flicker noise and thermal noise. Shot noise is generated when carriers in device cross barriers independently and randomly. It is an eminent noise source for diodes and bipolar transistors. For MOSFETs, only DC gate leakage current contributes shot noise. However, gate leakage is normally controlled to be very small. Generation and recombination noise occurs in semiconductors in which traps and recombination centers are always involved. Fluctuation of carrier number due to random trapping and de-trapping process contributes this noise.
The dominant noise sources of MOSFETs are flicker noise and thermal noise. The origin of flicker noise is generally proposed coming from the carrier number fluctuation due to trapping and de-trapping processes in the Si-SiO2 interface or from mobility fluctuation of device on the basis of empirical results. It is also called, 1/f noise, due to its noise power
spectral density given by (2.1) in which a frequency dependence with slope n approaching unity is achieved
I
( ) I
m
S f K n
= ⋅f (2-1) However, while working in microwave frequency, flicker noise is small compared with thermal noise. Therefore, thermal noise is the main concern for RF CMOS operation.
Nevertheless, for some RF applications such as mixers or oscillators where low frequency signal may be converted up to an intermediate or high frequency, and deteriorate the phase noise and signal-to-noise ratio.
2.1.1 Thermal Noise
Thermal noise is originated from the current fluctuation caused by collision of lattice and carriers by means of random thermal motion. Thermal motion of carriers is ubiquitous in any electronic components as long as its temperature is not absolute zero. Because of the thermal nature, thermal noise power turns out to be exactly proportional to temperature. Starting from the quantum theory of a harmonic oscillator, available noise power of thermal noise is given by [7]
av
P 1
2 ( / ) 1
[ hf kThf ]
hf f
= +e ⋅ ∆
−
(2-2)
where h is Plank’s constant, k is Boltzmann’s constant, f is the operating frequency and ∆f is the frequency interval. For hf/kT << 1 (holds for general case) and based on the noisy resistor model shown in Fig. 2.1, the mean-square open circuit noise voltage and noise current can be obtained.
2
= ∆ =4n
av
P kT f v
R (2-3)
2
= 4 ∆
v
nkTR f
(2-4)2 4
∆ 4
= = ∆
n
i kT f kTG f
R (2-5) Every component with electrical resistivity can be considered as a resistor. With known resistance value or equivalent resistance, noise voltage or noise current can be calculated.
2.1.2 Thermal Noise in MOSFETs
In MOSFETs, noise components include channel noise (or called drain current noise), induced gate noise and thermal noise due to terminal parasitic resistances (Rg, Rd, Rs).
The most broadly accepted noise model for MOSFETs is the van der Zeil model [8]. For a MOSFET under operation, the conducting channel behaves like a voltage-controlled resistor.
This resistor contributes thermal noise at the drain terminal. The power spectral density can be derived from the drain current expression. Refer to Fig. 2.2, taking velocity saturation into consideration, drain current at a certain position along channel direction is given by [7]
D eff I eff eff I D
C
I (x) dV I (x) = W Q (x) (x) = W Q
(x)-E dx
ν ⎛µ ⎞
⋅ ⋅ ⎜ ⋅ ⋅ ⎟⋅
⎝ ⎠
(2-6)
Integrating this current over the effective channel Leff, drain current can be obtained
D S
V D
D V eff eff I
eff C
I
I = 1 W Q (V)- dV
L ⎛⎜µ ⋅ ⋅ E ⎞⎟⋅
⎝ ⎠
∫
(2-7)The mean square values of a current fluctuation ∆i (t)d caused by ∆v(t) in a unit length segment is
2
2 D 2
d 2 eff eff I
eff C
1 I
( i ) = W Q (V)- ( v)
L ⎛µ E ⎞
∆ ⎜ ⋅ ⋅ ⎟ ⋅ ∆
⎝ ⎠
(2-8)
where (∆ν)2 is
2 i
Finally, power spectral density of the noise current generated by the channel resistance includes velocity saturation effect and hot-electron effects is given
D
where Te is the effective electron temperature in which hot-electron effect is considered. This is a general expression for the thermal noise in a channel. For simplicity it can be written as
2
where gd0 is the drain transconductance at VDS is zero. For long channel devices, γ is close to unity in its triode region and decreases to about 2/3 when in saturation (i.e. 2
1 3 ≤ γ ≤ ).
In long channel case, gd0 is equal to the gate transconductance gm in saturation region which leads to a familiar result
2
Due to the carrier heating by the large electric fields in short channel devices, γ may become larger than 2 and even larger.
Besides the channel current noise, the induced gate noise has gained increasing attention.
As the operation frequency increases, contribution of this noise can not be neglected. Noise model including this terms, thus, become essential. Induced gate noise is, as implied by the name, the noise induced by capacitive coupling from channel region to gate terminal due to the fluctuating potential. This noise can be expressed as [9]
2 g
Ig g
S =(i ) =4kT g
f γ
∆
(2-13)
where gg is given by
2 2
gs g
d0
g = C 5g ω
(2-14)
Because the channel noise and induced gate noise have a common origin, they do have correlation. The correlation coefficient is usually expressed as
* g d
2 2
g d
c= i i i i
(2-15)
As for noise contributed from parasitic resistances, they follow (2-5) and are given by
I,Rg I,Rd I,Rs
g d s
4kT 4kT 4kT
S = ; S = ; S =
R R R
(2-16)
Among them, due to the larger sheet resistance of poly-Si, gate resistance (Rg) is typically much larger than drain and source resistance (Rd and Rs). Therefore, Rg is an important noise contributor which can greatly affect the noise figure of the device. Multi-finger gate structure is widely used in RF MOSFET design to reduce Rg. Not only noise behavior, several characteristics are related to Rg too, in which maximum oscillation frequency (fmax) is one of the example. Multi-finger gate gain some performance but pay the penalty of larger parasitic capacitance.
2.2 Two-Port Noise Theory
2.2.1 Noise Figure
As mentioned above, overall noise of a device is generally not from a single origin. It does need a simpler measure of noise performance. For device characterization and circuit
design application, noise figure or noise factor is the most popular expression used. Based on the two-port noisy network model and definition of noise figure, formula of noise parameters can be derived.
Noise factor is defined as the signal-to-noise power ratio at the input to the signal-to-noise power ratio at the output.
i i
o o
F S /N
≡ S /N
(2-17)
From this definition, we can understand that noise factor of a network depicts the degradation of signal-to-noise ratio as signal goes through this network. Considering a network with gain G and noise Na, noise factor then can be express as
a i
i i i i
o o i a i i
N +GN
S /N S /N
F = =
S /N GS /(N +GN ) GN
≡ (2-18)
where Na and G are the noise power and gain of the network. From the expression shown above, noise factor can be defined as the ratio of total noise power at the output to the output noise power which is due to the input noise. In short, the larger noise factor means the noisier of the network. In (2-18), it shows the value of noise factor is affected by the input noise power which is generally from the thermal noise of the source, kT∆f. This means noise factor depends on the source temperature. 290K was adopted as a standard temperature by IEEE because it makes the value of kT close to around 4 × 10-21 Joule. Generally we use this measure in the unit of dB, named noise figure
NF = 10 log F (2-19)
2.2.2 Noise Parameters
Further detail derivation of noise factor based on the noise model with noise sources at the input leads to the following expression [10]
2
n s opt
min
s
R Y -Y F = F +
G
(2-20)
where
s s s
Y = G +j B (2-21)
opt opt opt
Y = G +j B (2-22)
Here Ys is the source admittance, Gs is the real part of Ys, Yopt is the optimum source admittance, and Fmin is the minimum noise factor achieved in the network when the source admittance Ys is equal to Yopt. Rn is named the equivalent noise resistance which indicates how sensitive the noise factor is when Ys differs from Yopt. Replacing the source admittance with its corresponding reflection coefficient at specific characterization impedance Z0, another common form of noise factor is obtained
2 s opt
min n 2 2
0 opt opt
4R Γ -Γ
F = F +
Z (1 Γ− )1+Γ
(2-23)
opt opt
0 opt
1 1-Γ Y =
Z 1 Γ+ (2-24)
s s
0 s
1-Γ Y = 1
Z 1 Γ+ (2-25) This gives us an idea that the noise figure of the network is not only determined by noise source inside but also the source admittance (Ys) driving it. It is also our goal to get the smaller noise factor while keep sufficient gain by varying Ys. The so-called noise parameters are the four parameters Fmin, Rn, Re(Γopt) and Im(Γopt). These parameters are determined purely by the intrinsic noise source of the network, they are unique under a certain operation frequency and bias. Typical dependence of noise figure on source admittance at a fixed
frequency and bias is a 3-D parabolic curve (x-y-z axis: Re(Γopt)-Im(Γopt)-Fmin), Rn is the curvature. Fig. 2.3 and Fig. 2.4 give noise factor plotted with respect to Re(Γopt) and Im(Γopt) with Fmin = 1, Re(Γsopt) = Im(Γsopt) = 0.1 and Rn = 100 and 50 (Ω) respectively. They give a simple idea about the noise figure characteristics.
2.3 Thermal Noise Model
There are two models for channel thermal noise model supported by BSIM3v3.2.2. One is SPICE2 noise model and the other is BSIM3v3 noise model. Noise model flag is defined to invoke different noise model sets [11]:
Noise model selection was done by parameter noimod. Both flicker noise and thermal noise can be calculated using SPICE2 or BSIM3v3 model. Detailed equations for flicker noise are not covered in this thesis and they can be referred to BSIM3v3 manual. Another noise model supported by many simulators is the HSPICE model. In Agilent-ADS simulator, BSIM3 model selected by noimod is valid when NLEV < 1 or HSPICE model will be used according to NLEV values (NLEV=1, 2, or 3). In models mentioned above, velocity saturation and the hot-electron effect model which are considered as two important effects in sub-micron transistors were not included.
SPICE2 Model
For noimod = 1 or 3, thermal noise is calculated according to [12]
8
= 3 ( + + )
Id m ds mbs
S kT g g g
(2-26)
This model is the modification of old HPSICE model shown below as with NLEV < 3, which improves the model accuracy in linear region.
BSIM3v3 Model
If noimod = 2 or 4, thermal noise power spectral density is calculated by [13]
2
4 µ
= eff
Id inv
eff
S kT Q
L
(2-27)
where Qinv is the channel inversion charge calculated according to the capacitance models (capMod=0, 1, 2, or 3).
HSPICE Model
The HSPICE noise model has different equations to calculate the flicker and thermal noises. Equation selection is through a parameter, NLEV. For NLEV smaller than 3, different flicker noise model was used but the same thermal noise equation was implemented which is given by [14]
8 3
= ⋅ m
Id
S kT g
(2-28) which is an old model and is lack of accuracy for modern devices.
If NLEV is set to 3, the noise equation is then given by [13]
8 1 2
3 β + +1
= ⋅ ⋅ − ⋅ ⋅
( ) +
Id GS T
kT a a
S V V Gdsnoi
a (2-29) where
β = eff ⋅µeff ⋅ ox
eff
W C
L (2-30) 1 , Linear region
0 Saturation region
= −
= ,
DS DSAT
a V
V
(2-31)
and Gdsnoi is the thermal noise coefficient with default value equal to 1.
Models mentioned above are integrated into various commercial simulators. Many other models have been proposed to consider velocity saturation effect, hot-electron effect or both [4, 5]. But they are not yet well accepted and verified. Noise simulation result comparison of different models was done in [15]. In this thesis, HSPICE model with NLEV set to 3 was used.
2.4 High Frequency Noise Measurement
In this work, high frequency noise measurement was supported by Radio Frequency Technology Center of National Nano Device Laboratory (NDL RFTC). On-wafer noise characterization was conducted using NP5 series noise parameter measurement system. The measurement system is introduced as follows.
2.4.1 System Configuration [16]
High frequency noise measurement system is mainly composed of a noise figure meter (HP8970B), network analyzer (HP8510), DC power supply (HP4142), a controller unit (NP5B controller), two remote modules (MNS and RRM), and a noise source. Block diagram of system configuration is shown in Fig. 2.5. Port 1 of the system is connected to device-under-test (DUT) by means of a coplanar probe through a mismatch noise source (MNS). MNS is a solid state electronic tuner with a built-in bias-Tee and switching circuit.
Output port (Port 2) of the DUT is followed by a remote receiver module (RRM), which consists of a low noise amplifier (LNA), bias-Tee and switching circuit. The LNA improves noise characterization accuracy by providing a low noise second stage. Noise source is the noise power supply connected at port 1 defined by its ENR (excess noise ratio) value. The ENR expresses the difference in noise power out of the noise source when it is “on” (hot state) and when it is “off” (cold state).
2.4.2 System Calibration and Measurement
As high frequency characterization was conducted on the devices (DUT), the applied signals with short wavelength are comparable to the probe, connecting cables, adapters, bonding wires, and our interested device. Thus, losses caused by the connections will remarkably affect the measurement results, especially critical as measurement frequency increases. On the other hand, a measurement system has its own system error. Consequently, a system calibration should be performed to take those losses into consideration, calibrate the system errors and then shift the measurement signal reference plane to the DUT plane. The validity and accuracy of the calibration results depend on the calibration method used.
For S-parameter measurement, SOLT (short-open-load-through) calibration is a popular method to establish the DUT test plane nowadays. For the noise measurement system, there are several calibration steps required to build a noise measurement plane for DUT. A complete calibration procedure includes input SOL calibration, noise source calibration, network analyzer calibration, thru delay calibration, RRM calibration, MNS calibration and finally system noise parameter calibration. Since calibration details are not our focus, only rough idea is provided here. After the overall calibration procedure, noise contribution of the system will be characterized. Thus, real noise power of DUT can be separated from the noise power contributed from system. This can be verified by connecting the input and output with a known DUT, in our case a dummy “thru” pattern was used to check if the noise figure is less than 0.1dB.
After calibration, noise measurement reference plane is then established. In the beginning of noise parameter characterization, S-parameters measurement at the DUT reference plane should be done first. In the following, by varying the impedance presented to the input of the DUT around the Smith chart, output noise power (sometimes, also refers to noise temperature) of DUT plus the receiver as a function of Γs (source reflection coefficient)
was measured, each Γs and the corresponding noise power constructs a set of equations. The noise parameters are decided by solving the set of equations. Theoretically speaking, only four input states are needed for noise characterization because the noise behavior equation (2-23) has merely four unknown parameters. In practice, however, for the sake of reducing the influence of random errors more than four points were measured (generally 16 states or 20 states) and a proper fitting procedure was used to extract the parameters. Finally, four noise parameters: NFmin, Rn,Re (Γopt) or Re (Yopt) and Im (Γopt) or Im (Yopt) are obtained.
In the measurement process, the overall noise figure was calculated by Y-factor method technique. The overall noise figure is then under a noise figure correction step to determine the noise figure of the DUT. Details of Y-factor method and noise figure correction are included in Appendix B.
+ R
-v
nR
n R i
(a) (b) (c) R
+
-v
nFig. 2.1 (a) Equivalent network for computing thermal noise of a resistor.(b)(c) Thermal noise model for a resistor.
Source Drain
P-substrate
Gate L W
0 x Leff
QI(x)
x+dx v(x)
E, lateral field
Fig. 2.2 Schematic diagram of a MOSFET operated in saturation condition.
(a)
(b)
(c)
Fig. 2.3 (a)(b)(c) noise figure F plotted with respect to Re(ΓBoptB) and Im(ΓBoptB) with FBmin B= 1, Re(ΓBsoptB) = Im(ΓBsoptB) = 0.1 and RBnB = 100.
(a)
(b)
(c) Fig. 2.4 (a)(b)(c) noise figure F plotted with respect to Re(ΓBoptB) and Im(ΓBoptB) with FBmin B= 1,
Re(ΓBsoptB) = Im(ΓBsoptB) = 0.1 and RBnB = 50.
Noise source
NP5 controller Noise figure meter Noise figure test set
Network analyzer DC power supply
DUT
Mismatch Noise Source
(MNS)
Remote Receiver
Module (RRM)
MNS: A solid state electronic tuner with embedded bias-T and switching circuit.
RRM: A low noise amplifier with embedded bias-T and switching circuit.
Fig. 2.5 Block diagram of ATN noise figure measurement system configuration.
Chapter 3
RF MOSFET Noise Characterization
3.1 Extrinsic Noise Characteristics
RF MOSFETs with 80nm and 65nm gate length were fabricated to study the nanoscale CMOS scaling effect on speed and noise performance. Multi-finger structure with fixed finger width (4µm) and various finger numbers (NF=6, 18, 36, 72) are employed to reduce the gate resistance. Reduction of gate resistance shows no impact on cut-off frequency (fT)
m
T 2 2
f = g
2
π
Cgg −Cgd
(3-1)
while other RF performance can be improved such as maximum oscillation frequency (fmax) and noise figure (NFmin) [17,18]. Fig. 3.1 indicates Rg extracted from Z-parameters and gate capacitances (Cg) extracted from Y-parameters for various finger numbers. It shows a trade-off between Rg and Cg (Cgd, Cgs).
Measured NFmin for 65nm and 80nm nMOS of various NF are shown in Fig. 3.2 (a) and (b). One is biased under maximum gm (Vgs = 0.7V for 80nm and Vgs = 0.6V for 65nm) which is corresponding to maximum fT, the other is biased under minimum NFmin (Vgs = 0.55V for 80nm and Vgs = 0.35V for 65nm). They indicate there is certain gate voltage difference between maximum fT and minimum NFmin. NFmin without de-embedding decreases remarkably with increasing NF. One reason is the Rg reduction due to increase multi-finger gate number, however, this can not explain the dramatic difference such as 2.5~3dB between NF = 6 and NF = 72 in frequency range of 5~18GHz.
Fig. 3.3 illustrates the fT extracted from extrapolation of |H21| to unity gain. Rg is decreasing as NF increases at the expense of larger gate capacitance. (3-1) shows fT is
dependent on gm and gate capacitance. Both gm and Cg are nearly proportion to the finger number, thus lead to weak dependence on NF for fT at around 100~105GHz for 80nm device.
Scaling from 80nm to 65nm in gate length, about 20~30% increase in driving current and maximum transconductance and 20% reduction in gate capacitance lead to obvious 50~60%
improvement in maximum fT. The improvement indicates the advantage provided by device scaling for high speed CMOS applications. However, measured NFmin of these two sets of
improvement in maximum fT. The improvement indicates the advantage provided by device scaling for high speed CMOS applications. However, measured NFmin of these two sets of