Noise Correlation Matrix De-embedding - Conventional Noise De-embedding Method

Chapter 3 RF MOSFET Noise Characterization

3.2 Conventional Noise De-embedding Method

3.2.1 Noise Correlation Matrix De-embedding

According to the circuit theory of linear noisy networks, any two-port device can be separated into two parts: additional noise source part and noiseless device part. For common application three equivalent representations are used to describe the two-port devices, they are admittance, impedance, chain representation respectively [21]. Generally, chain representation is used mostly in which a voltage noise source and a current noise source are included. Chain representation of a noisy two-port network is shown in Fig. 3.4. The benefit of the representation is that it is easier to find the relation of input signal and noise level because it refers the entire device noise source to the input. Correlation matrices are described with the noise sources in the form of self-power and cross power spectral densities as matrix element.

Power spectral densities are defined as the Fourier transform of their auto and cross correlation function.

To perform noise de-embedding, correlation matrices of the two-port circuit and the decomposed components should be known. The matrices are obtained from the measured noise parameters or calculated theoretically based on the physics (such as those passive elements). The noise parameters of a passive device are fully determined by its small-signal parameters. For an element with admittance Y, the correlation matrix is given in the form of

Y B

C =2K T Re[Y]⋅ (3-1)

Chain representation of the whole test fixture is estimated from the measured noise parameter (NFmin, Rn, Yopt).

1 [ ] 2 2

⎛ − − ⎞

⎜ ⎟

= ⎜ ⎟

⎜ − − ⎟

⎜ ⎟

⎝ ⎠

min

min * | |

n n opt

n opt n opt

R F R Y

C K T

F R Y R Y

(3-2)

Once the correlation matrices are known, according to the configuration of the two-port network, transformation of correlation matrices should be done. Appropriate matrix operation is applied to isolate the parasitic parts form the intrinsic correlation matrix. Noise parameters after de-embedding, called intrinsic noise parameters, and then could be computed as function of correlation matrix

11 22 12

1 12 −

= + ^{, ,} + ^{, ,} ^, ^, ^{, ,}

min,

(Im[ ])

Re[ A DUT] A DUT A DUT A DUT DUT

B B

C C C

F C

k T k T (3-3)

11 22 12 12

− + Ι

= + Ι = ^{, ,} ^, ^, ^{, ,} ^{, ,}

, , ,

, ,

(Im[ ]) * Im[ ]

* ^A ^DUT ^A ^DUT ^A ^DUT ^A ^DUT

sopt DUT sopt DUT sopt DUT

A DUT

C C C C

Y G B

(3-4)

= 2^{, ,}

, Re[ ^A ^DUT]

n DUT

R C

k T (3-5) Details of correlation matrices de-embedding procedure are included in Appendix B.

3.2.2 De-embedding Results

For the purpose of studying the correlation matrix de-embedding on different devices.

Three test-keys with different probing pad layout structures were implemented. The first one is 0.13µm low voltage technology (013LV) adopted for fabrication of 80nm and 65nm nMOS.

The second one is RF CMOS technology using 0.13µm general purpose process (013G) with device target gate length at around 105nm. The last one is also a 0.13µm general purpose technology with target gate length at around 110nm. The three sets of DUT are all nMOS devices but with different probing pad layout structures. Details of these test structures will be discussed in Chapter 5 where the corresponding equivalent circuit will be introduced.

De-embedding work was done by writing equations in ADS data display window. The correlation matrix de-embedding results are shown in Fig. 3.5 ~ Fig. 3.7. In Fig. 3.5(a), NFmin

after matrix de-embedding show great amount of reduction and almost the same level for

various NF devices. But decrease of NFmin with increasing frequency in lower frequency region (3~5GHz) fails to follow the linear frequency dependence. Reduction of Rn is decreasing as NF increases. The results suggest that more parasitic effect was originally suffered by smaller device, i.e. NF = 6 than NF = 72, and can be eliminated through de-embedding. Reduction of real part of optimum source admittance, Re(Ysopt) was also appreciable and this also relates to the reduction of NFmin. Fig. 3.6 is the comparison of de-embedding results for lossy pad and normal pad test structures. Much more noise reduction for lossy pad than normal pad was observed. It suggests effective de-embedding realized for lossy pad. However, frequency dependence issue as shown in Fig. 3.5 still remains. As for pad structure with poly ground shielding under signal pad, less substrate coupling effect leads to small difference between as-measured data and de-embedded results.

In summary, no need to establish an equivalent circuit model required for the matrix correlation method makes it convenient to calculate the intrinsic noise parameters from the measured ones. But there are three major drawbacks make this method not that popular.

Firstly, the data after de-embedding usually suffer severe fluctuation due to its limited measurement precision, i.e., de-embedded results are very sensitive to measured data accuracy, especially for novel devices with noise figure below 1dB. The second one is its critical dependence on open pad test structure design and limitation in fully extracting the TML induced extra coupling noise provided that it lacks of ground shielding. The last one drawback is its failure of full range coverage for circuit design application. Because noise parameters and S parameters corresponding to arbitrary biases or frequencies can not be predicted from the measured data limited to certain specified bias and frequency.

0 10 20 30 40 50 60 70 80 0

50 100 150 200 250 300 350 400 450 500

0 5 10 15 20 25 30 35 N

= 6

N

=18 N

=36 N

=72

T013LV_80nm_nMOS L=0.13

m,W

=4

m

C

+C

, C

(fF)

Finger Number, N

R

( Ω )

Fig. 3.1 80nm nMOS Rg and Cg (Cgs, Cgd, Cgd) extracted from Z- and Y- parameters. (NF = 6, 18, 36, 72)

0 2 4 6 8 10 12 14 16 18 20 0

1 2 3 4 5 6 7 8

Vds=1.0V Vg@min. NF

80nm 65nm N_F= 6 N_F=18 N

F=36 N

F=72

T013LV_65&80nm_nMOS L=0.13µm,W_F=4µm

NF min(dB)

freq (GHz)

(a)

0 2 4 6 8 10 12 14 16 18 20 0

1 2 3 4 5 6 7 8

Vds=1.0V Vg@max. g_m

80nm 65nm N

F= 6 N_F=18 N_F=36 N

F=72

T013LV_65&80nm_nMOS L=0.13µm,W_F=4µm

NF min(dB)

freq (GHz)

(b)

Fig. 3.2 Measured noise figure NFmin of 80 and 65nm nMOS for NF = 6, 18, 36, 72 (a) Vd=1V, Vg at min. NFmin (Vgs=0.7/0.6V)(b) Vd=1V, Vg at max. gm (Vgs=0.5/0.35V).

1 10 100 0

20 40 60 80 100 120 140 160 180 200

65nm 80nm N_F= 6 N_F=18 N

F=36 N

F=72

Vds=1.0V

T013LV_65nm&80nm_nMOS L=0.13µm,W_F=4µm

Cut-off frequency, f T(GHz)

Id (mA)

Fig. 3.3 Cut-off frequency fT of 80 and 65 nm nMOS under various drain current extracted from extrapolation of |H21| = 1.

Noisy Two-Port

Network

V

Noiseless Two-Port

Network I

Fig. 3.4 Chain representation of a noisy two-port network with a voltage source and a current source in the input port.

0 2 4 6 8 10 12 14 16 18 20

circle:Matrix De-embedded Re(Yopt)

circle:Matrix De-embedded

Ysopt(mS)

circle:Matrix De-embedded

Ysopt(mS)

circle:Matrix De-embedded

Ysopt(mS)

Pad layout without metal line and poly-ground shielding under signal pad. Signal pad metal stacking is from M2 to M8. Comparison of noise parameters between as-measured and after correlation matrix de-embedded. (a) NFmin (b) Rn (c) Re(Ysopt) and Im(Ysopt)

0 2 4 6 8 10 12 14 16 18 20

normal pad w/o ground shielding measured normal pad w/o ground shielding

measured

lossy pad w/o ground shielding measured lossy pad w/o ground shielding

measured

normal pad w/o ground shielding measured normal pad w/o ground shielding

measured

lossy pad w/o ground shielding measured lossy pad w/o ground shielding

measured

0 2 4 6 8 10 12 14 16 18 20

normal pad w/o ground shielding measured

Matrix de-embedded

T13RF95A_nMOS W/N_F=4µm/36 Vd=1.2, Vg=0.5

normal pad w/o ground shielding measured

Matrix de-embedded

lossy pad w/o ground shielding measured

Matrix de-embedded T13RF95A_nMOS

W/N_F=4µm/36 Vd=1.2, Vg=0.5 lossy pad w/o ground shielding

measured

Pad layout without poly-ground shielding under signal pad. Two signal pad metal stacking are from M2 to M8 (called lossy pad) and only top metal M8 (normal pad).

Comparison of noise parametersbetween as-measured and after correlation matrix de-embedded. (a) NFmin (b) Rn (c) Re(Ysopt) and Im(Ysopt)

0 2 4 6 8 10 12 14 16 18 20

circle:Matrix De-embedded Re(Yopt)

circle:Matrix De-embedded

Ysopt(mS)

circle:Matrix De-embedded

Ysopt(mS)

circle:Matrix De-embedded

Ysopt(mS) Vg = 0.6V. Pad layout with poly-ground shielding under signal pad. Signal pad metal stacking consists of M8 only. Comparison of noise parametersbetween as-measured and after correlation matrix de-embedded. (a) NFmin (b) Rn (c) Re(Ysopt) and Im(Ysopt)

Chapter 4 RF MOSFET Intrinsic I-V and C-V Model Calibration

4.1 I-V and C-V Modeling Theory Valid for Sub-100nm MOSFETs

A well calibrated current-voltage (I-V) and capacitance-voltage (C-V) model is pre-requisite to accurate RF MOSFET model development. An elaborated model of I-V characteristic over a wide bias range is important for nowadays circuit design, especially for analog and RF circuit design, where a variety of bias conditions will be used. Also, with the increasing usage of low power circuit in modern IC applications, modeling near subthreshold region is also necessary. Capacitance model, similarly, need to be well calibrated to accurately predict the circuit performance. Altogether, correct I-V and C-V models are essential to provide us trustworthy DC and AC characteristics for further study of high frequency performance.

To ensure free from a non-physical model, before starting the parameter extraction optimization loop, some process related model parameters are specified and fixed at their known values, such as some important geometry or process parameters, Lint (channel length offset), Wint (channel width offset), Tox (oxide thickness), Nch (channel doping concentration), Xj (junction depth) and so forth.

In this thesis, 80nm and 65nm devices fabricated by C013LV process were adopted for I-V and C-V model calibration and noise de-embedding method development. The calibration work was started by modifying the model released by foundry, TSMC. For C013LV technology, BSIM3v3 model is used and the following important mechanisms are considered [11] (1) short channel and narrow width effects on threshold voltage, (2) mobility reduction due to vertical field, (3) velocity saturation, (4) drain-induced barrier lowering (DIBL), and (5)

Substrate current induced body effect (SCBE). It is assumed that most of the I-V and C-V parameters were fairly modeled in the original model and only minor modification is needed to improve the model accuracy. Unfortunately, the assumption can barely fit 80 nm devices but absolutely is no longer valid for 65 nm devices.

4.2 Intrinsic I-V Model

For RF MOSFET, 3–terminal test structure is usually implemented with common source configuration in which source and body terminals are tied together and grounded. To measure its high frequency characteristic (both S parameter and NFmin), two sets of probing pad with G-S-G structures are implemented and connected to the gate and drain terminals. The parasitic resistances associated with MOSFET’s terminals such as Rg_ext, Rd_ext, Rs_ext, and Rb_ext contributed from the interconnection lines and probing pads will affect I-V characteristic of DUT. Extraction of these parasitic resistances should be done and added to the original intrinsic MOSFET model (BSIM3). The mentioned parasitic resistances can be extracted from the dummy short pads which is designed to de-embed the resistive and inductive parasitics of the interconnect lines and probe pads, etc.

In this study, simulation was done using Agilent Advance Design System (ADS) for model verification and calibration. Based on the original model card, default simulation results of Id-Vg and Id-Vd curves were obtained. Through comparison between simulation and measurement in terms of Id-Vg and gm-Vg curves in both linear and saturation regions, significant deviation was identified for the threshold voltage (Vth), drain current (Id), gate subthreshold swing (S), etc. As for comparison of Id-Vd curves, channel length modulation (CLM) and drain induced barrier lowering (DIBL) effects were revealed. Besides, the intrinsic and extrinsic parasitic resistances, Rd_int and Rd_ext at drain terminal will affect the rising slope between linear and saturation region.

For BSIM3, there are many parameters associated with the threshold voltage model.

Since source and body of the DUT are tied together and connected to ground, body bias effect on threshold voltage is not available. Narrow width effect on Vth was neglected for sufficient large width of 4µm. Short channel effect related parameters such as Dvt0 and Dvt1 were included to account for charge sharing induced threshold voltage lowering. Mobility model parameter U0 is the zero-filed mobility for Id-Vg simulation in linear region under small drain bias (Vd = 0.1 or 0.05V). Ua, Ub and Uc are fitting parameters used to model the mobility degradation subject to normal field under gate bias. Saturation velocity Vsat determines the saturation current level. Eta0, and Dsub control the amount of threshold voltage variation caused by DIBL and Id-Vg under Vd= Vdd is the fitting target. Parameters A1 and A2 stands for first and secondary non-saturation effect which occurs in the expression of Vdsat also help to improve Id-Vg and gm-Vg modeling. Subthreshold current fitting can be improved by Voff and Nfactor after the previous terms are well modeled. As for Id-Vd modeling, Pclm, Pdiblc1, Pdiblc2 can be used to properly modify the linear and saturation currents as well as output resistance Rout. Besides Id-Vg and Id-Vd characteristics, first order derivative and even second order derivative also deserve the effort to be well modeled since gm or gds at a certain given bias (application bias point) may affect the device performance such as fT, fmax as well as circuit simulation result.

For high frequency measurement, the test devices are configured to be probed through GSG pads. It is not suitable to conduct I-V measurement by using DC probes as conventional DC measurement does. It is due to the fact that only probing on two of the four ground pads will double the parasitic resistance. Even if G-S-G probes are used, horizontal level of the probes should be maintained at an identical horizon. Besides, to compensate for the cable loss, Kelvin connection [22] (with Force and Source lines) was adopted by introducing a bias-T.

This configuration can prevent cable loss and small signal interference. Fig. 4.1 (a) and (b)

give the idea of the need of this measurement framework.

Fig. 4.2 ~ Fig. 4.4 present the DC I-V modeling results. Good agreement between measured and simulated results under varying biases and various NF shows the integrity of the intrinsic BSIM model. The 65nm device was extremely trimmed from 130nm by 65nm, one half of its drawn length. High gate leakage or GIDL may contribute to the high drain current in its off-state. Current degradation for large NF can be identified from Fig. 4.2 (b).

Transconductance gm per unit width for various NF is given in Fig. 4.5. About 20% gm

degradation was observed for NF = 72 compared with NF = 6 for both two sets of device.

Additional IR drop caused by the parasitic source resistance Rs_ext is proposed to explain the increasing degradation associated with larger NF. It is worthy to note that due to the distinct difference in I-V characteristics between these two sets of devices (65nm and 80nm), different I-V model parameters were used to get optimized fitting individually.

4.3 Intrinsic Gate Capacitance (C-V) Model

In this section, capacitance modeling of multi-finger RF MOSFET is presented. Oxide thickness of C013LV nMOS technology is 1.7nm. For this thin oxide, capacitance model flag capMod = 3 was set as default model to take into account of the finite charge thickness determined by quantum effect.

Capacitance in MOSFET is generally divided into three parts, intrinsic, extrinsic and extrinsic parasitic. The intrinsic part is corresponding to the capacitances that are associated with the channel region (region under gate oxide and between metallurgical junction of source and drain). Extrinsic capacitances model considered in BSIM3 are fringing capacitance and overlap capacitance; both consist of bias dependent and bias independent part. Only bias independent outer fringing capacitance is implemented (parameter CF) while both bias dependent LDD overlap capacitance (parameter Cgsl, Cgdl) and bias independent non-LDD

overlap capacitance (parameter Cgso, Cgdo) are taken into account. However, due to metal routing of DUT and prerequisite of GSG probing pad for RF measurement, extra parasitic capacitances were introduced and these were classified as extrinsic parasitic capacitances (Cgs_ext, Cgd_ext, Cds_ext, Cpad). Fig. 4.6 demonstrates a detailed classification of capacitances in MOSFETs.

Capacitances of RF MOSFET with GSG probing structure are conventionally extracted from the intrinsic Y parameter (Yint) at low frequency. Before the extracting process, parasitic capacitances due to probing pad and interconnection metal should be de-embedded from the measured data. Traditionally, the removal of these parasitics is done through open de-embedding mentioned early. In fact, short de-embedding should also be carried out to get rid of the series impedances. This is essential for accurate capacitance extraction. A broadly accepted de-embedding technique is open/short two step de-embedding for two-port three terminal device (source/bulk tied together) [23]. Due to the fact that the coupling capacitance between two-ports is mainly dominated by the coupling of interconnection metal instead of probing pad, a modified open/short de-embedding approach was proposed to avoid over de-embedding on this coupling capacitance and thus improved Cgd model accuracy. Appendix C presents this modified de-embedding. The new de-embedding method is especially efficient when an open pad is designed with all the interconnection metal left.

After the de-embedding, intrinsic gate capacitances can be extracted from the formulas given by [24]:

gg int,11

C = Im(Y )/ω (4-1)

gd int,12

C = - Im(Y )/ω (4-2)

gs int,11 int,12

C = Im(Y +Y )/ω (4-3)

ds int,22 int,12

C =Im(Y +Y )/ω (4-4)

Intrinsic gate-to-back capacitance Cgb is negligible due to its small value in triode and saturation regions. This is because the inversion layer in the channel shields between gate and bulk. It is worthy to mention that how clean the parasitic capacitances can be removed and the intrinsic capacitance can be extracted critically depends on the open dummy structure, i.e., how many coupling terms can be removed from the measured data. A conventional open pad leaving only the GSG pad frame obviously underestimates the coupling capacitances. A modified structure is to remove the DUT cell simply, thus leave the connecting metal between DUT cell and signal metal pad. This modification enables us to extract the capacitances of the DUT cell that is sometimes what a circuit designer need in some cases. As for the open de-embedding structure available for C013LV devices, the metal line is terminated at M3 and the parasitic coupling between gate to drain, gate to source, drain to source by means of connecting via and metal (from M1 to M3 in 013LV case) will remain in the de-embedded data. These coupling terms greatly depend on the metal routing and lead to the non-scalability of capacitance modeling. This non-scalable property will affect the accuracy of the following parameter extraction for DUT, such as fT, i , ²_d i [18][19]. From device modeling point of ²_g view, it is better to clearly extract all the parasitics from the DUT to correctly model both capacitances of parasitic and DUT. Also, a pure device model can provide design freedom on metal routing.

In this work, one open dummy pad was shared by all the DUTs. This open dummy is designed so that only the common part of the DUTs was left, i.e. G-S-G pad with interconnection line terminated at M3. As mentioned above, this kind of de-embedding cannot remove the coupling capacitances associated with lower metals (M1~M3). Due to the fact, the capacitance of DUT after de-embedding includes finger-number dependent capacitance, both

intrinsic and extrinsic portion, and finger-number independent extrinsic parasitic capacitance.

Gate capacitance of different finger number is shown in Fig. 4.7. Linear finger-number dependence was demonstrated but the extrapolation of capacitance reveals a non-zero intercept. Linear slope of these capacitances shows Cgs/Cgd partition of approximately 60%/40% for 65nm device and 65%/35% for 80nm device, respectively. The non-zero intercept indicates a physically finger-number independent common parasitic term for the DUT with different finger numbers.

In the modeling process, extrinsic components Cgs_ext and Cgd_ext were used to model the common parasitic capacitance and model parameters, Cgso, C_gdo, C_gsl, C_gdl, V_offcv were used to complete the result. First, adjust Cgso and Cgdo to a value so that simulation result is close to the measured one. Then, use Voffcv to modify its gate bias trend. C_gsl and Cgdl are employed to modulate the gate bias trend of Cgs and Cgd individually. Parameter DLC may be included to adjust the length offset for C-V model which does not affect the I-V curve modeling.

Finalized model parameters are shown in Table 4.1. Fig. 4.8 (a)~(c) present the modeling result of the gate capacitance. Cgg is reduced by around 20% for 65nm following the Lgate

scaling factor while Cgd is reduced by only 7~14%. The minor reduction of Cgd is due to the drain depletion effect under saturation condition.

Table 4.1

Model parameters for gate capacitance modeling.

W_F=4um C_{gs_ext}(fF) C_{gd_ext}(fF) Cgs0(F/m) Cgd0(F/m)Cgsl(F/m)Cgdl(F/m) CF(F/m) Voffcv 65nm 3.488 3.2 10p 370p 60p 60p 0 -0.050 80nm 1.225 4.6 10p 420p 50p 50p 0 -0.038

0.0 0.2 0.4 0.6 0.8 1.0 0

20 40 60 80 100 120 140 160 180 200

w/o Kelvin connection with Kelvin connection

Id (mA)

Vd

80nm_Nf=72_NMOS Vg=0~1V step=0.2V

(a)

0.0 0.2 0.4 0.6 0.8 1.0 0

20 40 60 80 100 120 140 160 180

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35

I-V measured w/o Kelvin connection small signal power on

small signal power off

Id (mA )

Vg 80nm_Nf=72_NMOS Vg=1.0V

gm ( m A/V)

(b)

Fig. 4.1 (a) Id-Vd characteristic measured with and without Kelvin connection.

(b) Id-Vg characteristics measured with and without bias-T network to isolate the small-signal from DC measurement.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

line: Simulation Vd= 1V

gm (mS)

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Fig. 4.5 Transconductance gm for various NF of 65 and 80nm respectively.

Fig. 4.6 Category diagram of capacitance in MOSFETs.

0 5 10 15 20 25 30 35 40 0

25 50 75 100 125 150 175

Y =1.99632+2.14868 X

Y =6.00632+1.47702 X Y =7.99474+3.6261 X

Cgd Cgs

Cgg

Capacitance (fF)

Finger number ( N

) 65nm_nMOS

Vg=1, Vd=1V

(a)

0 5 10 15 20 25 30 35 40 0

50 100 150 200 250

Y =3.37842+3.51991 X

Y =4.59895+1.78605 X Y =7.98526+5.30557 X

Cgd Cgs Cgg

Capacitance ( fF)

Finger number ( N

) 80nm_nMOS

Vg=Vd=1V

(b)

Fig. 4.7 (a) 65nm nMOS Cgg, Cgd and Cgs extracted at Vg = Vd = 1V for NF = 6, 18, 36

在文檔中損耗基板之去寄生效應法與射頻金氧半場效電晶體雜訊萃取之應用 (頁 36-123)