System Calibration and Measurement - High Frequency Noise Measurement

Chapter 2 Noise Theory and Noise Measurement Technique

2.4 High Frequency Noise Measurement

2.4.2 System Calibration and Measurement

As high frequency characterization was conducted on the devices (DUT), the applied signals with short wavelength are comparable to the probe, connecting cables, adapters, bonding wires, and our interested device. Thus, losses caused by the connections will remarkably affect the measurement results, especially critical as measurement frequency increases. On the other hand, a measurement system has its own system error. Consequently, a system calibration should be performed to take those losses into consideration, calibrate the system errors and then shift the measurement signal reference plane to the DUT plane. The validity and accuracy of the calibration results depend on the calibration method used.

For S-parameter measurement, SOLT (short-open-load-through) calibration is a popular method to establish the DUT test plane nowadays. For the noise measurement system, there are several calibration steps required to build a noise measurement plane for DUT. A complete calibration procedure includes input SOL calibration, noise source calibration, network analyzer calibration, thru delay calibration, RRM calibration, MNS calibration and finally system noise parameter calibration. Since calibration details are not our focus, only rough idea is provided here. After the overall calibration procedure, noise contribution of the system will be characterized. Thus, real noise power of DUT can be separated from the noise power contributed from system. This can be verified by connecting the input and output with a known DUT, in our case a dummy “thru” pattern was used to check if the noise figure is less than 0.1dB.

After calibration, noise measurement reference plane is then established. In the beginning of noise parameter characterization, S-parameters measurement at the DUT reference plane should be done first. In the following, by varying the impedance presented to the input of the DUT around the Smith chart, output noise power (sometimes, also refers to noise temperature) of DUT plus the receiver as a function of Γs (source reflection coefficient)

was measured, each Γs and the corresponding noise power constructs a set of equations. The noise parameters are decided by solving the set of equations. Theoretically speaking, only four input states are needed for noise characterization because the noise behavior equation (2-23) has merely four unknown parameters. In practice, however, for the sake of reducing the influence of random errors more than four points were measured (generally 16 states or 20 states) and a proper fitting procedure was used to extract the parameters. Finally, four noise parameters: NFmin, Rn,Re (Γopt) or Re (Yopt) and Im (Γopt) or Im (Yopt) are obtained.

In the measurement process, the overall noise figure was calculated by Y-factor method technique. The overall noise figure is then under a noise figure correction step to determine the noise figure of the DUT. Details of Y-factor method and noise figure correction are included in Appendix B.

+ R

-v

n R i

(a) (b) (c) R

-v

Fig. 2.1 (a) Equivalent network for computing thermal noise of a resistor.(b)(c) Thermal noise model for a resistor.

Source Drain

P-substrate

Gate L W

0 x L_eff

Q_I(x)

x+dx v(x)

E, lateral field

Fig. 2.2 Schematic diagram of a MOSFET operated in saturation condition.

(a)

(b)

(c)

Fig. 2.3 (a)(b)(c) noise figure F plotted with respect to Re(Γ^Bopt^B) and Im(Γ^Bopt^B) with F^Bmin ^B= 1, Re(Γ^Bsopt^B) = Im(Γ^Bsopt^B) = 0.1 and R^Bn^B = 100.

(a)

(b)

Re(Γ^Bsopt^B) = Im(Γ^Bsopt^B) = 0.1 and R^Bn^B = 50.

Noise source

NP5 controller Noise figure meter Noise figure test set

Network analyzer DC power supply

DUT

Mismatch Noise Source

(MNS)

Remote Receiver

Module (RRM)

MNS: A solid state electronic tuner with embedded bias-T and switching circuit.

RRM: A low noise amplifier with embedded bias-T and switching circuit.

Fig. 2.5 Block diagram of ATN noise figure measurement system configuration.

Chapter 3

RF MOSFET Noise Characterization

3.1 Extrinsic Noise Characteristics

RF MOSFETs with 80nm and 65nm gate length were fabricated to study the nanoscale CMOS scaling effect on speed and noise performance. Multi-finger structure with fixed finger width (4µm) and various finger numbers (NF=6, 18, 36, 72) are employed to reduce the gate resistance. Reduction of gate resistance shows no impact on cut-off frequency (fT)

T 2 2

f = g

π

C_gg −C_gd

(3-1)

while other RF performance can be improved such as maximum oscillation frequency (fmax) and noise figure (NFmin) [17,18]. Fig. 3.1 indicates Rg extracted from Z-parameters and gate capacitances (Cg) extracted from Y-parameters for various finger numbers. It shows a trade-off between Rg and Cg (Cgd, Cgs).

Measured NFmin for 65nm and 80nm nMOS of various NF are shown in Fig. 3.2 (a) and (b). One is biased under maximum gm (Vgs = 0.7V for 80nm and Vgs = 0.6V for 65nm) which is corresponding to maximum fT, the other is biased under minimum NFmin (Vgs = 0.55V for 80nm and Vgs = 0.35V for 65nm). They indicate there is certain gate voltage difference between maximum fT and minimum NFmin. NFmin without de-embedding decreases remarkably with increasing NF. One reason is the Rg reduction due to increase multi-finger gate number, however, this can not explain the dramatic difference such as 2.5~3dB between NF = 6 and NF = 72 in frequency range of 5~18GHz.

Fig. 3.3 illustrates the fT extracted from extrapolation of |H21| to unity gain. Rg is decreasing as NF increases at the expense of larger gate capacitance. (3-1) shows fT is

dependent on gm and gate capacitance. Both gm and Cg are nearly proportion to the finger number, thus lead to weak dependence on NF for fT at around 100~105GHz for 80nm device.

Scaling from 80nm to 65nm in gate length, about 20~30% increase in driving current and maximum transconductance and 20% reduction in gate capacitance lead to obvious 50~60%

improvement in maximum fT. The improvement indicates the advantage provided by device scaling for high speed CMOS applications. However, measured NFmin of these two sets of devices did not show significant difference.

Three interesting features are revealed in measured noise in Fig. 3.2. Firstly, there is an abnormal strong dependence on finger number while fT is almost the same thought Rg is reduced. Secondly, weak dependence on gate length was observed even gained 50% fT

improvement. The last is the nonlinear frequency dependence of NFmin which can not be explained by the theoretical thermal noise behavior. As expressed in equivalent circuit element, NFmin was shown to be linearly dependent on frequency [18-20]. Consequently, it is suggested that lossy pad and lossy substrate contribute to these excess noise. Noise is coupled from the lossy substrate through capacitive probing pad and interconnects transmission line.

To understand the pure noise behavior (intrinsic) of the DUT and further to model it, noise de-embedding on the measured one is indispensable.

3.2 Conventional Noise De-embedding Method

Conventionally, there are two ways to characterize the intrinsic noise performance of MOSFET transistors. One is by directly de-embedding the external noise through matrix calculation that is similar to the S-parameter de-embedding but much more complicated. This popular technique is called noise correlation matrix de-embedding. The other method is to extract intrinsic noise parameters through the approach of equivalent circuit model. This is a new method developed in this study. By equivalent circuit implementation, measured noise parameters can be simulated and noise caused by probing pad can also be characterized. The

details will be described in chapter 5.

3.2.1 Noise Correlation Matrix De-embedding

According to the circuit theory of linear noisy networks, any two-port device can be separated into two parts: additional noise source part and noiseless device part. For common application three equivalent representations are used to describe the two-port devices, they are admittance, impedance, chain representation respectively [21]. Generally, chain representation is used mostly in which a voltage noise source and a current noise source are included. Chain representation of a noisy two-port network is shown in Fig. 3.4. The benefit of the representation is that it is easier to find the relation of input signal and noise level because it refers the entire device noise source to the input. Correlation matrices are described with the noise sources in the form of self-power and cross power spectral densities as matrix element.

Power spectral densities are defined as the Fourier transform of their auto and cross correlation function.

To perform noise de-embedding, correlation matrices of the two-port circuit and the decomposed components should be known. The matrices are obtained from the measured noise parameters or calculated theoretically based on the physics (such as those passive elements). The noise parameters of a passive device are fully determined by its small-signal parameters. For an element with admittance Y, the correlation matrix is given in the form of

Y B

C =2K T Re[Y]⋅ (3-1)

Chain representation of the whole test fixture is estimated from the measured noise parameter (NFmin, Rn, Yopt).

1 [ ] 2 2

⎛ − − ⎞

⎜ ⎟

= ⎜ ⎟

⎜ − − ⎟

⎜ ⎟

⎝ ⎠

min

min * | |

n n opt

n opt n opt

R F R Y

C K T

F R Y R Y

(3-2)

Once the correlation matrices are known, according to the configuration of the two-port network, transformation of correlation matrices should be done. Appropriate matrix operation is applied to isolate the parasitic parts form the intrinsic correlation matrix. Noise parameters after de-embedding, called intrinsic noise parameters, and then could be computed as function of correlation matrix

11 22 12

1 12 −

= + ^{, ,} + ^{, ,} ^, ^, ^{, ,}

min,

(Im[ ])

Re[ A DUT] A DUT A DUT A DUT DUT

B B

C C C

F C

k T k T (3-3)

11 22 12 12

− + Ι

= + Ι = ^{, ,} ^, ^, ^{, ,} ^{, ,}

, , ,

, ,

(Im[ ]) * Im[ ]

* ^A ^DUT ^A ^DUT ^A ^DUT ^A ^DUT

sopt DUT sopt DUT sopt DUT

A DUT

C C C C

Y G B

(3-4)

= 2^{, ,}

, Re[ ^A ^DUT]

n DUT

R C

k T (3-5) Details of correlation matrices de-embedding procedure are included in Appendix B.

3.2.2 De-embedding Results

For the purpose of studying the correlation matrix de-embedding on different devices.

Three test-keys with different probing pad layout structures were implemented. The first one is 0.13µm low voltage technology (013LV) adopted for fabrication of 80nm and 65nm nMOS.

The second one is RF CMOS technology using 0.13µm general purpose process (013G) with device target gate length at around 105nm. The last one is also a 0.13µm general purpose technology with target gate length at around 110nm. The three sets of DUT are all nMOS devices but with different probing pad layout structures. Details of these test structures will be discussed in Chapter 5 where the corresponding equivalent circuit will be introduced.

De-embedding work was done by writing equations in ADS data display window. The correlation matrix de-embedding results are shown in Fig. 3.5 ~ Fig. 3.7. In Fig. 3.5(a), NFmin

after matrix de-embedding show great amount of reduction and almost the same level for

various NF devices. But decrease of NFmin with increasing frequency in lower frequency region (3~5GHz) fails to follow the linear frequency dependence. Reduction of Rn is decreasing as NF increases. The results suggest that more parasitic effect was originally suffered by smaller device, i.e. NF = 6 than NF = 72, and can be eliminated through de-embedding. Reduction of real part of optimum source admittance, Re(Ysopt) was also appreciable and this also relates to the reduction of NFmin. Fig. 3.6 is the comparison of de-embedding results for lossy pad and normal pad test structures. Much more noise reduction for lossy pad than normal pad was observed. It suggests effective de-embedding realized for lossy pad. However, frequency dependence issue as shown in Fig. 3.5 still remains. As for pad structure with poly ground shielding under signal pad, less substrate coupling effect leads to small difference between as-measured data and de-embedded results.

In summary, no need to establish an equivalent circuit model required for the matrix correlation method makes it convenient to calculate the intrinsic noise parameters from the measured ones. But there are three major drawbacks make this method not that popular.

Firstly, the data after de-embedding usually suffer severe fluctuation due to its limited measurement precision, i.e., de-embedded results are very sensitive to measured data accuracy, especially for novel devices with noise figure below 1dB. The second one is its critical dependence on open pad test structure design and limitation in fully extracting the TML induced extra coupling noise provided that it lacks of ground shielding. The last one drawback is its failure of full range coverage for circuit design application. Because noise parameters and S parameters corresponding to arbitrary biases or frequencies can not be predicted from the measured data limited to certain specified bias and frequency.

0 10 20 30 40 50 60 70 80 0

50 100 150 200 250 300 350 400 450 500

0 5 10 15 20 25 30 35 N

= 6

N

=18 N

=36 N

=72

T013LV_80nm_nMOS L=0.13

m,W

=4

m

C

+C

, C

(fF)

Finger Number, N

R

( Ω )

Fig. 3.1 80nm nMOS Rg and Cg (Cgs, Cgd, Cgd) extracted from Z- and Y- parameters. (NF = 6, 18, 36, 72)

0 2 4 6 8 10 12 14 16 18 20 0

1 2 3 4 5 6 7 8

Vds=1.0V Vg@min. NF

80nm 65nm N_F= 6 N_F=18 N

F=36 N

F=72

T013LV_65&80nm_nMOS L=0.13µm,W_F=4µm

NF min(dB)

freq (GHz)

(a)

0 2 4 6 8 10 12 14 16 18 20 0

1 2 3 4 5 6 7 8

Vds=1.0V Vg@max. g_m

80nm 65nm N

F= 6 N_F=18 N_F=36 N

F=72

T013LV_65&80nm_nMOS L=0.13µm,W_F=4µm

NF min(dB)

freq (GHz)

(b)

Fig. 3.2 Measured noise figure NFmin of 80 and 65nm nMOS for NF = 6, 18, 36, 72 (a) Vd=1V, Vg at min. NFmin (Vgs=0.7/0.6V)(b) Vd=1V, Vg at max. gm (Vgs=0.5/0.35V).

1 10 100 0

20 40 60 80 100 120 140 160 180 200

65nm 80nm N_F= 6 N_F=18 N

F=36 N

F=72

Vds=1.0V

T013LV_65nm&80nm_nMOS L=0.13µm,W_F=4µm

Cut-off frequency, f T(GHz)

Id (mA)

Fig. 3.3 Cut-off frequency fT of 80 and 65 nm nMOS under various drain current extracted from extrapolation of |H21| = 1.

Noisy Two-Port

Network

V

Noiseless Two-Port

Network I

Fig. 3.4 Chain representation of a noisy two-port network with a voltage source and a current source in the input port.

0 2 4 6 8 10 12 14 16 18 20

circle:Matrix De-embedded Re(Yopt)

circle:Matrix De-embedded

Ysopt(mS)

circle:Matrix De-embedded

Ysopt(mS)

circle:Matrix De-embedded

Ysopt(mS)

Pad layout without metal line and poly-ground shielding under signal pad. Signal pad metal stacking is from M2 to M8. Comparison of noise parameters between as-measured and after correlation matrix de-embedded. (a) NFmin (b) Rn (c) Re(Ysopt) and Im(Ysopt)

0 2 4 6 8 10 12 14 16 18 20

normal pad w/o ground shielding measured normal pad w/o ground shielding

measured

lossy pad w/o ground shielding measured lossy pad w/o ground shielding

measured

normal pad w/o ground shielding measured normal pad w/o ground shielding

measured

lossy pad w/o ground shielding measured lossy pad w/o ground shielding

measured

0 2 4 6 8 10 12 14 16 18 20

normal pad w/o ground shielding measured

Matrix de-embedded

T13RF95A_nMOS W/N_F=4µm/36 Vd=1.2, Vg=0.5

normal pad w/o ground shielding measured

Matrix de-embedded

lossy pad w/o ground shielding measured

Matrix de-embedded T13RF95A_nMOS

W/N_F=4µm/36 Vd=1.2, Vg=0.5 lossy pad w/o ground shielding

measured

Pad layout without poly-ground shielding under signal pad. Two signal pad metal stacking are from M2 to M8 (called lossy pad) and only top metal M8 (normal pad).

Comparison of noise parametersbetween as-measured and after correlation matrix de-embedded. (a) NFmin (b) Rn (c) Re(Ysopt) and Im(Ysopt)

0 2 4 6 8 10 12 14 16 18 20

circle:Matrix De-embedded Re(Yopt)

circle:Matrix De-embedded

Ysopt(mS)

circle:Matrix De-embedded

Ysopt(mS)

circle:Matrix De-embedded

Ysopt(mS) Vg = 0.6V. Pad layout with poly-ground shielding under signal pad. Signal pad metal stacking consists of M8 only. Comparison of noise parametersbetween as-measured and after correlation matrix de-embedded. (a) NFmin (b) Rn (c) Re(Ysopt) and Im(Ysopt)

Chapter 4 RF MOSFET Intrinsic I-V and C-V Model Calibration

4.1 I-V and C-V Modeling Theory Valid for Sub-100nm MOSFETs

A well calibrated current-voltage (I-V) and capacitance-voltage (C-V) model is pre-requisite to accurate RF MOSFET model development. An elaborated model of I-V characteristic over a wide bias range is important for nowadays circuit design, especially for analog and RF circuit design, where a variety of bias conditions will be used. Also, with the increasing usage of low power circuit in modern IC applications, modeling near subthreshold region is also necessary. Capacitance model, similarly, need to be well calibrated to accurately predict the circuit performance. Altogether, correct I-V and C-V models are essential to provide us trustworthy DC and AC characteristics for further study of high frequency performance.

To ensure free from a non-physical model, before starting the parameter extraction optimization loop, some process related model parameters are specified and fixed at their known values, such as some important geometry or process parameters, Lint (channel length offset), Wint (channel width offset), Tox (oxide thickness), Nch (channel doping concentration), Xj (junction depth) and so forth.

In this thesis, 80nm and 65nm devices fabricated by C013LV process were adopted for I-V and C-V model calibration and noise de-embedding method development. The calibration work was started by modifying the model released by foundry, TSMC. For C013LV technology, BSIM3v3 model is used and the following important mechanisms are considered [11] (1) short channel and narrow width effects on threshold voltage, (2) mobility reduction due to vertical field, (3) velocity saturation, (4) drain-induced barrier lowering (DIBL), and (5)

Substrate current induced body effect (SCBE). It is assumed that most of the I-V and C-V parameters were fairly modeled in the original model and only minor modification is needed to improve the model accuracy. Unfortunately, the assumption can barely fit 80 nm devices but absolutely is no longer valid for 65 nm devices.

4.2 Intrinsic I-V Model

For RF MOSFET, 3–terminal test structure is usually implemented with common source configuration in which source and body terminals are tied together and grounded. To measure its high frequency characteristic (both S parameter and NFmin), two sets of probing pad with G-S-G structures are implemented and connected to the gate and drain terminals. The parasitic resistances associated with MOSFET’s terminals such as Rg_ext, Rd_ext, Rs_ext, and Rb_ext contributed from the interconnection lines and probing pads will affect I-V characteristic of DUT. Extraction of these parasitic resistances should be done and added to the original intrinsic MOSFET model (BSIM3). The mentioned parasitic resistances can be extracted from the dummy short pads which is designed to de-embed the resistive and inductive parasitics of the interconnect lines and probe pads, etc.

In this study, simulation was done using Agilent Advance Design System (ADS) for model verification and calibration. Based on the original model card, default simulation results of Id-Vg and Id-Vd curves were obtained. Through comparison between simulation and measurement in terms of Id-Vg and gm-Vg curves in both linear and saturation regions, significant deviation was identified for the threshold voltage (Vth), drain current (Id), gate subthreshold swing (S), etc. As for comparison of Id-Vd curves, channel length modulation (CLM) and drain induced barrier lowering (DIBL) effects were revealed. Besides, the intrinsic and extrinsic parasitic resistances, Rd_int and Rd_ext at drain terminal will affect the rising slope between linear and saturation region.

For BSIM3, there are many parameters associated with the threshold voltage model.

Since source and body of the DUT are tied together and connected to ground, body bias effect on threshold voltage is not available. Narrow width effect on Vth was neglected for sufficient large width of 4µm. Short channel effect related parameters such as Dvt0 and Dvt1 were included to account for charge sharing induced threshold voltage lowering. Mobility model parameter U0 is the zero-filed mobility for Id-Vg simulation in linear region under small drain bias (Vd = 0.1 or 0.05V). Ua, Ub and Uc are fitting parameters used to model the mobility degradation subject to normal field under gate bias. Saturation velocity Vsat determines the saturation current level. Eta0, and Dsub control the amount of threshold voltage variation caused by DIBL and Id-Vg under Vd= Vdd is the fitting target. Parameters A1 and A2 stands for first and secondary non-saturation effect which occurs in the expression of Vdsat also help to improve Id-Vg and gm-Vg modeling. Subthreshold current fitting can be improved by Voff and Nfactor after the previous terms are well modeled. As for Id-Vd modeling, Pclm, Pdiblc1, Pdiblc2 can be used to properly modify the linear and saturation currents as well as output resistance Rout. Besides Id-Vg and Id-Vd characteristics, first order derivative and even second order derivative also deserve the effort to be well modeled since gm or gds at a certain given bias (application bias point) may affect the device performance such as fT, fmax as well as circuit simulation result.

For high frequency measurement, the test devices are configured to be probed through GSG pads. It is not suitable to conduct I-V measurement by using DC probes as conventional DC measurement does. It is due to the fact that only probing on two of the four ground pads will double the parasitic resistance. Even if G-S-G probes are used, horizontal level of the probes should be maintained at an identical horizon. Besides, to compensate for the cable loss, Kelvin connection [22] (with Force and Source lines) was adopted by introducing a bias-T.

This configuration can prevent cable loss and small signal interference. Fig. 4.1 (a) and (b)

give the idea of the need of this measurement framework.

Fig. 4.2 ~ Fig. 4.4 present the DC I-V modeling results. Good agreement between measured and simulated results under varying biases and various NF shows the integrity of the intrinsic BSIM model. The 65nm device was extremely trimmed from 130nm by 65nm, one half of its drawn length. High gate leakage or GIDL may contribute to the high drain current in its off-state. Current degradation for large NF can be identified from Fig. 4.2 (b).

Transconductance gm per unit width for various NF is given in Fig. 4.5. About 20% gm

degradation was observed for NF = 72 compared with NF = 6 for both two sets of device.

在文檔中損耗基板之去寄生效應法與射頻金氧半場效電晶體雜訊萃取之應用 (頁 28-0)