Chapter 1 Introduction
1.2 Overview of Multiple-Gated Devices
A successful design of metal-oxide-semiconductor field-effect transistors (MOSFETs) means the delivery of maximum driving output current (Ion) and the maintenance of acceptable off-current (Ioff). Although a lower threshold voltage (Vth) is desired to achieve a higher output current, unfortunately, a greatly enhanced Ioff is usually accompanied. This is an inevitable trend encountered as shrinking the feature size of MOSFETs [1.28]. Therefore, how to well control the Vth roll-off in aggressively-scaled MOSFETs is an important task to address. In terms of device architecture, the suppression of Vth roll-off of a conventional bulk planar MOSFET can be achieved by the scaling of gate oxide thickness (tox)as well assource and drain (S/D)
junction depth (Xj) and maximum depletion region width (Wdep,max) [1.29]~[1.30].
However, all of them are limited by some constraints. For tox, the limitation is power consumption resulting from the unacceptable increment of gate leakage current with an ultra-thin gate oxide [1.31]~[1.32]. Replacing high- κ ( κ : dielectric constant) materials for the gate dielectrics can mitigate such issue because the adoption of high-κ materials can further scale the equivalent oxide thickness (EOT) while keeping a sufficiently thick physical oxide thickness to suppress the gate leakage current [1.33]~[1.35]. However, the employment of high-κdielectrics is facing a number of challenges and thus very difficult to be realized in practical production lines. These challenges include the inevitable existence of an interfacial layer which makes the actual EOT scaling difficult than expected [1.36], and mobility degradation due to the severe trapped charge-related scattering [1.37]~[1.38]. With respect to Xj, in the past two decades, numerous studies have been proposed to form extra shallow junctions, such as solid-phase epitaxial re-growth (SPER) [1.39] as well as plasma doping [1.40]~[1.41]. However, the accompanied concern is that too shallow an Xj leads to a high external parasitic resistance, and thus, degrading the output current [1.42].
Regarding Wdep,max, a shallow Wdep,max can be achieved by the increment of channel doping concentration. However, the carrier mobility will be aggravated if the channel doping concentration is too high [1.43]~[1.44]. In short, all of the strategies listed above
are seriously limited; therefore, the employment of new three-dimensional (3D) device architectures to replace conventional bulk MOSFETs seems urgently needed. The first multi-gate (MG) device, called XMOS featuring double-gate (DG) configuration, was
proposed by T. Sekigawa and Y. Hayashi in 1984 [1.45]. Five years later, the first fabricated DG device, called ―fully Depleted Lean-channel TrAnsistor (DELTA),‖ was
proposed and reported by D. Hisamoto et al. in 1989 [1.46]. About a decade later, D.
Hisamoto and his colleagues [1.47] proposed a similar DG structure dubbed ―folded channel transistor‖ built on an SOI substrate. This structure is a forerunner of the now
famous FinFET structure [1.48]. Following these pioneering works, a number of versions of MG devices, such as tri-gate [1.49]~[1.50], omega-gate [1.51]~[1.53], Π -gate [1.54]~[1.55], gate-all-around (GAA) [1.56] were subsequently proposed and investigated. Fig. 1-3 compiles all of the cross-sectional views of the aforementioned MG devices. Nowadays, MG devices have been regarded as one of the most promising candidates for succeeding the conventional bulk planar CMOS because of the following advantages [1.57]: (1) Strong immunity against SCEs, (2) low junction leakage current (due to greatly reduced junction area), and (3) compatibility with today's standard CMOS manufacturing. Actually, MG FinFET devices are no longer just candidates for succeeding the planar CMOS. In mid-2011, Intel had announced that the tri-gated body-tied Si-fin structure would be employed in the next 22nm-node microprocessors
[1.58].
Next, we briefly elaborate the root causes why MG devices can mitigate the SCEs and promise the continuity of scaling sown. For a fully-depleted (FD) MG device, the SCEs is closely related to a parameter, Φmin, which is the minimum potential through the whole conduction channel along the direction from source to drain. A sufficiently high potential barrier between S/D (i.e., a small enough Φmin) is desired to avoid the occurrence of punch-through or drain-induced barrier lowering (DIBL) in the channel.
In addition, the xmin, which corresponds to the location where the Φmin occurs, serves as another index to approximately measure the SCEs. Here the x-direction is from source to drain and x = 0 is located at the drain/source junction. Therefore a smaller xmin means the location of Φmin is closer to the source side, implying that more electric field encroachment from drain to the channel, and thus worse SCEs [1.59].
Next, we further introduce the concept of electrostatic scaling length, denoted asλ, which is contained in the relation between theΦmin and xmin and is helpful for us to
respectively. Lg is the effective channel. φ and s φ are the electric potentials at the d source and drain (S/D) regions, respectively, if we assume that the doping concentrations of the S/D regions are heavy enough and no drop in electric potential occurs in the S/D regions.λis defined as [1.59]~[1.60]
( si / ox)t tox si,
λ= ε ε
(1.2-3) where ε and si ε are dielectric constants of silicon and oxide, respectively, ox t is ox the thickness of gate oxide, and t is the thickness of the Si channel. According to the si aforementioned statements, the SCEs of MG devices can be improved by decreasing both Φmin and xmin. Based on Eqs. 1.2-1 ~ 1.2-3, it can be achieved by the reduction of the electrostatic scaling length λ with either a thinner t or si t . However, as ox mentioned above, the scaling of t is limited. Fortunately, concerns regarding the ox scaling of t can be released by the employment of an MG configuration. For DG si
devices, any of the two gates only has to control half of the silicon channel; therefore, the term t in Eq. 1.2-3 can be replaced by si tsi/ 2 and electrostatic scaling length is equal to [1.59]~[1.60]
( si/ ox)tox(tsi / 2)
λ= ε ε . (1.2-4)
This means that, compared to SG devices, DG devices only need twice thick channel thickness to attain the same immunity to SCEs. Similar concept can also be extended to quadruple-gate devices, which feature four control gates, and thus, electrostatic scaling
length can be expressed as [1.61]
( si/ ox)tox(tsi / 4).
λ= ε ε (1.2-5)
In short, with the same t , Eqs. 1.2-3 ~ 1.2-5 indicate that an MG device with si additional control gates features a shorterλ, which results in a smaller Φmin and xmin
and, thus, improving the SCEs. However, MG devices, such as tri-gate or quadruple-gate, usually suffer from the “ corner effect” which results from the premature inversion forming in the corners of the channel of MG devices [1.62]. In particular, such premature inversion results in a undesirable non-uniform turning-on phenomenon and kink presenting in the ID-VG characteristics in subthreshold region [1.62]. Therefore, preserving the feature of suppressing Vth roll-off while avoiding the undesirable“corner effect,” the ultimate MG configuration is with a cylindrical channel completely surrounded by a common gate. Namely, the inherently symmetrical GAA configuration provides theoretically the best gate controllability to the channel potential and eliminates the undesired corner effect [1.63].