Chapter 1 Introduction
1.7 Thesis Organization
Eight chapters are contained in this dissertation. Background and motivation are described in Chapter 1. In Chapter 2, results and analysis regarding particular performance enhancement under DG control in IDG poly-NW TFTs are given. Chapter 3 models and experimentally verifies the unique read characteristics associated with the IDG poly-NW TFT SONOS devices. Chapter 4 firstly presents a novel methodology for extracting the carrier concentration and mobility of heavily-doped poly-Si NWs with J-less transistor structures. Chapter 5 develops an analytical model of Vth and SS for DG
J-less transistors. Chapter 6 comprehensively investigates the device characteristics of a novel n-type asymmetric Schottky-barrier transistor (ASSBT) with silicided Schottky-barrier source and heavily n-doped channel and drain. Chapter 7 comprehensively studies the abnormal Sub-60 mV/dec SS found in GAA poly-Si NW transistors. In Chapter 8, major achievements and summary are stated, and suggested future works are listed. Detailed content of the following chapters are specified as follows:
In Chapter 2, IDG poly-NW TFTs are adopted to experimentally and theoretically elucidate the root cause of device performance enhancement under double-gate control.
In Chapter 3, taking advantages of the more operational flexibilities provided by two independently-biased gates, IDG poly-NW TFTs can serve as a good test vehicle to study the reading characteristics of SONOS devices with various operation modes and investigate the potential of the IDG configuration in the related application.
In Chapter 4, the other architecture of poly-Si NW TFTs featuring GAA configuration is utilized to fabricate the novel GAA in-situ doped poly-Si NW J-less transistors. Moreover, this kind of J-less transistors is adopted to develop a new methodology to probe the active doping concentration and mobility of heavily in-situ phosphorous-doped poly-Si NWs.
In Chapter 5, an analytical model of Vth and subthreshold current for DG J-less
transistors is developed, which can precisely describe the Vth roll-off and subthreshold current even as the channel length is scaled to 22 nm.
In Chapter 6, a novel n-type asymmetric Schottky-barrier transistor (ASSBT) with silicided Schottky-barrier source and heavily n-doped channel and drain is investigated by the aid of 2D TCAD simulation tool [1.112]. The particular operational mechanisms shown in transfer characteristics are investigated. Moreover, as such devices are operated in the region where its operational mechanism is dominated by thermionic field-emission, a modified scaling length“λ” corresponding to the nature of thicker EOT of transistors featuring heavily-doped channel, as mentioned in Sec. 1-3, is employed to describe the degradation of SS.
In Chapter 7, GAA poly-Si NW TFTs are fabricated and characterized. Specifically, under specific applied drain and gate voltage biases, an interesting phenomenon related to sub-60 mV/dec SS is found. Trapping of the excessive holes during the off-state conduction in the poly-Si NW channels is proposed to be responsible for such a phenomenon.
Chapter 8 summarizes the results and contributions made in this dissertation and provides suggested items for future works.
References
[1.1] G. E. Moore, ―Cramming more components onto integrated circuits,‖
Electronics, vol. 38, pp. 114-117, 1965.
[1.2] J. T. Hu, T. W. Odom, and C. M. Lieber, ―Chemistry and physics in one-dimension: Synthesis and properties of nanowires and nanotubes,‖ Acc.
Chem. Res., vol. 32, no. 5, pp. 435-445, 1999.
[1.3] J. Xiang, W. Lu, Y. Hu, Y. Wu, H. Yan, and C. M. Lieber, ―Ge/Si nanowire heterostructures as high-performance field-effect transistors,‖ Nature, vol. 441, no. 7092, pp. 489-493, 2006. transistor for high performance logic and terabit non-volatile memory devices,‖
in VLSI Symp. Tech. Dig., 2007, pp. 144-145.
[1.6] D. P. Burt, N. R. Wilson, J. M. R. Weaver, P. S. Dobson, and J. V. Macpherson,
―Nanowire probes for high resolution combined scanning electrochemical microscopy-atomic force microscopy‖ Nano Lett., vol. 5, no. 4, pp. 639-643, 2005.
[1.7] Y. Cui, Q. Wei, H. Park, and C. M. Lieber, ―Nanowire nanosensors for highly
sensitive and selective detection of biological and chemical species,‖ Science, vol. 293, no. 5533, pp. 1289-1292, 2001.
[1.8] H. C. Lin, M. H. Lee, C. J. Su, and S. W. Shen, ―Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channels,‖ IEEE Trans. Electron Devices, vol. 53, no. 10, pp. 2471-2477, 2006.
[1.9] A. M. Morales and C. M. Lieber, ―A laser ablation method for the synthesis of crystalline semiconductor nanowires,‖ Science, vol. 279, no. 5348, pp. 208-211, 1998.
[1.10] H. F. Yan, Y. J. Xing, b, Q. L. Hang, D. P. Yu, Y. P. Wang, J. Xu, Z. H. Xi, and S.
Q. Feng, ―Growth of amorphous silicon nanowires via a solid-liquid-solid mechanism,‖ Chemical Physics Lett., vol. 323, no. 16, pp. 224-228, 2000.
[1.11] N. A. Sanford, L. H. Robins, M. H. Gray, Y.-S. Kang, J. E. Van Nostrand, C.
Stutz, R. Cortez, A. V. Davydov, A. Shapiro, I. Levin, and A. Roshko,
"Fabrication and analysis of GaN nanorods grown by MBE," Phys. Status Solid.
C, vol. 2, no. 7, pp. 2357-2360, 2005.
[1.12] N. Wang, Y. F. Zhang, Y. H. Tang, C. S. Lee and S. T. Lee, ―SiO2-enhanced synthesis of Si nanowires by laser ablation,‖ Appl. Phys. Lett., vol. 73, no. 26, pp. 3902-3904, 1998.
[1.13] X. Duan and C. M. Lieber, ―General synthesis of compound semiconductor nanowires,‖ Adv. Mat., vol. 12, no. 4, pp. 298-302, 2000.
[1.14] R. S. Wagner and W. C. Ellis, ―Vapor-liquid-solid mechanism of single crystal growth,‖ Appl. Phys. Lett., vol. 4, no. 5, pp. 89-90, 1964.
[1.15] Y. Jiang, T. Y. Liow, N. Singh, L. H. Tan, G. Q. Lo, D. S. H. Chan, and D. L.
Kwong, ―Nickel salicided source/drain extensions for performance improvement
in ultrascaled (sub 10 nm) Si-nanowire transistors,‖ IEEE Electron Device Lett., vol. 30, no. 2, pp. 195-197, 2009.
[1.16] H. C. Lin, M. F. Wang, F. J. Hou, H. N. Lin, C. Y. Lu, J. T. Liu, and T. Y. Huang,
―High-performance p-channel Schottky-barrier SOI FinFET featuring self-aligned PtSi source/drain and electrical junctions,‖ IEEE Electron Device Lett., vol. 24, no. 2, pp. 102-104, 2003.
[1.17] Martensson, P. Carlberg, M. Borgstroem, L. Montelius, W. Seifert, and L.
Samuelson, ―Nanowire arrays defined by nanoimprint lithography,‖ Nano Lett., vol. 4, no. 4, pp. 699-702, 2004.
[1.18] H. C. Lin, M. H. Lee, C. J. Su, T. Y. Huang, C. C. Lee, and Y. S. Yang,“A simple and low-cost method to fabricate TFTs with poly-Si nanowire channel,‖
IEEE Electron Device Lett., vol. 26, no. 9, pp. 643-645, 2005.
[1.19] C. J. Su, H. C. Lin, and T. Y. Huang, ―High performance TFTs with Si nanowire channels enhanced by metal-induced lateral crystallization,‖ IEEE Electron Device Lett., vol. 27, no. 7, pp. 582-584, 2006.
[1.20] H. C. Lin, H. H. Hsu, C. J. Su, and T. Y. Huang, ―A novel multiple-gate polycrystalline silicon nanowire transistor featuring an inverse-T gate,‖ IEEE Electron Device Lett., vol. 29, no. 7, pp. 718-720, 2008.
[1.21] H. C. Lin, W. C. Chen, C. D. Lin, and T. Y. Huang, ―Performance enhancement in double-gated poly-Si nanowire transistors with reduced nanowire channel thickness,‖ IEEE Electron Device Lett., vol. 30, no. 6, pp. 644-646, 2009.
[1.22] H. H. Hsu, H. C. Lin, C. W. Luo, C. J. Su, and T. Y. Huang, ―Impacts of multiple-gated configuration on the characteristics of poly-Si nanowire SONOS devices,‖ IEEE Trans. Electron Devices, vol. 58, no. 3, pp. 641-649, 2011.
[1.23] H. H. Hsu, H. C. Lin, and T. Y. Huang, ―Origins of performance enhancement in independent double-gated poly-Si nanowire devices,‖ IEEE Trans. Electron Devices, vol. 57, no. 4, pp. 905-912, 2010.
[1.24] W. C. Chen, H. C. Lin, Y. C. Chang, C. D. Lin, and T. Y. Huang, ―In-situ doped source/drain for performance enhancement of double-gated poly-Si nanowire transistors,‖ IEEE Trans. Electron Devices, vol. 57, no. 7, pp. 1608-1615, 2010.
[1.25] C. H. Lin, C. H. Hung, C. Y. Hsiao, H. C. Lin, F. H. Ko, and Y. S. Yang,
―Poly-silicon nanowire field-effect transistor for ultrasensitive and label-free detection of pathogenic avian influenza DNA,‖ Biosens. Bioelectron., vol. 24, no. 10, pp. 3019-3024, 2009.
[1.26] W. C. Chen, H. C. Lin, Y. C. Chang, and T. Y. Huang, ―Effects of independent double-gated configuration on polycrystalline-Si nonvolatile memory devices,‖
Appl. Phys. Lett., vol. 95, no. 13, p. 133502, 2009.
[1.27] C. J. Su, T. I. Tsai, Y. L. Liou, Z. M. Lin, H. C. Lin, and T. S. Chao,
―Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels,‖ IEEE Electron Device Lett., vol. 32, no. 4, pp. 521-523, 2011.
[1.28] Y. Taur, ―CMOS design near the limit of scaling,‖ in IBM J. Res. Develop., vol.
46, no. 2.3, pp. 213-222, 2000.
[1.29] T. Skotnicki, G. Merckel, and T. Pedron, ―The voltage-doping transformation: A new approach to the modeling of MOSFET short-channel effects,‖ IEEE Electron Device Lett., vol. 9, no. 3, pp. 109-111, 1988.
[1.30] J. P. Colinge, ―Multi-gate SOI MOSFETs,‖ Solid State Electron., vol. 48, no.
9/10, pp. 897-905, 2004.
[1.31] S. H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, “Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultrathin-oxide nMOSFET’s,” IEEE Electron Device Lett., vol. 18, no. 2, pp.
209-211, 1997.
[1.32] X. Guo and T. P. Ma, “Tunneling leakage current in oxynitride: Dependence on oxygen/nitrogen content,” IEEE Electron Device Lett., vol. 19, no. 6, pp.
207-209, 1998.
[1.33] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-κgate dielectrics:
Current status and materials properties considerations,” J. Appl. Phys., vol. 89, no. 10, pp. 5243-5275, 2001.
[1.34] T. P. Ma, “High-κgate dielectrics for scaled CMOS technology,” in Proc. 6th Int. Conf. Solid-State Integrated-Circuit Technology, 2001, pp. 297-302.
[1.35] E. P. Gusev, D. A. Buchanan, E. Cartier,A. Kumar,D. DiMaria, S. Guha, A.
Callegari, S. Zafar, P. C. Jamison, D. A. Neumayer, M. Copel, M. A. Gribelyuk, H. Okorn-Schmidt, C. D’Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L.-A.
Ragnarsson, P. Ronsheim, K. Rim, R. J. Fleming, A. Mocuta, and A. Ajmera,
“Ultrathin high-κ gate stacks for advanced CMOS devices,” in IEDM Tech.
Dig., 2001, pp. 451-454.
[1.36] W. Tsai, L. Ragnarsson, P.J. Chen, B. Onsia, R.J. Carter, E. Cartier, E. Young, M.
Green, M. Caymax. S.D. Gendt and M. Heyns, “Comparison of sub 1 nm TiN/HfO2 with poly-Si/HfO2 gate stack using scaled chemical oxide interfaces,”
in VLSI Symp. Tech. Dig., 2003, pp. 21-22.
[1.37] W. Tsai, L. A. Ragnarsson, L. Pantisano, P. J. Chen, B. Onsia, T. Schram, E.
Cartier, A. Kerber, E.Young, M. Caymax, S. De Gendt, and M. Heyns,
―Performance comparison of sub 1 nm sputtered TiN/HfO2 nMOS and pMOSFETs,‖ in IEDM Tech. Dig., 2003, pp. 311-314.
[1.38] S. B. Samavedam, L. B. La, J. Smith, S. Dakshina-Murthy, E. Luckowski, J.
Schaeffer, M. Zavala, R. Martin, V. Dhandapani, D. Triyoso, H. H. Tseng, P. J.
Tobin, D. C. Gilmer, C. Hobbs, W. J. Taylor, J. M. Grant, R. I. Hegde, J. Mogab, C. Thomas, P. Abramowitz, M. Moosa, J. Conner, J. Jiang, V. Arunachalam, M.
Sadd, B. Y. Nguyen, and B. White, ―Dual metal gate CMOS with HfO2 gate dielectric,‖ in IEDM Tech. Dig., 2002, pp. 433-436.
[1.39] K. Tsuji, K. Takeuchi, and T. Mogami, ―High performance 50-nm physical gate length pMOSFET’s by using low temperature activation by re-crystallization scheme,‖ in VLSI Symp. Tech. Dig., 1999, pp. 15-16.
[1.40] P. K. Chu, ―Recent developments and applications of plasma immersion ion implantation (PIII),‖ J. Vac. Sci. Technol. B, vol. 22, no. 1, pp. 289-296, 2004.
[1.41] P. K. Chu and C. Chan, ―Applications of plasma immersion ion implantation in microelectronics-A brief review,‖ Surf. Coat. Technol., vol. 136, no. 1-3, pp.
151-156, 2001.
[1.42] S. Thompson, P. Packan, T. Ghani, M. Stettler, M. Alavi, I. Post, S. Tyagi, S.
Ahmed, S. Yang, and M. Bohr, ―Source/drain extension scaling for 0.1 um and below channel length MOSFETs,‖ in VLSI Symp. Tech. Dig., 1998, pp. 132-133.
[1.43] T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M.
Bohr, ―Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors,‖ in VLSI Symp. Tech. Dig., 2000, pp. 174-175.
[1.44] M. J. Van Dort, P. H. Woerlee, A. J. Walker, C. A. H. Juffermans, and H.
Lifka, ―Influence of high substrate doping levels on the threshold voltage and the mobility of deep submicron MOSFET’s,‖ IEEE Trans. Electron Devices, vol.
39, no. 4, pp. 932-838, 1992.
[1.45] T. Sekigawa and Y. Hayashi, ―Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate,‖ Solid State Electron., vol.
27, no. 8-9, pp. 827-828, 1984.
[1.46] D. Hisamoto, T. Kaga, Y. Kawamoto, E. Takeda, ―A fully depleted lean-channel transistor (DELTA)-A novel vertical ultra thin SOI MOSFET,‖ in IEDM Tech. Dig., 1989, pp. 833-836.
[1.47] D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, T. J.
King, J. Bokor, and C. Hu, ―A folded-channel MOSFET for deep-sub-tenth micron era,‖ in IEDM Tech. Dig., 1998, pp. 1032-1034.
[1.48] X. Huang, W. C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E.
Anderson, H. Takeuchi, Y. K. Choi, K. Asano, V. Subramanian, T. J. King, J.
Bokor, and C. Hu, ―Sub 50 nm FinFET: PMOS,‖ in IEDM Tech. Dig., 1999, pp.
67-70.
[1.49] R. Chau, B. Doyle, J. Kavalieros, D. Barlage, A. Murthy, M. Doczy, R.
Arghavani, and S. Datta, ―Advanced depleted-substrate transistors: Single-gate, double-gate and tri-gate,‖ in Ext. Abst. 2002 Int. Conf. Solid State Devices &
Materials, pp. 68-69.
[1.50] B. S. Doyle, S. Datta, M. Doczy, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R.
Rios, and R. Chau, ―High performance fully-depleted tri-gate CMOS transistors,‖ IEEE Electron Device Lett., vol. 24-4, no. 4, pp. 263-265, 2003.
[1.51] F. L. Yang, H. Y. Chen, F. C. Cheng, C. C. Huang, C. Y. Chang, H. K. Chiu, C.
C. Lee, C. C. Chen, H. T. Huang, C. J. Chen, H. J. Tao, Y.C. Yeo, M.S. Liang, nanowire FinFET,‖ in VLSL Symp. Tech. Dig., 2004, pp. 196-197.
[1.53] R. Ritzenthaler, C. Dupre, X. Mescot, O. Faynot, T. Ernst, J.C. Barbe, C. Jahan, L. Brévard, F. Andrieu, S. Deleonibus, and S. Cristoloveanu, ―Mobility behavior in narrow Ω -gate FET devices,‖ in Proc. IEEE International SOI Conf., 2006, pp. 77-78.
[1.54] J. T. Park, J. P. Colinge, and C. H. Diaz, ―Pi-gate SOI MOSFET,‖ IEEE Electron Device Lett., vol. 22, no. 8, pp. 405-406, 2001.
[1.55] J. T. Park and J. P. Colinge, ―Multiple-gate SOI MOSFETs: Device design guidelines,‖ IEEE Trans. Electron Devices, vol. 49, no. 12, pp. 2222-2229, 2002.
[1.56] J. P. Colinge, M. H. Gao, A. R. Rodriguez, H. Maes, and C. Claeys,
―Silicon-on-insulator gate-all-around device,‖ in IEDM Tech. Dig., 1990, pp.
595-598.
[1.57] E. J. Nowak, R. H. Dennard, P. M. Solomon, A. Bryant, O. H. Dokumaci, A.
Kumar, X. Wang, J. B. Johnson, and M. V. Fischetti., ―Silicon CMOS devices beyond scaling,‖ IBM J. Res. Develop., vol. 50, no. 4/5, pp. 339-361, 2006.
[1.58] K. Bourzac, ―How three-dimensional transistor went from lab to fab,‖
Technology Review, MIT Publishing, May 6th (2011).
[1.59] R. H. Yan, A. Ourmazd, and K. F. Lee, ―Scaling the Si MOSFET: From bulk to SOI to bulk,‖ IEEE Trans. Electron Devices, vol. 39, no. 7, pp. 1704-1710, 1992.
[1.60] K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, ―Scaling theory for double-gate SOI MOSFETs,‖ IEEE Trans. Electron Devices, vol. 40, no. 12, pp.
2326-2329, 1993.
[1.61] C. W. Lee, S. R. N. Yun, C. G. Yu, J. T. Park, and J. P. Colinge, ―Device design guidelines for nano-scale MuGFETs,‖ Solid State Electron., vol. 51, no. 3, pp.
505-510, 2007.
[1.62] A. Burenkov, and J. Lorenz, ―Corner effect in double and triple gate FinFETs,‖
in Proc. ESSDERC, 2003, pp. 135-138.
[1.63] N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H.
Tung, R. Kumar, G. Q. Lo, N. Balasubramanian, and D. L. Kwong,
―High-performance fully depleted silicon nanowire (diameter ≤ 5nm) gate-all-around CMOS devices,‖ IEEE Electron Device Lett., vol. 27, no. 5, pp.
383-386, 2006.
[1.64] H. J. L. Gossmann, A. Agarwal, T. Parrill, L. M. Rubin, and J. M. Poate, ―On the FinFET extension implant energy,‖ IEEE Trans. Nanotechnol., vol. 2, no. 4, pp.
285-290, 2003.
[1.65] J. Kedzierski, M. Ieong, E. Nowak, T. S. Kanarsky, Y. Zhang, R. Roy, D. Boyd, D. Fried, and H.-S. P. Wong, ―Extension and source/drain design for high-performance FinFET devices,‖ IEEE Trans. Electron. Devices, vol. 50, no.
4, pp. 952-958, 2003.
[1.66] D. Pham, L. Larson, and J. W. Yang, ―FinFET device junction formation challenges,‖ in Proc. Int. Workshop Junction Technol., 2006, pp. 73-77.
[1.67] L. Pelaz, R. Duffy, M. Aboy, L. Marques, P. Lopez, I. Santos, B. J. Pawlak, M.
J. H. van Dal, B. Duriez, T. Merelle, G. Doornbos, N. Collaert, L. Witters, R.
Rooyackers, W. Vandervorst, M. Jurczak, M. Kaiser, R. G. R. Weemaes, J. G.
M. van Berkum, P. Breimer, and R. J. P. Lander, ―Atomistic modeling of
Fuller, J. Chang, L. Chang, R. Muralidhar, A. Yagishita, R. Miller, Q. Ouyang, Y. Zhang, V. K. Paruchuri, H. Bu, B. Doris, M. Takayanagi, W. Haensch, D.
McHerron, J. O’Neill, and K. Ishimaru, ―Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond,‖ in IEDM Tech. Dig., 2009, pp. 1-4.
[1.69] D. Lenoble, K.G. Anil, A. D. Keersgieter, P. Eybens, N. Collaert, R. Rooyackers, S. Brus, P. Zimmerman, M. Goodwin, D. Vanhaeren, W. Vandervorst, S.
Radovanov, L. Godet, C. Cardinaud, S.Biesemans, T. Skotnicki, and M. Jurczak,
―Enhanced performance of PMOS MUGFET via integration of conformal plasma-doped source/drain extensions,‖ in VLSI Symp. Tech. Dig., 2006, pp.
168-169.
[1.70] Y. Sasaki, K. Okashita, K. Nakamoto, T. Kitaoka, B. Mizuno, and M. Ogura,
―Conformal doping for FinFETs and precise controllable shallow doping for
planar FET manufacturing by a novel B2H6/Helium self-regulatory plasma doping process,‖ in IEDM Tech. Dig., 2008, pp. 917-920.
[1.71] S. Takeuchi, N. D. Nguyen, F. Leys, R. Loo, T. Conard, W. Vandervorst, and M.
Caymax, ―Vapor phase doping with N-type dopant into silicon by atmospheric pressure chemical vapor deposition,‖ ECS Trans., vol. 16, no. 10, pp. 495-502, 2008.
[1.72] C. W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, J. P. Colinge,
―Performance estimation of junctionless multigate transistors,‖ Solid State Electron., vol. 54, no. 2, pp. 97-103, 2010.
[1.73] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy,
―Nanowire transistors without junctions,‖ Nat. Nanotechnol., vol. 5, no. 3, pp.
225-229, 2010.
[1.74] C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J. P. Colinge,
―Junctionless multigate field-effect transistor,‖ Appl. Phys. Lett., vol. 94, no. 5, p.
053511, 2009.
[1.75] J. P. Colinge, C. W. Lee, I. Ferain, N. D. Akhavan, R. Yan, P. Razavi, R. Yu, A.
N. Nazarov, and R. T. Doria, ―Reduced electric field in junctionless transistors,‖
Appl. Phys. Lett., vol. 96, no. 7, p. 073510, 2010.
[1.76] S. Cho, K. R. Kim, B.-G. Park, and I. M. Kang, ―RF performance and small-signal parameter extraction of junctionless silicon nanowire MOSFETs,‖
IEEE Trans. Electron Devices, vol. 58, no. 5, pp. 1388-1396, 2011.
[1.77] S. Cristoloveanu and S. Williams, ―Point-contact pseudo-MOSFET for in-situ characterization of as-grown silicon-on-insulator wafers,‖ IEEE Electron Device
Lett., vol. 13, no. 2, pp. 102-104, 1992.
[1.78] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed. Hoboken, NJ: Wiley-Interscience, 2007.
[1.79] J. P. Colinge, I. Ferain, A. Afzalian, C. W. Lee, and N. D. Akhavan,
―Junctionless nanowire transistor: Complementary metal-oxide-semiconductor without junctions,‖ Science of Advanced Materials, vol. 3, no. 3, pp. 477-482, 2011.
[1.80] H. T. Lue, E. K. Lai, Y. H. Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, S.
Y. Wang, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, and C.-Y. Lu, ―A novel junction-free BE-SONOS NAND flash,‖ in VLSI Symp. Tech. Dig., 2008, pp. 140-141.
[1.81] H. T. Lue, T. H. Hsu, Y. H. Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, S.
Y. Wang, J. Y. Hsieh, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, and C. Y. Lu,
―A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND flash using junction-free buried channel BE-SONOS device,‖ in VLSI Symp. Tech. Dig., pp.
131-132, 2010.
[1.82] S. J. Choi, D. I. Moon, S. Kim, J. H. Ahn, J. S. Lee, J. Y. Kim, and Y. K. Choi,
―Nonvolatile memory by all-around-gate junctionless transistor composed of silicon nanowire on bulk substrate,‖ IEEE Electron Device Lett., vol. 32, no. 5, pp. 1388-1396, 2011.
[1.83] Y. Sun, H. Y. Yu, N. Singh, K. C. Leong, G. Q. Lo, and D. L. Kwong,
―Junctionless vertical-si-nanowire-channel-based SONOS memory with 2-Bit storage per Cell,‖ IEEE Electron Device Lett., vol. 32, no. 6, pp. 725-728, 2011.
[1.84] C. H. Lee, J. Choi, Y. Park, C. Kang, B. I. Choi, H. Kim, H. Oh, and W. S. Lee,
―Highly scalable NAND flash memory with robust immunity to program disturbance using symmetric inversion type source and drain structure,‖ in VLSI Symp. Tech. Dig., 2008, pp. 118-119.
[1.85] Y. Nishi, ―Insulated gate field effect transistor and its manufacturing method,‖
Patent 587527, 1970 (Japan).
[1.86] T. Lepselter and S. M. Sze, ―SB-IGFET: An insulated-gate field-effect transistor using Schottky barrier contacts for source and drain,‖ Proc. IEEE, pp.
1400-1401, 1968.
[1.87] T. Mochizuki and K. D. Wise, ―An n-channel MOSFET with Schottky source and drain,‖ IEEE Electron Device Lett., vol. EDL-5, no. 4, pp. 108-111, 1984.
[1.88] B. Y. Tsui and M. C. Chen, ―A novel process for high-performance Schottky barrier PMOS,‖ J. Electrochem. Soc., vol. 136, no. 5, pp. 1456-1459, 1989.
[1.89] C. J. Koeneke and W. T. Lynch, ―Lightly doped Schottky MOSFET,‖ in IEDM Tech. Dig., 1982, pp. 466-469.
[1.90] J. M. Larson and J. P. Snyder, ―Overview and status of metal S/D Schottky-barrier MOSFET technology,‖ IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1048-1058, 2006.
[1.91] S. J. Choi, J. W. Han, S. Kim, M. G. Jang, J. S. Kim, K. H. Kim, G. S. Lee, J. S.
Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y. K. Choi,“Enhancement of program speed in dopant-segregated Schottky-barrier (DSSB) FinFET SONOS for NAND-type Flash memory,‖ IEEE Electron Device Lett., vol. 30, no. 1, pp.
78-81, 2009.
[1.92] A. W. Topol, D. C. La Tulipe, Jr., L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, and M. Ieong,
―Three-dimensional integrated circuits,‖ IBM J. Res. Develop., vol. 50, no. 4/5, pp. 491-506, 2006.
[1.93] S. Lai, ―Flash memories: Successes and challenges,‖ IBM J. Res. Develop., vol.
52, no. 4/5, pp. 529-535, 2008.
[1.94] G. Atwood, ―Future directions and challenges for ETOX flash memory scaling,‖
IEEE Trans. Device Mater. Rel., vol. 4, no. 3, pp. 301-305, 2004.
[1.95] S. J. Choi, J. W. Han, S. Kim, D. H. Kim, M. G. Jang, J. H. Yang, J. S. Kim, K.
H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J.W. Kim, and Y. K. Choi,
―High speed Flash memory and 1T-DRAM on dopant segregated Schottky barrier (DSSB) FinFET SONOS device for multi-functional SoC applications,‖
in IEDM Tech. Dig., 2008, pp. 1-4.
[1.96] C. H. Shih and J. T. Liang, ―Nonvolatile Schottky barrier multibit cell with source-side injected programming and reverse drain-side hole erasing,‖ IEEE Trans. Electron Devices, vol. 57, no. 8, pp. 1774-1780, 2010.
[1.97] C. H. Shih, S. P. Yeh, J. T. Liang, and Y. X. Luo, ―Source-side injection Schottky barrier Flash memory cells,‖ Semicond. Sci. Technol., vol. 24, no. 2, p.
025013, 2009.
[1.98] J. Knoch and J. Appenzeller, ―Impact of the channel thickness on the performance of SB-MOSFETs,‖ Appl. Phys. Lett., vol. 81, no. 16, pp.
3082-3084, 2002.
[1.99] J. Knoch, M. Zhang, S. Mantl, and J. Appenzeller, ―On the performance of single-gated, ultrathin body SOI Schottky-barrier MOSFETs,‖ IEEE Trans.
Electron Devices, vol. 53, no. 7, pp. 1669-1674, 2006.
[1.100] J. Guo and M. S. Lundstrom, ―A computational study of thin-body, double-gate,
SB-MOSFETs,‖ IEEE Trans. Electron Devices, vol. 49, no. 11, pp. 1897-1902, high performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique,‖ in VLSI Symp. Tech. Dig., 2004, pp. 168-169.
[1.103] G. P. Lousberg, H. Y. Yu, B. Froment, E. Augendre, A. De Keersgieter, A.
Lauwers, M.-F. Li, P. Absil, M. Jurczak, and S. Biesemans,‖ Schottky-barrier height lowering by an increase of the substrate doping in PtSi Schottky barrier source/drain FETs,‖ IEEE Electron Device Lett., vol. 28, no. 2, pp. 123-125, 2007.
[1.104] D. Connelly, C. Faulkner, D. E. Grupp, and J. S. Harris, ―A new route to zero-barrier metal source/drain MOSFETs,‖ IEEE Trans. Nanotechnology, vol. 3, no. 1, pp. 98-104, 2004.
[1.105] J. W. Peng, S. J. Lee, G. C. A. Liang, N. Singh, S. Y. Zhu, G. Q. Lo, and D. L.
Kwong, ―Improved carrier injection in gate-all-around Schottky barrier silicon nanowire field-effect transistors,‖ Appl. Phys. Lett., vol. 93, no. 7, pp.
073503-073503-3, 2008.
[1.106] H. C. Lin, K. L. Yeh, R. G. Huang, C. Y. Lin, and T. Y. Huang, ―Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain extension,‖ IEEE Electron Device Lett., vol. 22, no. 10, pp. 179-181, 2001.
[1.107] L. H. Lin, "Fabrication and characterizations of asymmetric Schottky barrier thin-film transistors and floating gate memory devices," Master Thesis, National Chiao Tung University, 2011, p. 7.
[1.108] W. Y. Choi, B. G. Park, J. D. Lee, and T. J. K. Liu, ―Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,‖ IEEE Electron Device Lett., vol. 28, no. 8, pp. 743-745, 2007.
[1.109] K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, ―I-MOS: A novel semiconductor device with a subthreshold slope lower than kT/q,‖ in IEDM Tech.
Dig., 2002, pp. 289-292.
[1.110] J. R. Davis, A. E. Glacuum, K. Reeson, and P. L. F. Hemment, ―Improved subthreshold characteristics of n-channel SOI transistors,‖ IEEE Trans. Electron Devices, vol. 35, no. 10, pp. 629-633, 1988.
[1.111] A. J. Walker, ―Sub-50-nm dual-gate thin-film transistors for monolithic 3-D Flash,‖ IEEE Trans. Electron Devices, vol. 56, no. 11, pp. 2703-2710, 2009.
[1.112] ISE TCAD Rel. 10.0 Manual," DESSIS, 2004.
Fig. 1-1 Growth mechanism of silicon nanowires by means of vapor-liquid-solid (VLS)
Fig. 1-1 Growth mechanism of silicon nanowires by means of vapor-liquid-solid (VLS)