Chapter 2 Performance Enhancement of Poly-Si Nanowire (NW)
2.6 Summary
In this chapter, the physical mechanism responsible for the output current enhancement of poly-Si TFTs with ultra-thin channel under DG mode of operation is explored experimentally and theoretically under small drain voltage. The experimental data indicate that the potential barriers, which are provoked by the grain boundaries in the granular poly-Si channel, can be more efficiently lowered as the device is operated in DG mode. Such barrier-lowering leads to more efficient thermionic emission and consequently significantly improves output current. In addition to the experimental investigation, this interesting phenomenon is also verified from the theoretical analysis with the aid of a two-dimensional TCAD tool [2.13] and analytical expressions.
References
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.
Fig. 2-1 (a) Stereo view as well as cross-sectional TEM image and (b) top view of the n-type IDG poly-Si NW TFTs investigated in this chapter, featuring two independently-biased gates and rectangular poly-Si NWs.
Fig. 2-2 (a)~(d) Key steps of fabrication flow of the IDG poly-Si NW TFTs investigated in this chapter.
Fig. 2-3 (a) ID-VG and characteristic of the investigated IDG poly-Si NW TFT, featuring poly-Si channel thickness of 20 nm, gate oxide of 14 nm, and gate length of 5
m under SG-1, SG-2, and DG modes of operation. (b) Comparison of the output characteristic under DG mode of operation with the sum of those under SG-1 and SG-2 modes of operation.
(a)
(b)
Lg = 5
m
LG
= 5 m
LG
= 5 m
Fig. 2-4 Extracted VB as a function of gate voltage for the device characterized in Fig.
2-3. The inset shows some of the log(ID) vs. temperature (T) curves for extracting VB. DG mode shows reduced VB as compared with the SG mode.
Fig. 2-5 Simplified 2D schematic illustration of the device applied in 2D TCAD simulation, featuring poly-Si channel thickness of 20 nm, gate oxide of 14 nm as well as gate length of 5m and bamboolike structure corresponding to the granular channel of IDG poly-Si NW TFTs.
Fig. 2-6 The simulated (a) ID-VG and (b) ID-VD characteristics of the IDG poly-Si NW TFT under DG and SG modes of operation. Excellent agreements with those from experimental measurements shown in Fig. 2-3 are obtained.
LG =5 m
LG
= 5 m
Fig. 2-7 The simulated VB values at y = 1, 3, and 5 nm with simulated ID-VG and ID-VD
characteristics shown in Fig. 2-6.
Fig. 2-8 Comparisons of experimental and simulated TEF under DG and SG modes of operation.
Chapter 3
Read Characteristics of Independent Double-Gated (IDG) Poly-Si Nanowire SONOS Devices
3-1 Introduction
Driven by the tremendous increase in the demand of portable electronic products, the non-volatile semiconductor flash memory market dominated by the floating-gate (FG) flash technology has been rapidly growing. However, other potential alternatives such as charge-trapping flash memories have also drawn particular renewed attentions because the minimization of floating-gate cells is strongly limited by the decreasing of gate coupling ratio as well as reliability issues caused by stress-induced leakage current (SILC) or interference of neighboring cells [3.1]~[3.4]. In the charge-trapping flash memory technologies, silicon-oxide-nitride-oxide-silicon (SONOS) scheme has been widely studied and reported [3.5]~[3.6]. Such a scheme adopts the sandwich architecture (i.e., oxide/nitride/oxide) where the nitride layer replaces the FG as the charge storage medium. The discrete and isolated trapping centers provided by the nitride enable a SONOS flash memory device to exhibit a greater immunity against the
catastrophic failure due to the leakage current from a single defect located in the tunneling oxide and, thus, allowing the use of a thinner tunneling oxide [3.7]. In addition, compared to floating-gate flash memories, the reduction of stacking height makes SONOS flash memories less vulnerable to the interference from neighboring cells.
Most of the previous studies adopted a single-crystalline silicon layer as the conduction channel in a SONOS flash memory. However, considering the applications in 3D stackable technologies, the replacement of a single-crystalline silicon channel by a poly-Si one is a preferable choice in terms of the low deposition temperature (typically below 600 ℃). Certainly the potential concern is the inevitable defects contained in the ploy-Si channel. As mentioned in Chapter 2, such an issue can be efficiently addressed by the employment of poly-Si NW channels and MG configurations for more efficient modulation of the potential barriers caused by GB defects in poly-Si channel. In addition, the MG control, such as GAA configuration, can strengthen the electric field at the channel-to-gate dielectric interface and, thus, improve the programming/erasing (P/E) efficiency [3.8]. Although most of previous studies were focused on common MG gate architectures owing to the ease of process, SONOS flash memories featuring IDG configurations have also drawn a lot of attentions [3.9]~[3.10]. It is because the IDG configuration can offer more design flexibility pertaining to the two individually-biased
gates. In addition, it has been demonstrated that the ―read-pass disturb‖ can be
efficiently suppressed in IDG SONOS flash memory if the auxiliary gate (i.e., the one without oxide/nitride/oxide layers to store data) is utilized as the read-passing gate [3.7].
Previously, by modifying the aforementioned novel IDG NW poly-Si TFT (shown in Chapter 2), our group has succeeded in fabricating an IDG poly-Si NW SONOS device, which shows greatly enhanced program/erase (P/E) speed if an appropriate IDG bias condition is applied and the channel is thin enough [3.11].
On the other hand, different read modes can be adopted in an IDG poly-Si NW SONOS device with the two feasible control gates. Nonetheless, their impact on the memory window is still not clear. Therefore, in this chapter, special attention is paid to the operation of different read modes and the impact on memory window. Both theoretical analysis and experimental clarification are conducted to comprehend the above topics. The organization of this chapter is as follows. The three-dimensional architecture of the investigated IDG poly-Si NW SONOS device and the cross-sectional transmission electron microscopic (TEM) image are shown in Sec. 3-2. Next, Section 3-3 introduces the theorectical background of threshold voltage (Vth) as a function of control gate bias in an IDG device. Next, based on that, the model of memory window under two read modes for an IDG SONOS device will be proposed in Sec. 3-4. Next, the experimental verification is provided in Sec. 3-5. Finally, in Sec. 3-5, based on the
analysis done in previous sections, an innovative IDG SONOS flash memory devices suitable for the future three-dimensional stacked flash memory technology is proposed to end Chapter 3.
3-2 Device Structure
The three-dimensional schematic structure as well as cross-sectional transmission electron microscopic (TEM) image and top view of the investigated IDG poly-Si NW SONOS device are shown in Figs. 3-1(a)-(b), respectively. As shown in the figures, its architecture is almost the same as the IDG poly-Si NW TFT investigated in Chapter 2 except for the replacement of the first-gate TEOS oxide by an oxide/nitride/oxide (ONO, 4nm/7nm/7nm) stack. As shown in Figs. 3-1(a) and (b), the IDG poly-Si NW SONOS device features a pair of poly-Si NW channels, gated by two independent control gates. Therefore, such a device can provide two kinds of read mode.
In addition, the cross-sectional TEM image illustrates the rectangular NW channels with extra-thin thickness of 10 nm.
3-3 Effects of Auxiliary Gate Bias on V
thof the IDG Devices
This section introduces the theory governing the effects of the auxiliary gate bias
on the Vth of an n-channel IDG fully-depleted (FD) device driven by the opposite gate of the device. Figure 3-2 schematically depicts the structure of a n-channel IDG FD device.
During measurements, the gate bias applied to the driving gate is swept to obtain the transfer characteristics while a fixed voltage is applied to the auxiliary (or Vth-control, control for short) gate. Figure 3-3 illustrates the simplified Vth characteristics of the device (Vth(dri)) as a function of the control gate bias (VG(con)). According to the theory developed by Lim and Fossum [3.12]~[3.13], the Vth characteristics can be divided into three regions, as indicated in the figure. In regions I and III, the channel surface of the control-gate side are respectively accumulated and inverted. As a consequence, the Vth
of the driving gate is pinned at Vth(dri),acc(con) and Vth(dri),inv(con), respectively, and can be
density in the silicon film, tsi is the thickness of silicon film, kT/q is the thermal energy,
and ni is the intrinsic carrier concentration. In region II, the channel surface of the control-gate side is depleted and the Vth(dri) can be adjusted by the applied VG(con). Boundaries of these regions are at VG(con,acc) and VG(con,inv), which represent the onsets of accumulated and inverted surface of control gate, respectively, and can be expressed as
( , ) ( )
driving gate in region II can be expressed as:
( )
Furthermore, its slope is defined as the body-factor, β, which is expressed as
( )
81
another situation shown in Fig. 3-4, which has two independent gates denoted as gate 1 (G1) and gate 2 (G2), and an amount of negative charges is contained in the gate oxide of G1. Since the two gates can be operated independently, two read modes can be applied. In mode I, the device is driven by G2 while G1 serves as the control gate to adjust Vth(dri). The Vth2(dri)-VG1(con) characteristics in the mode I are shown in Fig. 3-5(a), where the solid and dashed lines are individually related to the cases with and without the aforementioned extra stored charges. Actually, the dashed line is the same as the one shown in Fig. 3-3. As can be seen in the figure, the Vth2(dri)-VG1(con) curve with the extra
charges shows a parallel shift toward positive direction of the applied bias of G1, which severs as the control gate in mode I. This is because of the positive shift of the G1’s
flat-band voltage resulting from the incorporated fixed charges at the gate oxide of G1.
Therefore, based on Eqs. 3-3 and 3-4, the voltages corresponding to the onsets of the accumulated and inverted surface of G1 with negative charges contained in the gate oxide of G1, denoted as V(Q)G1(con,acc) and V(Q)G1(con,inv), can be expressed as [3.14]
1( , ) 1( , )
where tox1, x, and ρ individually denote the oxide thickness of G1, position, and charge density of the charges in the gate oxide of G1. The difference in Vth between the two characteristic curves in Fig. 3-5(a) is defined as the memory window. Due to the right shift caused by the incorporated charges, the memory window operated in the region between points A and B is shown in Fig. 3-5(b), which shows a linear relation with respective to the bias of control gate (VG1). In addition, its slope is determined by the body-factor β (Eq. 3-6). Therefore, the memory window can be expressed as
1 1( , ) driving gate and control gate, respectively. In other words, the roles of G1 and G2 in the mode I are switched in the present case. The Vth1(dri)-VG2(con) characteristics in the mode II are shown in Fig. 3-6(a) where the solid and dashed lines are respectively related to the cases with or without negative charges contained in the gate oxide of G1. It should be noted that the extra fixed charges contained in the gate oxide of G1 have no influence on the surface conditions of channel gated by G2. This means the voltages correspond to the onsets of the accumulated and inverted surface of the channel gated with G2 remain unchanged. However, it indeed affects the threshold voltage as G1 serves as the driving gate. As a result, a parallel shift toward positive direction of the threshold
voltage (y-axis) is observed in Fig. 3-6(a). Furthermore, the associated threshold voltages with negative charges contained in the gate oxide of G1 in the mode II at the onsets of the accumulation and inversion of the channel gated with G2, V(Q)th1(dri),acc2
and V(Q)th1(dri),inv2, respectively, can be expressed as
1( ), 2( ) 1( ), 2( ) Fig. 3-6(b) shows the memory window operated in the region betweens point A and B shown in Fig. 3-6(a) which has no dependence on the gate bias of the control gate which is proportional to the amount of charges incorporated.
3-5 Experimental Verification and Discussion
Next, the aforementioned fabricated IDG poly-Si NW SONOS TFT (Fig. 3-1(a)) is employed to explore the characteristics of the IDG SONOS devices and verify the theoretical model derived in Sec. 3-4. As can be seen in the cross-sectional TEM image
(Fig. 3-1(a)), the poly-Si NW channel is 10 nm in thickness, horizontally sandwiched by two independent gates denoted as the first and the second gates. In the following discussion, for simplicity, the first gate and its gate bias are denoted as the ONO-gate and VG-ONO, respectively, while the second gate and its gate bias as oxide-gate and VG-O,
respectively. The device is programmed and erased using Fowler-Nordheim (FN) tunneling by applying a high gate bias to the ONO-gate while the oxide-gate, source and drain are grounded. As mentioned above, due to the flexibility offered by the IDG configuration, two read modes depending on the choice of driving gate are feasible. The ID-VG characteristics of programmed and erased states measured under modes I and II are shown in Figs. 3-7(a) and (b), respectively. The programming was executed with VG-ONO = 15V and VG-O = 0V for 5msec, and erasing was with VG-ONO = -12V and VG-O = 0V for 20msec. The memory window is defined as the Vth difference between the erased and programmed states. Figure 3-8 shows the results of memory window for the two read modes extracted from the data shown in Figs. 3-7(a) and (b). Figure 3-9 shows the simplified two-dimensional schematic SONOS structure with certain amount of electrons contained in the nitride layer. Detailed device parameters for the analysis are also included. In the figure, Neff is the effective channel doping concentration resulting from the grain-boundary trapping centers in poly-Si film [3.15] and is estimated to be about 5 × 1017 cm-3 [3.16]. The difference of the present structure from that shown in
Fig. 3-4 is the replacement of the gate oxide of G1 by the ONO stack; thus, the analytical form of memory window given in Eq. 3-10 and Eq. 3-14 for mode I and mode II, respectively, can be applied if a modification in the oxide capacitance of G1 is made. The revised form, denoted as effective Cox1, is expressed as
0
where toxt, tN, and toxb are the thicknesses of tunneling oxide, nitride, and blocking oxide, respectively, and N is the nitride dielectric permittivity. As the trapped electrons in the nitride layer shown in Fig. 3-9 is taken into account, Eq. 3-14 can be modified into the following form [3.17] individual memory windows in mode I and II can be calculated. The theoretical results are shown and verified with the experimental data in Fig. 3-8. Since it is well-known that the charge centroid of the trapped electrons in the nitride layer is located close to
the middle of nitride as long as the programming time is sufficiently long. Therefore, the xmean and Qtot used in the above calculation are set to be 3.5 nm and 5 x 1012 cm-2, respectively. As can be seen in Fig. 3-8, the calculated results well describe the measured memory windows extracted from the ID-VG characteristics shown in Figs.
3-7(a) and (b).
3-6 Innovative IDG SONOS Devices
The above theoretical analysis and experimental data indicate that the read operation of an IDG SONOS device prefers the mode with the ONO-gate serving as the driving gate and oxide-gate as the control gate. Such a read mode acquires a memory window which is larger than the other mode and independent of the bias applied to the control gate. Based on these features, we proposed a new SONOS flash structure shown in Fig. 3-10(a). Before describing its major features and advantages, we first review a previous structure developed by Walker [3.9] as shown in Fig. 3-10(b). The cell devices in such a structure also adopt an ONO-gate for charge storage and an oxide-gate underneath the channel. During read operation, the oxide-gates of the cells except for the one to be accessed are applied with a bias (Vread-pass) in order to reduce the parasitic series resistance. Such scheme can eliminate the necessity of applying a high bias to the ONO-gates of the cells neighboring the accessed cell. As a result, read-pass disturb can
be effectively suppressed. One major issue associated with such a structure is the alignment of top ONO-gate and bottom oxide-gate in the cell devices, making the fabrication complicated. Another major issue is the extra areas occupied by the contact holes of the serial bottom oxide-gates. These two issues can be addressed with the because based on the above analysis, the memory window is independent of the Vread-pass applied to the bottom oxide-gate. With the present scheme, the merit of the previous structure shown in Fig. 3-10(b) in eliminating the read-pass disturb can be sustained, while two unique merits can be generated: 1) Easier fabrication due to elimination of the constraints stemmed from the precise alignment of the top and bottom gates, 2) less occupied areas owing to the replacement of the serial contact holes by a common bottom oxide-gate. However, in terms of the application in three-dimensional stackable flash memory technologies, the scheme shown in Fig. 3-10(a) also suffers from the high thermal budget associated with n+ S/D regions. This issue can be addressed by anther new scheme shown in Fig. 3-11(a), where a novel junctionless (J-less) architecture is
adopted to replace the original undoped channel regions by a heavily doped one. As mentioned in Sec. 1-3, a J-less device features heavy and homogeneous doping concentration across source, channel, and drain and, thus, the original concerns related to the high thermal budget can be relaxed. In addition, low-pressure chemical vapor deposition (LPCVD) in-situ doped poly-Si film can be utilized to form such a heavily doped film in the J-less version. Such an implantation-free process can greatly simplify the complexity of device fabrication.
Finally, we briefly summarize some of the additional advantages of the proposed structure shown in Fig. 3-11(a): (i) Similar to the conventional DG structure [3.7][3.18],
Finally, we briefly summarize some of the additional advantages of the proposed structure shown in Fig. 3-11(a): (i) Similar to the conventional DG structure [3.7][3.18],