Experiments

LTPS TFTs were fabricated on the glass substrates with top-gate structures. The process

flow of the p-channel LTPS TFT is shown in Figs. 2.2(a) － 2.2(g). First, a 400-Å amorphous-Si layer was deposited by a plasma-enhanced chemical-vapor deposition (PECVD) system on a buffer layer and crystallized into a poly-Si film through excimer laser annealing. After defining the active region, the gate dielectric of the 1000-Å SiO2 layer was deposited at 300 ^oC. Mo was then deposited at a thickness of 3000 Å and patterned as the gate electrode. Self-aligned source and drain were formed through plasma doping. Following that, hydrogenation was performed with an NH₃ plasma treatment at 300 ^oC to passivate the dangling bonds at the poly-Si/SiO₂ interface and in the grain boundaries. A 5000-Å inter-layer dielectric of SiO₂ was then deposited and densified through rapid thermal annealing (RTA) at 700 ^oC for 30 s. The dopants were activated during the densification of the inter-layer dielectric. Finally, after a contact-hole opening, 5000-Å Al was deposited and patterned as the interconnection metal. The channel length (L) and width (W) of the device used in this study were 10 µm and 20 µm, respectively.

During stress, the glass substrate was heated to stress temperatures ranging from 25 ^oC to 150 ^oC. Stress gate biases were ＋15 V as PBTI stress, and ranging from －15 to －30 V as NBTI stress. Source and drain were electrically grounded. The stress was periodically stopped to measure the basic device characteristics, including transfer and output characteristics, to characterize the NBTI effect. All the measurements were taken at stress temperatures.

indicates that PBTI is an important issue for p-channel LTPS TFTs. Besides, during inverter operation, p-channel LTPS TFTs will be subjected to NBTI stress instead of PBTI stress.

Therefore, only NBTI degradation will be discussed below.

2.3.1 Device Degradation Due to NBTI

Figs. 2.4(a) and 2.4(b) show the transfer characteristics and output characteristics of the LTPS TFT under NBTI stress, respectively. The stress was performed at 100 ^oC with a stress gate voltage of －30 V for 1000 s. In Fig. 2.4(a), it is observed that the threshold voltage shifts to the negative direction after the NBTI stress. In addition, the NBTI stress also leads to the performance degradation in the subthreshold swing, field-effect mobility, and drive current. The degradation of the subthreshold swing and field-effect mobility is attributed to the interface-trap-state generation. The drive current of LTPS TFTs can be given in the threshold-voltage (Vth) shift and field-effect mobility (µFE) decrease. Therefore, the reduction of the drive current after NBTI stress can be attributed to the threshold-voltage shift and field-effect mobility degradation. Furthermore, the leakage current also increases after stress which leads to the increase of standby current.

In MOSFETs, the threshold-voltage shift caused by the NBTI stress is generally attributed to the generation of fixed oxide charges and interface trap states [2.4]－[2.7]. In poly-Si TFTs, however, there are many grain boundaries in the channel regions, and the grain boundaries may be degraded under NBTI stress. Therefore, in addition to the generation of fixed oxide charges and interface trap states, we suggest that the threshold-voltage shift in poly-Si TFTs is also attributed to the grain-boundary trap-state creation. The detailed

analysis of the correlation between the grain-boundary trap-state generation and the threshold-voltage shift under NBTI stress will be discussed in the latter section.

2.3.2 Analysis of the Threshold-Voltage Shift

Figs. 2.5(a)－2.5(c) show the dependence of the threshold-voltage shift on the stress time, stress voltage, and stress temperature, respectively. The gate voltage at a specified threshold drain-current (IDS), (W/L) × 10 nA for VDS = －0.1 V, is taken as the threshold voltage. In Fig. 2.5(a), the threshold-voltage shift increases upon increasing the stress time, and it shows a power law dependence on the stress time. It is observed that the threshold-voltage shift slightly fluctuates as a function of the stress time; this is because the magnitude of the threshold-voltage shift under NBTI stress is very small (＜ 0.1 V for short stress time). Actually, the correlation coefficients of the four fitting curves in Fig.

2.5(a) are all above 0.98, which means that the measured data and the fitting curves almost fit together. In Figs. 2.5(b) and 2.5(c), it is found that the NBTI degradation is enhanced at a higher stress voltage or stress temperature, indicating that the NBTI can be electrically and thermally activated.

The behavior of the threshold-voltage shift can be empirically modeled as [2.12]

a kT CVG

E n

th

t e e

V ∝

^{(− / )}

∆

, (Eq. 2.2) where the exponent n approximates from 0.28 to 0.34 in our experimental results, which is similar to the results previously reported for poly-Si TFTs [2.10], [2.11], and bulk MOSFETs

NBTI-degradation mechanism is related to the ionic drift, as shown in Fig. 2.6(a), the threshold voltage should shift to the positive direction, however, this clashed with the experimental results. On the other hand, in some models of charge trapping in gate dielectric [2.14], it is revealed that when the device is under gate bias stress, charges may inject into the gate dielectric and generate extra trap states, leading to the threshold-voltage shift, as shown in Fig. 2.6(b). In our experiments, there are several reasons to explain why the device degradation under NBTI stress was not due to the charge trapping in the gate dielectric. First, if the threshold-voltage shift is caused by the electron injection from the gate into the gate dielectric, the threshold voltage should shift to the positive direction. However, this clashed with the experimental results. Second, if the degradation is caused by the hole injection from the channel to the gate dielectric, the threshold voltage will shift to the positive direction.

This seems consistent with the experimental results. However, the electric field across the gate dielectric (below 3 MV/cm) was not high enough to cause hole injection, and the Fowler

－Nordheim current was undetectable at these bias conditions, as shown in Fig. 2.7.

Therefore, the extra trap-state generation and device instability caused by small currents can be neglected [2.16]. Third, previous studies showed that the threshold-voltage shift caused by the charge-trapping process exhibits exponential dependence on 1/VG and is virtually temperature independent [2.14], [2.15]. If the threshold-voltage shift is caused by charge trapping, it should have the same dependence on the stress gate voltage and stress temperature as in the charge-trapping model. However, the charge-trapping model can’t explain the exponential dependence of the threshold-voltage shift on VG

and 1/T as shown in

Figs. 2.5(b) and 2.5(c), respectively. Finally, the charge-trapping models [2.14] cannot explain the linear fit of the log-log plot of the threshold-voltage shift versus the stress time as shown in Fig. 2.5(a). Therefore, instead of ionic drift or charge trapping in the gate dielectric, we suggest that the threshold-voltage shift caused by NBTI stress is due to the charge defect creation in the gate oxide, and trap-state generation at the poly-Si/SiO interface and in the

grain boundaries. Detailed analysis of the degradation mechanism will be discussed in the later sections.

The lifetimes of the LTPS TFTs are plotted as a function of the stress voltage, with various stress temperatures, as shown in Fig. 2.8. The lifetime is defined as the time taken for the device to reach a threshold-voltage shift of 100 mV under NBTI stress. Obviously, the lifetime degrades upon increasing the stress voltage or temperature because NBTI can be electrically and thermally activated.

2.3.3 Analysis of the Grain-Boundary Trap-State Generation

Due to the grain boundaries in the channel regions, the NBTI-degradation mechanism for LTPS TFTs may be different from MOSFETs. To investigate the effects of grain boundaries in the LTPS TFTs during NBTI stress, the grain-boundary trap-state densities (Ntrap) before and after stress were estimated by the Levinson and Proano method [2.17], [2.18]. Fig. 2.9 exhibits the plots of ln [IDS

/ (V

GS

- V

FB)] versus 1/ (VGS

- V

FB

)

² curves at low

V

DS and high VGS, where the flat-band voltage (VFB) is defined as the gate voltage that yields the minimum drain-current from the transfer characteristic with VDS = －0.1 V. The grain-boundary trap-state density can be determined from the square root of the slope:

Slope q

N

_trap

= C

^OX . (Eq. 2.3)

From Fig. 2.9, it is apparent that the grain-boundary trap-state density increases after NBTI stress, indicating that grain-boundary trap-state generation plays an important role in

stress time at 100 ^oC with various stress voltages. The grain-boundary trap-state density variation, like the threshold-voltage shift, follows a power-law dependence on the stress time with exponents from 0.25 to 0.32, which is similar to the exponent factors extracted from Fig.

2.5(a). In addition, we also examined the dependence of the grain-boundary trap-state density variation on the stress voltage and stress temperature, as shown in Figs. 2.10(b) and 2.10(c). It was found that the grain-boundary trap-state density variation (∆Ntrap) has the same function form as the threshold-voltage shift, which can be represented as:

a kT CVG The parameters n’, Ea

’, C’ under various NBTI stress conditions are shown in Fig. 2.11

and are compared with n, Ea, and C extracted from the threshold-voltage shift. It is worth noting that n’, Ea’, and C’ are similar to n, Ea, and C, respectively; this implies that the grain-boundary trap-state generation and the threshold-voltage shift show the same dependence on the stress time, stress voltage, and stress temperature.

Fig. 2.12 describes the correlation between the grain-boundary trap-state generation and the threshold-voltage shift. As the grain-boundary trap-state density increases, the threshold-voltage shift becomes larger. Both the two physical quantities are closely related, because they have the same dependence as on the stress time, stress voltage, and stress temperature discussed above. Therefore, we have proven that the grain-boundaries trap-state generation is closely related to the NBTI-degradation mechanism for LTPS TFTs.

2.3.4 Analysis of the Interface-Trap-State Generation

In addition to the grain-boundary trap-state generation as discussed above, we suggest that the interface trap states at the poly-Si/SiO2 interface are also generated in the LTPS TFTs during NBTI stress. Figs. 2.13(a) and 2.13(b) reveal the correlation between the degradation of the subthreshold swing, the maximum transconductance, and the threshold-voltage shift.

The generation of interface states is reflected in both the degradation of subthreshold swing and maximum transconductance. Furthermore, it has been reported that the subthreshold swing is more closely related to the trap states located near the mid-gap region (deep states), while the mobility is more associated with the trap states located near the band edge (tail states) [2.19]. The deep states and tail states originate from the dangling bonds and strain bonds, respectively. In addition, the degradation of subthreshold swing is found to be severer than maximum transconductance degradation; accordingly, we suggested NBTI causes the generation of interface states, and the interface state creation is mainly attributed to the formation of dangling bonds.

To correlate the generation of grain-boundary trap states with trap states near the poly-Si/SiO2 interface, the interface-trap-state density must be estimated. By neglecting the depletion capacitance in the active layer, an effective interface-trap-state density (Nit) near the poly-Si/SiO2 interface can be evaluated from the subthreshold swing (S) [2.20]:

 

grain-boundary and interface trap states during NBTI stress are in the same order. Therefore, we have demonstrated that the trap-state generation occurs both in the grain boundaries and at the poly-Si/SiO₂ interface for LTPS TFTs under NBTI stress.

the threshold voltage under various temperatures and passivation voltages. Generally, as the temperature or passivation voltage increases, the recovery of the threshold voltage is enhanced. This confirms that the recovery of the threshold voltage can be thermally and electrically activated. It is worth noting that, as we mentioned earlier, the NBTI degradation can also be thermally and electrically activated. This leads us to speculate that the mechanism of the threshold-voltage recovery is the reverse process of the NBTI degradation, because both of these can be activated thermally and electrically.

Fig. 2.17(a) shows the time dependence of the threshold-voltage shift of the devices during NBTI stress. The shift of the threshold voltage follows a power dependence on the stress time with an exponent from 1/3 to 1/4, and this can be explained by the diffusion-controlled electrochemical reactions. In Fig. 2.17 (b), the threshold-voltage recovery of the devices during the passivation process also follows a power-law dependence on the stress time, with similar exponents as the threshold-voltage shift. Therefore, the mechanism of the passivation process can be interpreted by the reverse of the NBTI-degradation mechanism.

2.3.6 Physical Model of NBTI

In MOSFETs, NBTI degradation has been widely attributed to the generation of fixed oxide charges and interface trap states. In LTPS TFTs, however, our experimental results indicate that grain-boundary trap-state generation must also be considered to clarify the degradation mechanism. The results show that both the threshold-voltage shift and the grain-boundary trap-state generation have almost the same power-law dependence on the stress time. The exponent approximates from 1/3 to 1/4, which is generally explained by the diffusion-controlled electrochemical reactions [2.5], [2.21].

The values of the exponent factor n are slightly larger than those extracted in the NBTI experiments of MOSFETs having SiO gate dielectric (about 0.25). We think there are two

possible reasons to explain this phenomenon. First, the difference may be explained from Table 2.1 proposed by Chakravarthi et al., which shows the effect of different species on fractional time dependence of NBTI evolution for a diffusion-limited system [2.22]. In MOSFETs, the primary degradation mechanism is dominated by the diffusion of a neutral hydrogen species (H^o). Therefore, the exponent is about 0.25 [2.5]. In LTPS TFTs, the larger values of the exponents indicate that the hydrogen species participate in the NBTI reaction may consist of H^o and H^＋. Second, in LTPS TFTs, the gate oxide is deposited by the PECVD system. The quality of the PECVD-deposited SiO₂ is not as good as the thermal-grown SiO₂, thus it is easier for the hydrogen species to diffuse in the PECVD-deposited SiO₂ than in the thermal-grown SiO2. Because NBTI degradation is a diffusion-limited mechanism, therefore, we suggest that the poor quality of PECVD-deposited SiO2 accelerates the diffusion of the hydrogen species and results in larger value of the exponent.

By expanding the model proposed for bulk-Si MOSFETs [2.21], we propose a new model to explain the NBTI-degradation mechanism for LTPS TFTs as shown in Figs. 2.18(a)

－2.18(c). The NBTI-degradation model for LTPS TFTs can be given by the following:

Si₃≡Si－H (interface and grain boundary) ＋ ≡Si－O－Si≡ (gate oxide) Si₃≡Si․ (interface and grain boundary trap states) ＋ O₃≡Si^＋(fixed oxide charge)

＋ O₃≡Si－OH ＋ e^－.

(Eq. 2.6) We assume that the Si dangling bonds at the poly-Si/SiO interface and in the grain

the interface trap states and grain-boundary trap states during NBTI stress are in the same order. The released hydrogen species from the interface and grain boundaries diffuse or drift into the gate oxide and react with it, forming OH groups bounded to oxide Si atoms (O₃≡Si

－OH) and leaving positive fixed oxide charges (O₃≡Si^＋) in the gate oxide. Finally, the hydrogen species diffuse in the gate oxide, becoming a reaction-limiting factor. Besides, the reaction is reversible because the threshold-voltage shift and the threshold-voltage recovery show a similar power-law dependence on the stress time.

2.4 Summary

NBTI of p-channel LTPS TFTs has been studied in this chapter, and we have proven that NBTI is important on the reliability of LTPS TFTs. We found that the threshold voltage, subthreshold swing, field-effect mobility, and drive current of the LTPS TFTs degrade after NBTI stress. The NBTI degradation increases upon increasing the stress temperature and electric field, indicating that NBTI can be thermally and electrically activated. Due to the grain boundaries in the channel regions of LTPS TFTs, the grain-boundary trap-state generation must be considered to explain the NBTI-degradation mechanism. In this study, we have proven that the threshold-voltage shift is closely related to the grain-boundary trap-state generation, because both of these two physical quantities follow almost the same power-law dependence on the stress time; that is, the same exponential dependence on both the stress voltage and on the reciprocal of the ambient temperature. The exponential value of the power-law dependence on the stress time approximates from 1/3 to 1/4, which is explained by the diffusion-controlled electrochemical reactions. The values of the exponent n are slightly larger than those extracted from MOSFETs under NBTI stress. This can be attributed to the different hydrogen species participating in the NBTI degradation or/and poor quality of the PECVD-deposited SiO₂. From the experimental results, we conclude that the NBTI

degradation in LTPS TFTs is caused by the generation of fixed oxide charges, interface trap states, and grain-boundary trap states. Besides, these charges or trap states become passivated as the stress voltage is removed or a positive voltage is applied on the gate, leading to the threshold voltage recovery.The recovery of the NBTI degradation can be explained by the reverse process of the diffusion-controlled electrochemical reactions.

Fig. 2.1 Bias conditions of a CMOS inverter during circuit operations.

p-MOSFET (NBTI)

n-MOSFET (NBTI) V _DD / GND

GND / V _DD

V _DD

NBTI PBTI

Input

Output

(a) Buffer layer deposition on the glass substrate.

(b) Amorphous-Si layer deposition by PECVD.

(c) Crystallization of the amorphous-Si film followed by active region definition.

Glass Substrate Buffer Layer

Glass Buffer Layer Amorphous-Si

Glass Buffer Layer

Poly-Si

(d) Gate dielectric and Mo deposition followed by patterning as the gate electrode.

(e) Self-aligned source and drain dopping followed by hydrogenation.

Glass Buffer Layer

Poly-Si Gate Dielectric

Gate

Glass Buffer Layer

Poly-Si Gate Dielectric

Gate

P

⁺

P

⁺

(f) Inter-layer dielectric deposition and dopant activation.

Glass Buffer Layer

Poly-Si Gate Oxide

Metal Gate

P

⁺

P

⁺

Poly-Si Gate Oxide

Metal Gate

P

⁺

P

⁺

0

Fig. 2.3 Transfer characteristics in the linear scale of the LTPS TFTs before and after 1000 s (a) NBTI stress and (b) PBTI stress with stress voltages of ± 15 V.

1 0^{- 1 4}

0.001 0.01 0.1 1

0.1 1 10 100 1000

V

G

= - 15 V

V

G

= - 20 V

V

G

= - 25 V

V

G

= - 30 V

- V

th

S h ift (V )

Stress Time (s)

W/L = 20um/10um Tem perature = 100

^o

C

Fig. 2.5 (a) Dependence of the threshold-voltage shift on the stress time under various stress conditions.

0.01 0.1 1 10

25

^o

C 50

^o

C 10 0

^o

C 15 0

^o

C

-35 -30

-25 -20

-15 -10

- V

th

S h if t (V )

G ate V o ltag e, V

G

(V )

W /L = 2 0um /10um S tre ss Tim e = 1000 s

Fig. 2.5 (b) Dependence of the threshold-voltage shift on the stress voltage under various stress conditions.

0.01 0.1 1 10

26 28 30 32 34 36 38 40

V

G

= - 15 V, E a ~ 0.13 eV

V

G

= - 20 V, E a ~ 0.14 eV

V

G

= - 25 V, E a ~ 0.14 eV

V

G

= - 30 V, E a ~ 0.16 eV

- V

th

S h if t (V )

1/kT (1/eV )

W /L = 20um /10um S tress Tim e = 10 00 s

Fig. 2.5 (c) Dependence of the threshold-voltage shift on the stress temperature under various stress conditions.

(a)

Metal Gate

Metal Gate (Negative Voltage)

(Negative Voltage)

Electron

Poly-Si Channel

Holes (Inversion) Holes (Inversion) Gate Oxide

Gate Oxide

Poly-Si Channel

10

^-13

10

^-12

10

^-11

10

^-10

-100 -80 -6 0 -40 -2 0 0

G a te C u rr e n t, I

G

( A )

G ate V olta ge, V

G

(V ) F o w ler-N ord h eim C u rren t

M axim u m S tress B ias

Fig. 2.7 Gate current of the LTPS TFT. Fowler－Nordheim current is not prominent at the maximum stress bias of －30 V. Therefore, the extra trap-state generation and device instability caused by small currents can be neglected.

0.1 1 10 10 0 1 0 0 0 10⁴ 10⁵ 10⁶

-35 -30

-2 5 -20

-15 -10

2 5 ^oC 5 0 ^oC 1 0 0 ^oC 1 5 0 ^oC

L if e ti m e @ V

th

S h if t = - 1 0 0 m V ( s )

G ate V o ltag e, V

G

(V )

Fig. 2.8 Dependence of the lifetime on the stress voltage with various stress temperatures.

The lifetime is defined as the time taken to reach a threshold-voltage shift of 100

-15 .8 -15 .6 -15 .4 -15 .2 -15 -14 .8 -14 .6 -14 .4

0.02 0.0 4 0.06 0.08 0.1

inital stres s

ln [ I

DS

/ ( V

GS

- V

FB

) ]

1 / ( V

G S

- V

FB

)

²

(V

^-2

)

S tre ss C o nd itio n T em p eratu re = 10 0 ^oC S tre ss Tim e = 1 0 00 s VG = - 3 0 V

N

tra p

= 5.9x1 0

^{1 1}

c m

^-2

N

trap

= 8.1x10

^{1 1}

c m

^-2

Fig. 2.9 Grain-boundary trap-state density extraction of the LTPS TFT before and after 1000 s NBTI stress at 100 ^oC with a stress voltage of －30 V.

10

⁹

10

¹⁰

10

¹¹

10

¹²

0.1 1 10 100 1000

V

G

= - 15 V V

G

= - 20 V V

G

= - 25 V V

G

= - 30 V

N

trap

G e n e ra ti o n ( c m

-2

)

Stress Tim e (s)

W /L = 20um /10um Tem perature = 100

^o

C

Fig. 2.10 (a) Dependence of the grain-boundary trap-state generation on the stress time under various stress conditions.

1 1 0 10 0 10 00

25

^o

C 50

^o

C 10 0

^o

C 15 0

^o

C

-35 -30

-25 -20

-15 -1 0

N

trap

G e n e rat io n ( % )

G ate V o ltag e, V

G

(V )

W /L = 2 0um /10 um S tre ss Tim e = 10 00 s

Fig. 2.10 (b) Dependence of the grain-boundary trap-state generation on the stress voltage under various stress conditions.

1 10 10 0 1000

26 28 30 32 34 36 38 40

V

_G

= - 15 V, E a ~ 0.1 6 eV V

G

= - 20 V, E a ~ 0.1 4 eV V

G

= - 25 V, E a ~ 0.1 7 eV

V

G

= - 30 V, E a ~ 0.1 6 eV

N

trap

G e n e ra ti o n ( % )

1/kT (1/eV )

W /L = 20um /10 um S tress Tim e = 10 00 s

Fig. 2.10 (c) Dependence of the grain-boundary trap-state generation on the stress temperature under various stress conditions.

0

Fig. 2.11 Comparison of the parameters extracted from the grain-boundary trap-state generation and the threshold-voltage shift.

0 10 20 30 40 50 60 70 80

-1 -0.8

-0.6 -0.4

-0.2 0

2 5

^o

C 5 0

^o

C 1 0 0

^o

C 1 5 0

^o

C

N

trap

G e n e ra ti o n ( % )

V

th

S h ift (V )

S tre ss C o n d itio n S tre ss T im e = 10 00 s V

G

= - 15 ~ - 30 V

Fig. 2.12 Correlation between the grain-boundary trap-state generation and the threshold-voltage shift of the LTPS TFTs after NBTI stress.

0

Fig. 2.13 Correlation between the degradation of the (a) subthreshold swing, (b) maximum transconductance, and the threshold-voltage shift of the LTPS TFTs after 1000 s NBTI stress.

10⁹ 10¹⁰ 10¹¹ 10¹² 10¹³

10⁹ 10¹⁰ 10¹¹ 10¹² 10¹³

25 ^oC 50 ^oC 100 ^oC 150 ^oC

N

it

G e n e ra ti o n ( c m

-2

)

N

trap

G en eration (cm

^-2

)

Fig. 2.14 Correlation between the generation of interface trap states and grain- boundary trap states of the LTPS TFTs after NBTI stress.

0 0.1 0.2 0.3 0.4

0 500 10 00 15 00 2000 25 00 30 00

S ta tic V

G

= - 20 V P assivation V

G

= 0 V P assivation V

G

= 10 V

- V

th

S h if t (V )

S tress Tim e (s)

W /L = 2 0um /20 um Tem perature = 100

^o

C

S tre ss V

G

= - 20 V

S tre ss P assivation S tre ss

Fig. 2.15 Transfer characteristics of the devices under static stressing process and

Fig. 2.15 Transfer characteristics of the devices under static stressing process and

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