Chapter 1 Introduction
1.4 Thesis Organization
This thesis is organized as follow:
In Chapter 1, the overview of LTPS TFTs and some reliability issues are illustrated. The motivation of this thesis is also described.
In Chapter 2, NBTI of p-channel LTPS TFTs is thoroughly studied. In addition to the threshold-voltage shift, the generation of grain-boundary trap states and interface trap states are analyzed. A stressing-passivation-stressing procedure is also used to study the effect of threshold-voltage recovery. From the experimental results, the NBTI-degradation mechanism of LTPS TFTs is identified.
In Chapter 3, a charge-pumping technique is utilized to analyze the NBTI degradation of LTPS TFTs. In addition to the increase of bulk trap states (including interface and grain-boundary trap states), the increase of fixed oxide charges is also extracted. By using this technique, the NBTI-degradation mechanism of LTPS TFTs can be further confirmed
In Chapter 4, n-channel LTPS TFTs designed with different antenna area ratios are used to study the impacts of an antenna effect on the device performance and reliability. Electrical characteristics of the devices were measured to identify the influence of the antenna effect.
Finally, gate-bias stress and hot-carrier stress were used to analyze the degradation of device reliability.
In Chapter 5, the impacts of the antenna effect on the NBTI behaviors are investigated.
NBTI stress was performed on the LTPS TFTs having different antenna area ratios. By extracting the related device parameters, the antenna effect can be demonstrated to enhance the NBTI degradation in LTPS TFTs.
In Chapter 6, a reliability model is proposed which successfully introduces the physical mechanisms of both the NBTI and HCS for p-channel LTPS TFTs. The stress drain bias voltage is introduced into the conventional NBTI degradation model to develop a
Fig. 1.1 Cross-sectional and top views of the first TFT in literature.
(Ref. Weimer, IRE-AICE Device Research Conference, 1961)
Fig. 1.2 Energy band diagrams of the Si substrate showing the occupancy of interface traps and the various charge polarities: an (a) p-type substrate with positive interface trap charges at flatband condition and negative interface trap charges at inversion
Fig. 1.3 Schematic two-dimensional representation of the Si－SiO2 interface, showing (a) the Si3≡Si－H defect, and (b) how this defect may be electrically activated during NBTI stress to form a surface trap , an oxide charge, and a hydroxyl group, that (c) may diffuse in the oxide and be the reaction-limiting factor.
(Ref. Jeppson and Svensson, J. Appl. Phys., 1977)
Si
3≡ ≡ ≡ ≡Si－ － － －H defect
Si
3≡ ≡Si ≡ ≡
․․․․＋ ＋O ＋ ＋
3≡ ≡ ≡ ≡Si
＋＋＋＋＋ ＋ ＋ ＋≡ ≡ ≡ ≡Si－ － －OH －
Diffusing OH-group
Table 1.1 Various types of material damage involved in the semiconductor fabrication.
(Ref. Rakkhit et al., in Proc. IEEE Int. Reliab. Phys. Symp., 1993.)
Material Damage Source Damage
Energetic Particles Creation of Traps and G-R Centers Creation of Defects
Impurity Incorporation Dopant Deactivation Semiconductor
Chemical Reaction Creation of Traps and G-R Centers Defect Generation and Propagation Addition or Removal of Hydrogen Charging Damage
UV Ionization Damage
Creation of Traps Charging Up of Traps Creation of Fixed Charges Gate Oxide
Chemical Reaction Addition or Removal of Hydrogen Creation of Traps
Energetic Particles Roughening of the Interface
Oxide-Semiconductor
Table 1.2 Parameter variations and corresponding possible degradation mechanics.
(Ref. Farmakis et al., IEEE Electron Device Lett., 2001.)
Chapter 2
Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon
Thin-Film Transistors
2.1 Introduction
LTPS TFTs are attracting much research interest for their various applications, such as driver circuits of active matrix liquid crystal displays (AM-LCDs) and active matrix organic light emitting diode displays (AM-OLED). Moreover, due to the high carrier mobility of LTPS TFTs, they have high potential of realizing system on panel (SOP), in which the peripheral drivers can be integrated on the glass substrates to minimize the panel size, improve the reliability and resolution of the displays, yield a light and thin display having a reduced number of connection pins, and reduce the fabrication cost [2.1], [2.2]. For the driving circuit operation, LTPS TFTs must be designed using the CMOS inverter configuration. Unlike the functionality for pixel switching, the peripheral driving circuits operate with a relatively high duty cycle. Accordingly, the p-channel and n-channel TFTs are subjected to negative and positive bias stress, respectively. Fig. 2.1 gives a more detailed picture of the correlated information. It presents the bias conditions of a CMOS inverter for
In p-channel MOSFETs, NBTI has been found to be an important reliability problem which has been widely investigated. The NBTI-degradation in MOSFETs is mainly attributed to the generation of interface trap states and fixed oxide charges, and it can be thermally and electrically activated [2.4]－[2.7]. Besides, it is accepted that degradation partially recovers once stress is removed [2.8], [2.9]. The recovery of the NBTI degradation comes from the reduction of interface trap states and fixed oxide charges. In LTPS TFTs, due to the poor thermal conductivity of the glass substrate and high operation voltage, we suppose that NBTI is important to the reliability of LTPS TFTs. Okuyama et al. have pointed out that the NBTI stress causes a performance degradation in poly-Si TFTs as well as in MOSFETs [2.10], [2.11]. However, the NBTI degradation and the recovery effect have not been thoroughly studied in LTPS TFTs, and the mechanisms are not well known. In addition, we speculate that the NBTI-degradation mechanism in LTPS TFTs, due to grain boundaries in the channel regions, may be different from those in MOSFETs. Some studies have indicated that the NBTI stress on poly-Si TFTs may generate trap states in the grain boundaries [2.11]; however, the correlation between the grain-boundary trap-state generation and the device degradation during NBTI stress in LTPS TFTs has not been well explored.
In this chapter, the instability and mechanism of p-channel LTPS TFTs under NBTI stress have been studied. Positive bias temperature instability (PBTI) is also measured to be compared with the NBTI effect. By measuring and analyzing the transfer and output characteristics before and after NBTI stress under different stress gate voltages and stress temperatures, the NBTI degradation and recovery mechanisms of LTPS TFTs were studied and a new model is proposed to explain the experimental results.
2.2 Experiments
LTPS TFTs were fabricated on the glass substrates with top-gate structures. The process
flow of the p-channel LTPS TFT is shown in Figs. 2.2(a) － 2.2(g). First, a 400-Å amorphous-Si layer was deposited by a plasma-enhanced chemical-vapor deposition (PECVD) system on a buffer layer and crystallized into a poly-Si film through excimer laser annealing. After defining the active region, the gate dielectric of the 1000-Å SiO2 layer was deposited at 300 oC. Mo was then deposited at a thickness of 3000 Å and patterned as the gate electrode. Self-aligned source and drain were formed through plasma doping. Following that, hydrogenation was performed with an NH3 plasma treatment at 300 oC to passivate the dangling bonds at the poly-Si/SiO2 interface and in the grain boundaries. A 5000-Å inter-layer dielectric of SiO2 was then deposited and densified through rapid thermal annealing (RTA) at 700 oC for 30 s. The dopants were activated during the densification of the inter-layer dielectric. Finally, after a contact-hole opening, 5000-Å Al was deposited and patterned as the interconnection metal. The channel length (L) and width (W) of the device used in this study were 10 µm and 20 µm, respectively.
During stress, the glass substrate was heated to stress temperatures ranging from 25 oC to 150 oC. Stress gate biases were ＋15 V as PBTI stress, and ranging from －15 to －30 V as NBTI stress. Source and drain were electrically grounded. The stress was periodically stopped to measure the basic device characteristics, including transfer and output characteristics, to characterize the NBTI effect. All the measurements were taken at stress temperatures.
indicates that PBTI is an important issue for p-channel LTPS TFTs. Besides, during inverter operation, p-channel LTPS TFTs will be subjected to NBTI stress instead of PBTI stress.
Therefore, only NBTI degradation will be discussed below.
2.3.1 Device Degradation Due to NBTI
Figs. 2.4(a) and 2.4(b) show the transfer characteristics and output characteristics of the LTPS TFT under NBTI stress, respectively. The stress was performed at 100 oC with a stress gate voltage of －30 V for 1000 s. In Fig. 2.4(a), it is observed that the threshold voltage shifts to the negative direction after the NBTI stress. In addition, the NBTI stress also leads to the performance degradation in the subthreshold swing, field-effect mobility, and drive current. The degradation of the subthreshold swing and field-effect mobility is attributed to the interface-trap-state generation. The drive current of LTPS TFTs can be given in the threshold-voltage (Vth) shift and field-effect mobility (µFE) decrease. Therefore, the reduction of the drive current after NBTI stress can be attributed to the threshold-voltage shift and field-effect mobility degradation. Furthermore, the leakage current also increases after stress which leads to the increase of standby current.
In MOSFETs, the threshold-voltage shift caused by the NBTI stress is generally attributed to the generation of fixed oxide charges and interface trap states [2.4]－[2.7]. In poly-Si TFTs, however, there are many grain boundaries in the channel regions, and the grain boundaries may be degraded under NBTI stress. Therefore, in addition to the generation of fixed oxide charges and interface trap states, we suggest that the threshold-voltage shift in poly-Si TFTs is also attributed to the grain-boundary trap-state creation. The detailed
analysis of the correlation between the grain-boundary trap-state generation and the threshold-voltage shift under NBTI stress will be discussed in the latter section.
2.3.2 Analysis of the Threshold-Voltage Shift
Figs. 2.5(a)－2.5(c) show the dependence of the threshold-voltage shift on the stress time, stress voltage, and stress temperature, respectively. The gate voltage at a specified threshold drain-current (IDS), (W/L) × 10 nA for VDS = －0.1 V, is taken as the threshold voltage. In Fig. 2.5(a), the threshold-voltage shift increases upon increasing the stress time, and it shows a power law dependence on the stress time. It is observed that the threshold-voltage shift slightly fluctuates as a function of the stress time; this is because the magnitude of the threshold-voltage shift under NBTI stress is very small (＜ 0.1 V for short stress time). Actually, the correlation coefficients of the four fitting curves in Fig.
2.5(a) are all above 0.98, which means that the measured data and the fitting curves almost fit together. In Figs. 2.5(b) and 2.5(c), it is found that the NBTI degradation is enhanced at a higher stress voltage or stress temperature, indicating that the NBTI can be electrically and thermally activated.
The behavior of the threshold-voltage shift can be empirically modeled as [2.12]
a kT CVG
E n
th
t e e
V ∝
(− / )∆
, (Eq. 2.2) where the exponent n approximates from 0.28 to 0.34 in our experimental results, which is similar to the results previously reported for poly-Si TFTs [2.10], [2.11], and bulk MOSFETsNBTI-degradation mechanism is related to the ionic drift, as shown in Fig. 2.6(a), the threshold voltage should shift to the positive direction, however, this clashed with the experimental results. On the other hand, in some models of charge trapping in gate dielectric [2.14], it is revealed that when the device is under gate bias stress, charges may inject into the gate dielectric and generate extra trap states, leading to the threshold-voltage shift, as shown in Fig. 2.6(b). In our experiments, there are several reasons to explain why the device degradation under NBTI stress was not due to the charge trapping in the gate dielectric. First, if the threshold-voltage shift is caused by the electron injection from the gate into the gate dielectric, the threshold voltage should shift to the positive direction. However, this clashed with the experimental results. Second, if the degradation is caused by the hole injection from the channel to the gate dielectric, the threshold voltage will shift to the positive direction.
This seems consistent with the experimental results. However, the electric field across the gate dielectric (below 3 MV/cm) was not high enough to cause hole injection, and the Fowler
－Nordheim current was undetectable at these bias conditions, as shown in Fig. 2.7.
Therefore, the extra trap-state generation and device instability caused by small currents can be neglected [2.16]. Third, previous studies showed that the threshold-voltage shift caused by the charge-trapping process exhibits exponential dependence on 1/VG and is virtually temperature independent [2.14], [2.15]. If the threshold-voltage shift is caused by charge trapping, it should have the same dependence on the stress gate voltage and stress temperature as in the charge-trapping model. However, the charge-trapping model can’t explain the exponential dependence of the threshold-voltage shift on VG
and 1/T as shown in
Figs. 2.5(b) and 2.5(c), respectively. Finally, the charge-trapping models [2.14] cannot explain the linear fit of the log-log plot of the threshold-voltage shift versus the stress time as shown in Fig. 2.5(a). Therefore, instead of ionic drift or charge trapping in the gate dielectric, we suggest that the threshold-voltage shift caused by NBTI stress is due to the charge defect creation in the gate oxide, and trap-state generation at the poly-Si/SiO interface and in thegrain boundaries. Detailed analysis of the degradation mechanism will be discussed in the later sections.
The lifetimes of the LTPS TFTs are plotted as a function of the stress voltage, with various stress temperatures, as shown in Fig. 2.8. The lifetime is defined as the time taken for the device to reach a threshold-voltage shift of 100 mV under NBTI stress. Obviously, the lifetime degrades upon increasing the stress voltage or temperature because NBTI can be electrically and thermally activated.
2.3.3 Analysis of the Grain-Boundary Trap-State Generation
Due to the grain boundaries in the channel regions, the NBTI-degradation mechanism for LTPS TFTs may be different from MOSFETs. To investigate the effects of grain boundaries in the LTPS TFTs during NBTI stress, the grain-boundary trap-state densities (Ntrap) before and after stress were estimated by the Levinson and Proano method [2.17], [2.18]. Fig. 2.9 exhibits the plots of ln [IDS
/ (V
GS- V
FB)] versus 1/ (VGS- V
FB)
2 curves at lowV
DS and high VGS, where the flat-band voltage (VFB) is defined as the gate voltage that yields the minimum drain-current from the transfer characteristic with VDS = －0.1 V. The grain-boundary trap-state density can be determined from the square root of the slope:Slope q
N
trap= C
OX . (Eq. 2.3)From Fig. 2.9, it is apparent that the grain-boundary trap-state density increases after NBTI stress, indicating that grain-boundary trap-state generation plays an important role in
stress time at 100 oC with various stress voltages. The grain-boundary trap-state density variation, like the threshold-voltage shift, follows a power-law dependence on the stress time with exponents from 0.25 to 0.32, which is similar to the exponent factors extracted from Fig.
2.5(a). In addition, we also examined the dependence of the grain-boundary trap-state density variation on the stress voltage and stress temperature, as shown in Figs. 2.10(b) and 2.10(c). It was found that the grain-boundary trap-state density variation (∆Ntrap) has the same function form as the threshold-voltage shift, which can be represented as:
a kT CVG The parameters n’, Ea
’, C’ under various NBTI stress conditions are shown in Fig. 2.11
and are compared with n, Ea, and C extracted from the threshold-voltage shift. It is worth noting that n’, Ea’, and C’ are similar to n, Ea, and C, respectively; this implies that the grain-boundary trap-state generation and the threshold-voltage shift show the same dependence on the stress time, stress voltage, and stress temperature.Fig. 2.12 describes the correlation between the grain-boundary trap-state generation and the threshold-voltage shift. As the grain-boundary trap-state density increases, the threshold-voltage shift becomes larger. Both the two physical quantities are closely related, because they have the same dependence as on the stress time, stress voltage, and stress temperature discussed above. Therefore, we have proven that the grain-boundaries trap-state generation is closely related to the NBTI-degradation mechanism for LTPS TFTs.
2.3.4 Analysis of the Interface-Trap-State Generation
In addition to the grain-boundary trap-state generation as discussed above, we suggest that the interface trap states at the poly-Si/SiO2 interface are also generated in the LTPS TFTs during NBTI stress. Figs. 2.13(a) and 2.13(b) reveal the correlation between the degradation of the subthreshold swing, the maximum transconductance, and the threshold-voltage shift.
The generation of interface states is reflected in both the degradation of subthreshold swing and maximum transconductance. Furthermore, it has been reported that the subthreshold swing is more closely related to the trap states located near the mid-gap region (deep states), while the mobility is more associated with the trap states located near the band edge (tail states) [2.19]. The deep states and tail states originate from the dangling bonds and strain bonds, respectively. In addition, the degradation of subthreshold swing is found to be severer than maximum transconductance degradation; accordingly, we suggested NBTI causes the generation of interface states, and the interface state creation is mainly attributed to the formation of dangling bonds.
To correlate the generation of grain-boundary trap states with trap states near the poly-Si/SiO2 interface, the interface-trap-state density must be estimated. By neglecting the depletion capacitance in the active layer, an effective interface-trap-state density (Nit) near the poly-Si/SiO2 interface can be evaluated from the subthreshold swing (S) [2.20]:
grain-boundary and interface trap states during NBTI stress are in the same order. Therefore, we have demonstrated that the trap-state generation occurs both in the grain boundaries and at the poly-Si/SiO2 interface for LTPS TFTs under NBTI stress.the threshold voltage under various temperatures and passivation voltages. Generally, as the temperature or passivation voltage increases, the recovery of the threshold voltage is enhanced. This confirms that the recovery of the threshold voltage can be thermally and electrically activated. It is worth noting that, as we mentioned earlier, the NBTI degradation can also be thermally and electrically activated. This leads us to speculate that the mechanism of the threshold-voltage recovery is the reverse process of the NBTI degradation, because both of these can be activated thermally and electrically.
Fig. 2.17(a) shows the time dependence of the threshold-voltage shift of the devices during NBTI stress. The shift of the threshold voltage follows a power dependence on the stress time with an exponent from 1/3 to 1/4, and this can be explained by the diffusion-controlled electrochemical reactions. In Fig. 2.17 (b), the threshold-voltage recovery of the devices during the passivation process also follows a power-law dependence on the stress time, with similar exponents as the threshold-voltage shift. Therefore, the mechanism of the passivation process can be interpreted by the reverse of the NBTI-degradation mechanism.
2.3.6 Physical Model of NBTI
In MOSFETs, NBTI degradation has been widely attributed to the generation of fixed oxide charges and interface trap states. In LTPS TFTs, however, our experimental results indicate that grain-boundary trap-state generation must also be considered to clarify the degradation mechanism. The results show that both the threshold-voltage shift and the grain-boundary trap-state generation have almost the same power-law dependence on the stress time. The exponent approximates from 1/3 to 1/4, which is generally explained by the diffusion-controlled electrochemical reactions [2.5], [2.21].
The values of the exponent factor n are slightly larger than those extracted in the NBTI experiments of MOSFETs having SiO gate dielectric (about 0.25). We think there are two
possible reasons to explain this phenomenon. First, the difference may be explained from Table 2.1 proposed by Chakravarthi et al., which shows the effect of different species on fractional time dependence of NBTI evolution for a diffusion-limited system [2.22]. In MOSFETs, the primary degradation mechanism is dominated by the diffusion of a neutral hydrogen species (Ho). Therefore, the exponent is about 0.25 [2.5]. In LTPS TFTs, the larger values of the exponents indicate that the hydrogen species participate in the NBTI reaction may consist of Ho and H＋. Second, in LTPS TFTs, the gate oxide is deposited by the PECVD system. The quality of the PECVD-deposited SiO2 is not as good as the thermal-grown SiO2, thus it is easier for the hydrogen species to diffuse in the PECVD-deposited SiO2 than in the thermal-grown SiO2. Because NBTI degradation is a diffusion-limited mechanism, therefore,
possible reasons to explain this phenomenon. First, the difference may be explained from Table 2.1 proposed by Chakravarthi et al., which shows the effect of different species on fractional time dependence of NBTI evolution for a diffusion-limited system [2.22]. In MOSFETs, the primary degradation mechanism is dominated by the diffusion of a neutral hydrogen species (Ho). Therefore, the exponent is about 0.25 [2.5]. In LTPS TFTs, the larger values of the exponents indicate that the hydrogen species participate in the NBTI reaction may consist of Ho and H＋. Second, in LTPS TFTs, the gate oxide is deposited by the PECVD system. The quality of the PECVD-deposited SiO2 is not as good as the thermal-grown SiO2, thus it is easier for the hydrogen species to diffuse in the PECVD-deposited SiO2 than in the thermal-grown SiO2. Because NBTI degradation is a diffusion-limited mechanism, therefore,