Chapter 3 Analysis of Negative Bias Temperature Instability in Body-Tied
3.3.1 Basic Charge-Pumping-Current Characteristics
Before we analyze the NBTI-degradation mechanism of LTPS TFTs, the basic charge-pumping current characteristics must be identified to optimize the measurement condition. In our experiment, the measurement was performed by varying the pulse base voltage from inversion to accumulation while keeping the amplitude of the pulse constant.
Figs. 3.3－3.10 show the curves of charge-pumping currents and the dependence of the maximum charge-pumping currents and the bulk trap-state density on the measurement conditions, including frequency, pulse amplitude, raising time, falling time, source/drain bias, and duty ratio.
Fig. 3.3(a) shows the charge-pumping current measured with different frequencies. The charge-pumping current gradually increases with the pulse base voltage, then reaches the maximum value and finally gradually decreases. The curve is not as sharp as that seen in MOSFET. This is because the threshold-voltage distribution in the channel of the LTPS TFT is non-uniform due to the grain boundaries [3.16]. Fig. 3.3(b) indicates that the charge-pumping current increases with the frequency of the pulse voltage. However, the measured bulk trap-state density decreases. This may be due to the reduced time for the carrier to fill the trap states. In order to obtain more information of on the bulk trap-state properties, the pulse frequency in our charge-pumping measurement was set to be 100 kHz.
In Figs 3.4(a) and 3.4(b), the charge-pumping current and the measured bulk trap-state density increase with the pulse amplitude. This can be explained by the reduced emission time of electrons (tem, e) and holes (tem, h) as the pulse amplitude increases, as shown in Figs.
3.5(a) and 3.5(b). Furthermore, since only those regions can be sensed where ∆V > ︱Vth－
V
fb︱, increasing the pulse amplitude permits to sense bulk traps further into the source and drain regions [3.22], as shown in Figs. 3.6(a) and 3.6(b). Although a larger value of pulseamplitude is useful to get more information about the bulk trap-state properties, still, a larger range of pulse voltage is required to measure the charge-pumping curve, and this is time-consuming and may result in the recovery of the threshold-voltage shift during NBTI stress. Therefore, the pulse amplitude in our measurement was set to be 1.5 V.
In Figs. 3.7 and 3.8, the charge-pumping current and measured bulk trap-state density decrease as the rising time or falling time increases. This can be explained by the enlarged emission time of electrons (tem, e) or holes (tem, h) as the rising time or falling time increases, as shown in Figs. 3.9(a) and 3.9(b). Although a smaller value of the rising time or falling time is useful to get more information about the bulk trap-state properties, yet Uraoka et al.
have pointed out that a smaller value of the rising time or falling time leads to device degradation in field-effect mobility [3.23]. Therefore, the values of both the rising time and falling time in our charge-pumping measurement were set to be 100 ns.
In Fig. 3.10(a) and 3.10(b), the charge-pumping current and measured bulk trap-state density decrease as the source/drain reverse bias increases. When a reverse bias is applied to the source and drain with respect to the substrate, body effect appears and results in the increase of the threshold voltage (modulus). It therefore limits the scanning into the source/drain regions, and hence decreases the maximum charge-pumping current. Therefore, in order to get more information about the bulk trap-state properties, the values of the reverse source/drain bias in our charge-pumping measurement were set to be －50 mV. Finally, the effect of the duty ratio is shown in Figs. 3.11(a) and 3.11(b). The duty ratio shows a negligible effect on the charge-pumping current and bulk trap-state density. Therefore, the
gate voltage of –20 V for 1000 s. The stress degrades the subthreshold swing and field-effect mobility, indicating that interface trap states were generated [3.24]. The threshold voltage (Vth) also shifts to the negative direction after the stress. The NBTI degradation can be attributed to the generation of bulk trap states (including grain-boundary and interface trap states) and fixed oxide charges. Detailed analysis of these trap-state generations will be discussed below.
Figs. 3.13(a)－3.13(c) show the charge-pumping current before and after 1000 s NBTI under the stress conditions of VG = －15 V at 100 oC, VG = －20 V at 100 oC, and VG = － 15 V at 150 oC, respectively. It is obvious that the charge-pumping current increases after NBTI stress; this directly indicates that bulk trap states are generated during the NBTI stress, and implies that bulk trap-state generation plays an important role in the NBTI-degradation mechanism of LTPS TFTs. In addition, the curve of the charge-pumping current shifts to the negative direction after the stress, and this implies that a net positive charge is clearly generated in the oxide or/and at the interface. As the stress voltage increases from －15 V to
－20 V at 100 oC, the charge-pumping current variation increases from 3.4 % to 8.2 %; as the stress temperature increases from 100 oC to 150 oC under the stress voltage of －15 V, the charge-pumping current variation increases from 3.4 % to 10.3 %. The results confirm that the NBTI degradation becomes more serious as the stress voltage or stress temperature increases.
3.3.3 Analysis of the Bulk Trap-State Generation
Fig. 3.14(a) shows the time dependence of the bulk trap-state density (Nbulk) generation under various stress voltages and stress temperatures. The bulk trap-state density is calculated from the charge-pumping current. The generation of bulk trap states follows a power law dependence on the stress time with an exponent from 0.41 to 0.43. Such a power-law dependency is characteristic of NBTI [3.1], [3.2]. The values of the exponents are
slightly larger than those extracted from the conventional LTPS TFTs as shown in Chapter 1 (from 0.28 to 0.34). This indicates that the body-tied TFT has a faster degradation rate than the conventional TFT under NBTI stress. Fig. 3.2 may be used to explain this phenomenon.
Our body-tied TFT is fabricated through the heavily doped n+ region. When the device is turned on during the NBTI stress, the gate inverts the n+ layer beneath it and the inverted n+ layer is just like the normal p-channel formed beneath the normal gate. When the body tie is grounded, the extra p-layer (the inverted n+ layer) can transport extra holes to the normal poly-Si/SiO2 interface due to the potential drop. Therefore, the extra holes assist more bond dissociation and accelerate the NBTI degradation [3.25].
In addition, the atomic hydrogen model indicates that the release of a neutral hydrogen atom is the primary NBTI-degradation mechanism, which exhibits a power-law dependence on the stress time with an exponent of 0.25. The atomic hydrogen model can be expressed as:
SiH + h+ Si+ + Ho. (Eq. 3.1) On the other hand, the proton model clarifies that proton (H+) participates in the NBTI degradation, in which the exponent approximates from 0.25 to 0.5. The proton model can be expressed as:
SiH + 2h+ Si+ + H+. (Eq. 3.2) In addition to the diffusion component (Ho), the drift component (H+) arises because the charged hydrogen species can also move under the influence of the electric field. Due to the additional drift component, therefore, the value of the exponent is larger than 0.25 [3.26]. In our experiments, we suggest that the extra p-layer (the inverted n+ layer) provides extra holes
equation: where n is the time dependent exponent. The voltage accelerated factor C extracted from Fig.
3.14(b) is between 0.14 and 0.19, which is dependent on the process and independent of the stress voltage [3.27]. The activation energy (Ea) extracted from the Arrhenius plot of Fig.
3.14(c) is between 0.25 to 0.30 eV. Moreover, Figs. 3.14(b) and 3.14(c) show that the bulk trap-state density increases with the stress voltage or stress temperature; this confirms that the bulk trap-state generation induced by NBTI stress can be electrically and thermally activated. Also, the charge trapping model can’t explain the exponential dependence of threshold voltage shift on VG
and 1/T [3.28], [3.29]. Furthermore, the electric field across the
gate dielectric (below 2 MV/cm) was not high enough to cause a hole injection. Therefore, we further confirm that the NBTI degradation in LTPS TFTs is attributed to the diffusion-controlled electrochemical reactions instead of the charge trapping model. Fig. 3.15 presents the correlation between the bulk trap-state density variation and the threshold-voltage shift. These two physical quantities are closely related and show linear relation, and this demonstrates that the bulk trap-state generation attributes to the NBTI degradation in LTPS TFTs.3.3.4 Analysis of the Fixed-Oxide-Charge Generation
In MOSFETs, the NBTI degradation is generally explained by the generation of interface trap states and fixed oxide charges. In LTPS TFTs, because the NBTI degradation can be explained by the diffusion-controlled electrochemical reactions, we can assume that the threshold-voltage shift is caused by the generation of bulk trap-state density (Nbulk) and fixed-oxide-charge density (Nox). Therefore, the threshold-voltage shift (∆Vth) can be simply expressed as:
ox fixed-oxide-charge density can be calculated from the measured threshold-voltage shift and bulk trap-state density generation.
Fig. 3.16(a) shows the time dependence of the fixed-oxide-charge density variation under various stress voltages at 100 oC. It is interesting that the increases of the fixed-oxide-charge density, like the bulk trap-state density, also follows a power law dependence on the stress time. The exponent ranges between 0.35 and 0.50. Besides, the increase of the fixed-oxide-charge density shows an exponential dependence on the stress voltage and reciprocal of the stress temperature. Accordingly, we can express the bulk trap-state density variation with the following equation:
a kT C VG activation energy (Ea
’) extracted from the Arrhenius plot of Fig. 3.16(c) is between 0.26 to
0.35 eV. Fig. 3.17 shows the comparison of the parameters extracted from the bulk trap-state generation and the fixed-oxide-charge generation. The correlation between the increase of fixed-oxide-charge density and the threshold-voltage shift is shown in Fig. 3.18. The increase of fixed-oxide-charge density is closely related to the threshold-voltage shift, implying that the generation of fixed oxide charges also participates in the NBTI degradation in LTPSand the bulk trap-state density. Both the two parameters are close related and show a linear relation. The increases of the fixed-oxide-charge density and the bulk trap-state density are in the same order; therefore, we have demonstrated that the trap-state generation occurs both in the channel bulk region and in the gate dielectric for LTPS TFTs under NBTI stress.
As described in Chapter 2, we introduced a model to explain the NBTI-degradation mechanism for LTPS TFTs by expanding the model proposed for bulk-Si MOSFETs [3.30].
The model can be further explained from the energy band diagram as shown in Fig. 3.20.
The Si dangling bonds in the bulk channel region are assumed to be initially passivated by hydrogen atoms. During NBTI stress, the hydrogen atoms react with the holes and dissociate from the Si atoms, resulting in the generation of bulk trap states. The released hydrogen species, including Ho and H+, diffuse or drift into the gate oxide and react with it, forming OH groups bounded to oxide Si atoms. In the meantime, positive fixed oxide charges were generated in the gate oxide. Finally, the hydrogen species diffuse in the gate oxide, becoming a reaction-limiting factor.
3.4 Summary
For the first time, the charge-pumping technique is utilized to analyze the NBTI-degradation mechanism in LTPS TFTs. The properties of bulk trap states can be directly characterized from the charge-pumping current. In addition, the increase of fixed-oxide-charge density is also extracted. Our results show that the increases of both bulk trap-state density and fixed oxide charges are closely related to the threshold-voltage shift, further confirming that the bulk trap states alone cannot explain the measured threshold-voltage shift, and the fixed oxide charges must be taken into account. In addition, the body-tied LTPS TFTs show a larger value of exponent factor compared to conventional LTPS TFT. This is because that the extra p-layer (inverted n+ layer) provides extra holes to enhance the generation of proton and
leads to the larger value of the exponent factor. Furthermore, experimental results show that the NBTI degradation can be electrically and thermally activated. Therefore, the operation voltage and power consumption have to be well designed and new processes must be developed to suppress the NBTI degradation and to realize SOP.
(a)
(b)
Fig. 3.1 Schematic diagrams illustrating (a) the pulse waveform and (b) the charge- pumping-current curve of a p-channel transistor.
Period
Amplitude (∆V) V
GBV
GPt r t f
I
CPV
GBV
fbV
fbV
th＋ ＋∆V ＋ ＋
V
thAccumulation
Inversion
∆V
No I
CPCP regime No I
CP(a)
(b)
Interface trap states
Grain-boundary trap states
Bulk trap states
Gate
A
B
A B
Gate
∆V
GI
CPV
R= - 50mV
Sub.
Substrate (n
+)
Poly-Si
Grain
Ch a rge P um ping Curre nt, I
CP(nA)
P u ls e B a s e V o lta g e , V
dependence of the maximum charge-pumping current and the bulk trap-state density on the frequency.
C h a rg e P u m p in g C u rr en t, I
cp( n A )
P u ls e B a s e V o lta g e , V
(a)
. (b)
Fig. 3.5 Schematic diagrams of the pulse waveform with (a) a small and (b) a large pulse amplitude. The emission times of both electrons (tem,e) and holes (tem,h) decrease as the pulse amplitude increases.
t r t f
V fb V th
V fb V th t r t f
t em,e t em,h
t em,e t em,h
Gate
Large ∆V
Small ∆V
Contributed to I
CP(more)
Contributed to I
CP(less)
(a)
(b) V
thV
fbV
thV
fb
Ch a rge P um ping Curre n t, I
CP(nA)
P u ls e B a s e V o lta g e , V
dependence of the maximum charge-pumping current and the bulk trap-state density on the rising time.
Ch a rge P u m p in g Curre nt , I
CP(nA)
P u ls e B a s e V o lta g e , V
(a)
(b)
Fig. 3.9 Schematic diagrams of the pulse waveform with (a) a small and (b) a large rising/falling time. The emission times of electrons (tem,e) and holes (tem,h) increase with the rising time and falling time.
t r t f
t r t f
V fb V th
V fb V th
t em,e t em,h
t em,e t em,h
C h a rg e P u m p in g C u rr e n t, I
cp( n A )
P u ls e B a s e V o lta g e , V
C h a rg e P u m p in g C u rr e n t, I
CP( n A )
P u ls e B a s e V o lta g e , V
dependence of the maximum charge-pumping current and the bulk trap-state density on the duty ratio.
0
10
810
910
1010
111 10 100 1000
V
G= - 13 V V
G= - 15 V V
G= - 17 V V
G= - 20 V
N
bulkG e n e ra ti o n ( c m
-2)
Stress Tim e (s)
W /L = 1 0um /10um Tem p erature = 100
oC
Fig. 3.14 (a) Time dependence of the bulk trap-state density generation under various stress voltages at 100 oC.
10
910
1010
11-25 -20
-15 -10
75
oC 100
oC 125
oC 150
oC
N
bulkG e n e ra ti o n ( c m
-2)
Gate Voltage, V
G
(V)
W /L = 10um /10um Stress Tim e = 1000 s
.
Fig. 3.14 (b) Dependence of the bulk trap-state density generation on the stress voltage of the LTPS TFTs under various stress conditions.
10
910
1010
1127 28 29 30 31 32 33 34
V
G= - 13 V V
G= - 15 V V
G= - 17 V V
G= - 20 V
N
bulkG en e rat io n ( c m
-2)
1/kT (1/eV)
W/L = 10um/10um Stress Time = 1000 s
Fig. 3.14 (c) Dependence of the bulk trap-state density variation on the stress temperature of the LTPS TFTs under various stress conditions.
0 1X1010 2X1010 3X1010
-0.5 -0.4
-0.3 -0.2
-0.1 0
75 oC 100 oC 125 oC 150 oC
N
bulkG e n e ra ti o n ( c m
-2)
V
thShift (V)
Stress Condition
VG = - 13, - 15, - 17, - 20 V Stress Tim e = 1000 s
Fig. 3.15 Correlation between the increases of the bulk trap-state density and the threshold-voltage shift.
10
810
910
1010
111 10 100 1000
V
G= - 13 V
V
G= - 15 V
V
G= - 17 V
V
G= - 20 V
N
oxG e n e ra ti o n ( c m
-2)
Stress Tim e (s)
W /L = 10um /10um Tem perature = 100
oC
Fig. 3.16 (a) Time dependence of the variation of fixed-oxide-charge density under various stress voltages at 100 oC.
10
910
1010
1110
12-25 -20
-15 -10
75
oC 100
oC 125
oC 150
oC
N
oxG e n e ra ti o n ( c m
-2)
G ate V oltage, V
G
(V)
W /L = 1 0um /10 um Stre ss Tim e = 1000 s
Fig. 3.16 (b) Dependence of the variation of fixed-oxide-charge density on the stress voltage of the LTPS TFTs under various stress conditions.
10
910
1010
1110
1227 28 29 30 31 32 33 34
V
G= - 13 V V
G= - 15 V V
G= - 17 V V
G= - 20 V
N
oxG e n e ra ti o n ( c m
-2)
1/kT (1/eV)
W /L = 10um/10um Stress Time = 1000 s
Fig. 3.16 (c) Dependence of the variation of fixed-oxide-charge density on the stress temperature of the LTPS TFTs under various stress conditions.
0
0 2X1010 4X1010 6X1010 8X1010
-0.5 -0.4
-0.3 -0.2
-0.1 0
75 oC 100 oC 125 oC 150 oC
N
oxG e n e ra ti o n ( c m
-2)
V
thShift (V)
Stress Condition
VG = - 13, - 15, - 17, - 20 V Stress Tim e = 1000 s
Fig. 3.18 Correlation between the increases of the fixed-oxide-charge density and the threshold-voltage shift.
10
910
1010
1110
910
1010
1175
oC 10 0
oC 12 5
oC 15 0
oC
N
oxGen erat ion (c m
-2)
N
bu lkG en eration (cm
-2)
Fig. 3.19 Correlation between the increases of the fixed-oxide-charge density and the bulk trap-state density.
Fig. 3.20 Energy band diagram of the p-channel LTPS TFT under NBTI stress.
Poly-Si Channel Metal Gate Gate Oxide
Dangling Bonds
Holes (Inversion) Diffusion or Drift of
Hydrogen Species
Fixed Oxide Charge
(Negative Voltage)
Chapter 4
Impacts of the Antenna Effect on Low-Temperature Polycrystalline Silicon Thin-Film Transistors
4.1 Introduction
In the fabrication of very-large-scale integration (VLSI) and poly-Si TFTs, plasma-etching processes are widely adopted to achieve good process repeatability and precise control over the feature sizes in the insulators, semiconductors, and metals. However, the impact of plasma processing on device reliability has been a cause for concern since many reports have highlighted that plasma processing during the VLSI manufacturing, including aluminum etching, poly-silicon etching, and resist ashing, may induce reliability issues such as the degradation of threshold voltage, transconductance, gate leakage current, and oxide reliability [4.1]－[4.4].
When an isolated object comes into contact with plasma, negative charges accumulate very rapidly on the object because electrons are the lightest and hottest particles. This situation leads to the buildup of negative potential, called the floating potential (Vf), with respect to the plasma potential (Vp). The floating potential continues to increase until the net flux of arriving negative charges on the isolated object is equal to the net flux of the positive charges [4.5]. However, plasma non-uniformity leads to a local imbalance between the flux of the positive and negative charges, causing a charge accumulation by the isolated object [4.6]. If a conducting layer is connected to the gate oxide and then subjected to plasma etching, the layer completely covers the wafer during most of the etching process; charges flow through the layer to balance the local non-uniformity of the charge flux such that no
charge accumulates on the layer. When the conducting layer is nearly completely etched, however, the layer eventually becomes discontinuous, leading to the onset of local charge accumulation and damage to the gate oxide [4.7]. In addition, during the over-etching step of the photoresist stripping process, the entire wafer surface is exposed to the plasma, causing charge accumulation on the conducting layer. The charges collected by the conducting layer cause stress to the gate oxide. When the plasma non-uniformity is sufficiently large, and the electric field across the gate oxide exceeds a critical value, electrons inject through the gate oxide via FN tunneling, causing deterioration of the oxide quality and integrity [4.8].The injection process could occur through either substrate injection or gate injection, depending upon the potential distribution at the wafer surface during the plasma process [4.9].
The degree of plasma damage is strongly related to the topography of the gate interconnection. It is reported that plasma damage occurs when the gate electrode is longer [4.10], or when the gate electrode is connected to a longer metal line [4.11]. In addition, the charging effect is amplified by the ratio of the areas of the conducting layer and the gate, the so-called antenna-area ratio (AR). This phenomenon is referred as the antenna effect. For LTPS TFTs, because they have a high potential to be used in the driving circuit, the antenna structure will be very common in circuit layout, and the antenna effect will be an important reliability issue. However, it has only rarely been investigated in LTPS TFTs. Some studies have indicated that the plasma processing may degrade the performance of poly-Si TFTs through such phenomena as crystal damage, exposure damage, radiation damage, and charging damage [4.12], [4.13]; however, the impacts of the antenna effect on the
4.2 Experiments
LTPS TFTs having a lightly-doped drain (LDD) were fabricated on the glass substrates having top-gate structures. The process flow of the n-channel LTPS TFT is shown in Figs. 4.1(a)－4.1(g). A 400-Å amorphous-Si layer was deposited by plasma-enhanced chemical-vapor deposition (PECVD) at 300 oC on a buffer layer, and then crystallized into a poly-Si film by excimer laser annealing. After source and drain formation through plasma doping, the gate dielectric was deposited having 1000-Å SiO2 by PECVD at 300 oC. Mo was deposited having a thickness of 3000 Å and patterned as the gate electrode. After gate formation, an LDD having a length of 1.5 µm was formed by a self-aligned process. Then, 5000-Å SiO2 was deposited as the inter-layer dielectric and densified through rapid thermal annealing (RTA) at 700 oC for 30 s. The dopants were also activated during the densification process. Finally, after contact-hole opening, 5000-Å Al was deposited and patterned as the interconnection metal.
The antenna geometry of the test structure is presented in Fig. 4.2, and the antenna-area ratio (AR) is defined as:
W)
To study the effects of the antenna structures on the characteristics of the LTPS TFTs, two sets of antenna patterns were designed; their parameters are detailed in Tables 4.1 and 4.2.
The first series of devices were designed having a fixed channel width (W) and a channel length (L) of 20 µm and 10 µm, respectively; their values of AR were varied from 36 to 1000.
The second series of devices were designed having a fixed AR of 1000, and the channel widths were varied from 5 to 30 µm at a fixed channel length of 5 µm.
4.3 Results and Discussion
4.3.1 Fixed Device Size/Various ARs
There are many device parameters that can be used to check plasma-induced damage, such as the threshold voltage, drive current and gate-leakage current [4.1], [4.2]. In our experiments, we found that the threshold-voltage distribution of the LTPS TFTs displays a clear dependence on the AR, as shown in Fig. 4.3. The threshold-voltage distribution degrades as the AR increases to 1000. When the devices are exposed to plasma, local charges accumulate on the conducting layer and create a voltage across the gate dielectric.
There are many device parameters that can be used to check plasma-induced damage, such as the threshold voltage, drive current and gate-leakage current [4.1], [4.2]. In our experiments, we found that the threshold-voltage distribution of the LTPS TFTs displays a clear dependence on the AR, as shown in Fig. 4.3. The threshold-voltage distribution degrades as the AR increases to 1000. When the devices are exposed to plasma, local charges accumulate on the conducting layer and create a voltage across the gate dielectric.