The power management unit is a very important function block in every different application integrated circuits. Fig. 18 showed the TFT-LCD driver’s power generation unit that is composed of various types of linear regulators and switching capacitor converters. Let us review the power budgets of every function blocks of this work. For a QVGA 240RGB*320 resolution, frame rate 60Hz, the inversion types chooses line inversion as the worst case:
Source driver power consumption: Based on the regular source panel loading ranges from 10pF to 20pF, the source driver output voltage changes from 0.5V to 4.5V.
mA p
IDDVDH_SRC =(240⋅3⋅320)⋅60⋅20 ⋅(4.5−0.5)=1.106 (8)
VCOM driver power consumption: Based on the regular VCOM panel loading ranges from 5nF to 15nF, the VCOM driver output voltage changes from 4V to -1V.
mA 20pF to 40pF, the gate driver output voltage changes from 15V to -10V.
uA
TCON and SRAM power consumption: This item varies with process and various digital functions and typically 1mA to 2mA current budget comes from the VCORE linear regulator.
Vreg1out power consumption: Vreg1out is the reference power of the gamma resistors, normally consumes current less than 50uA, this current comes from DDVDH.
VCOMH power consumption: As Eq. 9 showed, the average current consumption of VCOMH is 0.72mA and this current comes from DDVDH.
VCOML power consumption: As Eq. 9 showed, the average current consumption of VCOML is 0.72mA and this current comes from VCL.
Let’s summarize the current budgets as follow:
DDVDH is generated by CP1 and the current budget is:
mA m
m m
IDDVDH_total =1.106 +0.72 +0.05 =1.876 (11)
VCL is generated by CP4 and the current budget is:
mA
IVCL_total =0.72 (12)
VGH and VGL is generated by CP23 and the current budget is:
uA
IVGH_total =19.2 (13)
uA IVGL_total =19.2
In Fig. 20, the conventional dual side CP1 use two flying capacitors to generate DDVDH, and the conventional dual side CP4 use two flying capacitors to generate VCL, too. This work proposes a new dual side dual output CP14 as Fig. 20 shows that uses only two flying capacitors to generate DDVDH and VCL.
Fig. 20. New Proposed Dual Side Dual Output Charge Pump
The new proposed method saves two flying capacitors, 4 pin outs and 4 power switches for generating DDVDH and VCL. The IC layout area of the new proposed method saves more than 27% than the traditional method without sacrificing the display quality.
Table III shows several system voltage specifications of the TFT-LCD driver. As
introduced in section 1.2, the source driver, the Vreg1out regulator, the VCOMH and the VCOML generator use op-based structure to achieve high line regulation performance.
The source drivers are responsible for driving 64 gamma gray levels into the TFT-LCD panel. The voltage steps between each gamma gray levels are not equal because of the gamma correlation of the human eyes. The minimum gamma voltage step is around 15mV and that means if the voltage difference is smaller than 15mV, the human eyes may not be able to recognize the difference of the gamma level. The line regulation of source driver is 0.74mV/V in DDVDH power domain and that means if DDVDH voltage changes abruptly 20.27V, the source driver output voltage will change 15mV. We can figure out if DDVDH voltage changes abruptly 33.33V, the output voltage of Vreg1out regulator will change one step 50mV. Also if DDVDH voltage changes abruptly 7.35V, the output voltage of VCOMH will change one step 25mV. We can come out a summary for DDVDH voltage that the voltage ripple of DDVDH should be smaller than 7.35V to meet the specifications of the source driver, the Vreg1out regulator and the VCOMH voltage generator.
We can also figure out that if VCL voltage changes abruptly 3.65V, the output voltage of VCOML will change one step 25mV. So VCL voltage ripple should be smaller than 3.65V to meet the specification of the VCOML voltage generator.
All of these voltage specifications are listed in TABLE III. From Table III, we can get the maximum output impedance specifications for DDVDH and VCL,
Ω
ROUT DDVDH MAX MIN MIN DDVDH MAX
Ω
The smaller the output impedance, the larger driving ability the voltage converter has.
TABLE III. TFT-LCDDRIVER SYSTEM VOLTAGE SPECIFICATIONS.
Line Regulation Voltage Spec
Source driver 0.74 mV/V (DDVDH) Gamma step Min 15mV
Vreg1out 1.5mV/V (DDVDH) Vreg1out 3.0V~6.0V, step 50mV VCOMH 3.4mV/V (DDVDH) VCOMH 2.7V~5.875V, step 25mV
VCOML 6.85mV/V (VCL) VCOML -2.5V~0V, step 25mV Power Spec
VCI 2.5V~3.6V
DDVDH 4.7V~6.0V, ripple < 1V, max current 2mA ROUT_DDVDH_MAX=150ΩΩΩΩ VCL -2.4V~-3V, ripple < 1V, max current 0.8mA ROUT_VCL_MAX=125ΩΩΩΩ VGH 10V~20V, max current 25uA
VGL -5V~-15V, max current 25uA
Chapter 2
Performance Checking of Switching Capacitor Voltage Converter
With the progress of semiconductor process from submicron meter to deep submicron meter such as 0.35um, 0.25um, 0.18um, 0.13um and even 45nm, the devices are made smaller generation by generation, and the power supply voltage levels for the smaller devices also drop generation by generation for solving power dissipation issues. But some special application ICs such as the electrically erasable programmable read-only memory (EEPROM), the flash memories, the dynamic random access memory (DRAM) and the TFT-LCD drivers need high voltages for normal function operation. Charge pumps have been used to generate voltages higher than the system power supply voltage for these applications. Charge pumps characterized with low EMI (electro magnetic interference), inductor-less, high efficiency larger than 90%, low cost, low profile and compact are often the best choice of the handheld TFT-LCD drivers. The charge pumps have many different topologies [15] [16] [17]. In this chapter, we will introduce the voltage doubler and the voltage inverter. Gaining more insight into the theory of the charge pump is the goal of this chapter. Section 2.1 introduces some basic concepts about the switching capacitor [18], section 2.2 shows the voltage doubler converter and at last, section 2.3 explains the theories of the voltage inverter converter.