Dual Side Dual Output Switching Capacitor Voltage Converter

Circuit Structure and Implementation

Fig. 39 illustrates the proposed dual side dual output voltage doubler. The proposed charge pump is composed of three parts. The CLK_PHASE_GEN circuit generates four phase

clocks to control this charge pump. The LSH_P6V and LSH_N3V transforms the signal voltage level from 3V to 6V domain and to 3V/-3V domain. The POWER SWITCH block contains the power switches needed for this charge pump. This dual side dual output voltage converter utilizes two flying capacitors C₁₁ and C₁₂ to generate small ripple DDVDH voltage and VCL voltage. The flying capacitors C11, C12 and the stabilize capacitors are all external components.

DDVDH/0 + VCI/VCL domain

VCI/0 domain

Fig. 39. Dual Side Dual Output Voltage Converter.

Clock Phase Generation Circuit

Fig. 40 is the clock phase generation circuit of the proposed voltage converter. The clock phase generation circuit is used to generate the charge phases and pump phases for the dual side dual output voltage converter. As in Fig. 40, CLK is the clock signal coming from the TCON. PH_CH is the phase control signal for the charging phases. PH_PU1 is the phase control signal for the pumping phase. PH_PU2 is also the phase control signal for the pumping phase. The internal capacitors C_A and C_B are used to adjust non-overlap timing which prevents from the possible occurring leakage currents during phase change as we mentioned before. As to the DFF, it is used to insert two more inter-leave phases for the dual side dual output voltage converter.

Fig. 40. Clock Phase Generation Circuit.

Fig. 41 shows the simulation results of clock phase generator. The Tnon-overlap is the non-overlap time between the phase1, phase2, phase3 and phase4. With proper design, this non-overlap time can prevent the leakage current when the different phase changes.

There are four phases for the new proposed charge pump. Phase1 and phase3 are responsible for the charging phase. Phase2 is responsible for the pumping phase which pumps

DDVDH or VCL voltage. Phase4 is also responsible for the pumping phase which pumps DDVDH or VCL voltage. Phase 3 and phase 4 are new extra charging and pumping phase clocks for the dual side dual output operation.

Fig. 41. Simulation Result of Clock Phase Generation Circuit.

Power Switches

Fig. 42 illustrates the power switches of the dual side dual output voltage converter with 12 power switches, 8 pin outs and 2 flying capacitors.

The dual side dual output voltage converter is composed of two single side dual output voltage converters. The flying capacitor C11 and 6 power switches M1A, M2A, M3A, M4A, M5A

and M6A realize a single side dual output voltage converter, while the flying capacitor C12 and the other 6 power switches M_1B, M_2B, M_3B, M_4B, M_5B and M_6B realize another single side dual output voltage converter.

Fig. 42. Power Switches of Dual Side Dual Output Voltage Converter.

The 2.8Ω turning on resistance R_DSON of the power switch M_1A is listed in Fig. 42 and we symbolize it as RSWM1A. In the following discussions, we will use RSWMxx as the resistances R_DSON of all other power switches. The resistors R_M1A, R_M2A, R_M3A, R_M4A, R_M5A, RM6A, RM1B, RM2B, RM3B, RM4B, RM5B and RM6B represent the IC layout metal routing resistances between the power switches and DDVDH, VCI, DGND and VCL pin outs. The resistors RitoC11N, RitoC11P, RitoC12N and RitoC12P represent the TFT-LCD panel ITO parasitic resistances of the pin outs C_11N, C_11P, C_12N and C_12P individually. The resistors R_itoVCI, R_itoDGND, RitoDDVDH and RitoVCL represent the TFT-LCD panel ITO parasitic resistances of the pin outs VCI, DGND, DDVDH and VCL individually.

Fig. 43 shows the simulation results of dual side dual output voltage converter. In this simulation, the load currents of both DDVDH and VCL are 2mA. During the phase1 and

phase3, both C11 and C12 are in the charging phase, being connected to VIN. During the phase2, C₁₁ is in the pumping phase, being connected to DDVDH, while C₁₂ is in the pumping phase, being connected to VCL. During the phase4, C11 is in the pumping phase, being connected to VCL, while C₁₂ is in the pumping phase, being connected to DDVDH.

DDVDH VCL C

C

phase1 phase3

phase2 phase4

phase1 phase3

phase2 phase4 I(M

)

I(M

) I(M

) C

C

I(M

) I(M

) I(M

) I(DDVDH)

I(VCL)

Fig. 43. Simulation Results of Dual Side Dual Output Voltage Converter.

Output Loading for DDVDH Only

To simplify and to distinguish the difference of the performance of DDVDH between the conventional doubler and the proposed converter, we are going to discuss the output current loading occurring only at DDVDH. Let’s review the output impedance ROUT and the output

voltage ripple of DDVDH of the dual side dual output voltage converter.

During the phase1 and phase3, both C₁₁ and C₁₂ are in the charging phase, being connected to VIN. As in Fig. 44, the IOUT output current of DDVDH is 2mA. During the phase1 and phase3, a current of I_OUT flows from the VCI pin through M_1A, C₁₁ and M_2A to the DGND pin, and there is also a current of IOUT flows from the VCI pin through M1B, C12 and M_2B to the DGND pin. There is always an rms current of I_OUT flowing through R_{PH1,3A_SW1} and RPH1,3A_SW2 for C11, and RPH1,3B_SW1 and RPH1,3B_SW2 for C12.

DDVDH C_11P C11N

I(M_2A) I(M3A) I(M_6A) C12P

C_12N I(M_2B) I(M_3B) I(M_6B) I(DDVDH)

phase1 phase3

phase2 phase4

phase1 phase3

phase2 phase4

I_OUT 2·I_OUT

I_OUT 2·I_OUT

I_OUT

Fig. 44. Simulation Results of Dual Side Dual Output Voltage Converter: DDVDH only.

During the phase2, C₁₁ is in the pumping phase, being connected to DDVDH, while C₁₂ is in the pumping phase, being connected to VCL. A current of 2IOUT flows from the VCI pin

through M3A, C11 and M4A to the DDVDH pin, and there is also a current of 2IOUT flows from the DGND pin through M_5B, C₁₂ and M_6B to the VCL pin. There is always an rms current of 2IOUT flowing through RPH2A_SW1 and RPH2A_SW2 for C11, and RPH2B_SW1 and RPH2B_SW2 for C12.

During the phase4, C₁₁ is in the pumping phase, being connected to VCL, while C₁₂ is in the pumping phase, being connected to DDVDH. A current of 2IOUT flows from the DGND pin through M_5A, C₁₁ and M_6A to the VCL pin, and there is also a current of 2I_OUT flows from the VCI pin through M3B, C12 and M4B to the DDVDH pin. There is always an rms current of 2I_OUT flowing through R_{PH4A_SW1} and R_{PH4A_SW2} for C₁₁, and R_{PH4B_SW1} and R_{PH4B_SW2} for C₁₂.

Assuming the switching frequency is 40kHz. For C11,

Ω

Ω

For the ROUT of the dual side dual output voltage converter for DDVDH, +

Comparing to TABLE III, Eq. 48, the ROUT of the dual side dual output voltage converter for DDVDH is much smaller than the output impedance specification of DDVDH ROUT_DDVDH_MAX=150Ω. That means the driving ability of the designed dual side dual output voltage converter for DDVDH can meet the need of the TFT-LCD driver.

For the output voltage ripple of the dual side dual output voltage converter for DDVDH, mV

u k m

V_{RIPPLE_DDVDH_dual_output} =2 /(2⋅20 ⋅1 )=50 (49)

Comparing to TABLE III, Eq. 49, the DDVDH output voltage ripple of the dual side dual output voltage converter is much smaller than the output voltage ripple specification 1V.

Output Loading for VCL Only

To simplify and to distinguish the difference of the performance of VCL between the conventional inverter and the proposed converter, we are going to discuss the output current loading occurring only at VCL. Let’s review the output impedance ROUT and the output voltage ripple of VCL of the dual side dual output voltage converter.

During the phase1 and phase3, both C11 and C12 are in the charging phase, being connected to V_IN. As in Fig. 45, the I_OUT output current of VCL is 2mA. During the phase1 and phase3, a current of IOUT flows from the VCI pin through M1A, C11 and M2A to the DGND pin, and there is also a current of I_OUT flows from the VCI pin through M_1B, C₁₂ and M_2B to

the DGND pin. There is always an rms current of IOUT flowing through RPH1,3A_SW1 and R_{PH1,3A_SW2} for C₁₁, and R_{PH1,3B_SW1} and R_{PH1,3B_SW2} for C₁₂.

During the phase2, C11 is in the pumping phase, being connected to DDVDH, while C12

is in the pumping phase, being connected to VCL. A current of 2I_OUT flows from the VCI pin through M3A, C11 and M4A to the DDVDH pin, and there is also a current of 2IOUT flows from the DGND pin through M_5B, C₁₂ and M_6B to the VCL pin. There is always an rms current of 2IOUT flowing through RPH2A_SW1 and RPH2A_SW2 for C11, and RPH2B_SW1 and RPH2B_SW2 for C12.

VCL C11P

C11N

I(M2A) I(M3A) I(M6A) C12P

C12N

I(M2B) I(M3B) I(M6B) I(VCL)

phase1 phase3

phase2 phase4

phase1 phase3

phase2 phase4

IOUT

2·IOUT

IOUT

2·IOUT

IOUT

Fig. 45. Simulation Results of Dual Side Dual Output Voltage Converter: VCL only.

During the phase4, C₁₁ is in the pumping phase, being connected to VCL, while C₁₂ is in the pumping phase, being connected to DDVDH. A current of 2IOUT flows from the DGND

pin through M5A, C11 and M6A to the VCL pin, and there is also a current of 2IOUT flows from the VCI pin through M_3B, C₁₂ and M_4B to the DDVDH pin. There is always an rms current of 2IOUT flowing through RPH4A_SW1 and RPH4A_SW2 for C11, and RPH4B_SW1 and RPH4B_SW2 for C12.

Assuming the switching frequency is 40kHz. For C₁₁,

Ω

For the R_OUT of the dual side dual output voltage converter for VCL, from Eq. 46 and 47,

+

Comparing to TABLE III, Eq. 52, the R_OUT of the dual side dual output voltage converter for VCL is much smaller than the output impedance specification of VCL ROUT_VCL_MAX=125Ω. That means the driving ability of the designed dual side dual output voltage converter for VCL can meet the need of the TFT-LCD driver.

For the output voltage ripple of the dual side dual output voltage converter for VCL, mV output voltage converter is much smaller than the output voltage ripple specification 1V.

3.2.2 Comparisons of Conventional and Proposed Voltage