The basic mechanisms of the program and erase are related to the carriers transport through tunnel oxide. In early years, several carrier transport mechanisms such as channel hot electron injection (CHEI) [3-7], Fowler-Nordheim (F-N) tunneling [3-8], direct tunneling (DT) [3-9], and band-to-band tunneling (BTBT) [3-10] have been developed for SONOS operation. Since the channel of our devices is formed by poly-Si, grain boundaries may scatter the electrons when transporting in the channel. Therefore, these electrons are difficult to gain sufficient energy to become hot. As a result, CHEI is not a suitable method for programming operation in our devices. In this study, we therefore employ the F-N tunneling as the method of P/E operations in the poly-Si NW MONOS devices. In programming operation, both source and drain are grounded while a positive voltage is applied to the gate to induce a large electric field across the gate dielectric. Electrons in the channel can tunnel through the thin tunneling oxide and be captured by the traps in the nitride or hafnium oxide layer. Under erasing operation, both source and drain are grounded and a negative voltage is applied to the gate. High electric field causes holes to inject into nitride or the trapped electrons to de-trap from the trapping layer.
In this study, we keep each layer (i.e., blocking oxide, trapping layer, tunneling oxide) in all splits with the same physical thickness rather than the same EOT, since the objective is to study the feasibility of high-κ metal gate technology with GAA nanowire device architecture for nonvolatile memory application. The purpose of growing equal physical thickness of each layer is to enhance the electric field in the tunneling oxide and reduce the electric field in the blocking oxide in the nanowire TAHOS devices, as a consequence of using high dielectric constant materials. Under P/E operation, F-N tunneling is employed as mentioned before. For programming, the
fresh transfer curve will be measured first and the programmed transfer curve will be measured subsequently after a programming pulse is applied. The P/E characteristics of TONOS device are taken as examples, as shown in Fig. 3.11. The threshold voltage is extracted by constant current method at a magnitude of 1 nA. Fig. 3.11 (a) depicts the programming results, a 2.1 V memory window can be achieved after a 13 V programming pulse for 100 μs. For the erase operation, we start by programming the device with about 2.5 V shift in Vth first, then use a negative gate bias pulse to erase the devices. Fig. 3.11 (b) depicts an example of erasing a TONOS device, the memory window is about 1.5 V after applying a -11 V/1 ms pulse. The P/E characteristics of the three types of devices are shown in Figs. 3.12, 3.13, and 3.14, respectively. The TAHOS device is the one with its HfO2 grown at 250oC. The influence of deposition temperature will be discussed later. Figs. 3.12 (a), 3.13 (a), and 3.14 (a) depict the Vth shift versus programming time for different stack of GAA NW devices with gate biases of 9 V, 10 V, 11 V, 12 V, 13 V, 14 V and 15 V, respectively. Figs. 3.12 (b), 3.13 (b), and 3.14 (b) depict the Vth shift versus erasing time for different stack of GAA NW devices with gate biases of -9 V, -10 V, -11 V, -12 V, and -13 V, respectively. As shown in the figures, the Vth shift increases when prolonging the operation or increasing the gate bias due to the correspondingly larger F-N tunneling currents. If the target Vth shift is 1 V, the TONOS device requires a 14 V/100 ns pulse condition to reach the specification. For the TANOS device, the bias could be lowered to 12 V while the time duration remains unchanged to reach the same Vth shift. A further enhancement can be achieved by the TAHOS architecture as we predicted.
This phenomenon is desirable for the low power operation in future NVM. The key reason is the reduced EOT which is attributed to the use of high-κ materials. As the band diagrams shown in Fig.3.15, the reduced EOT because of the use of high-κ
blocking oxide and trapping layers causes an enhanced electric field strength across the tunneling oxide and a greater program efficiency. Another reason for the enhancement of programming efficiency is the difference in conduction band offset (ΔEc). The ΔEc between SiO2 and HfO2 is 1.7eV which is larger than that between SiO2 and Si3N4 (1.1 eV). Since we adopt F-N tunneling as the method of P/E operation, the larger ΔEc between tunneling oxide and trapping layer is more favorable for carrier trapping. The programming speed characteristics for three splits of devices with an identical gate bias of 13 V are shown in Fig. 3.16. A strong enhancement of programming efficiency can be gained by adopting Al2O3 as the blocking oxide. Further improvement can be achieved in TAHOS device by the reasons of higher permittivity and trapping sites of HfO2 trapping layer. Under the erasing operation, the smaller EOT of the high-κ layer also enhances the electric field across the tunneling oxide, as can be seen from the band diagrams shown in Figs. 3.17 (a) ~ (c). The erasing speed characteristics for the three types of devices with an identical gate bias of -11 V are shown in Fig. 3.18. The major erasing mechanism of the TONOS and TANOS devices is the electron detrapping rather than the hole injection from the substrate [3-11]. So the slight improvement by adopting Al2O3 as the blocking oxide could be attributed to the higher electric field across the tunneling oxide. One thing should be pointed out is the dramatic enhancement of the TAHOS device. As has been pointed out in the literatures [3-12], the charges are stored close to the Si3N4/Al2O3 interface for the TANOS devices, so the P/E operation is strongly related to the interface properties between trapping layer and blocking oxide. In TAHOS devices, the Al2O3 deposited on the HfO2 tends to be crystallized after annealing, as has been indicated in Fig. 3.4(d), while the interface is also rougher than the Si3N4 /Al2O3 case. By this view point, the excessive charges can be trapped at the
HfO2/Al2O3 surface, so a larger memory window can be achieved.
In this study, TAHOS-NW devices with varying ALD-HfO2 deposition temperature were also fabricated. The deposition temperatures were 100oC, 150oC, 200oC, and 250oC. With the analysis made in the previous section, the trap density only differs slightly among the deposited thin films. The programming and erasing characteristics are shown in Figs. 3.19(a) and (b), respectively. The differences in P/E efficiency among the four devices are very slight. However, we still can observe a rough trend that for the TAHOS device with ALD-HfO2 deposited at a higher temperature, the P/E rate would be retarded owing to the reduced trap density inside the film.