Reliability of the nonvolatile flash memory is a crucial issue for practical application. In this thesis we examine two important topics of reliability, namely, data retention and endurance. Data retention refers to the ability to keep the storage charges in the trapping layer and provide enough memory window so the logic states can be easily distinguished. Generally, a memory window larger than 0.5V after ten years is necessary for commercial products. Fig. 3.20 depicts the migration paths of the trapped charges, including trap-to-band tunneling (path (a)), trap-to-trap tunneling (path (b)), band-to-trap tunneling (path (c)), and thermal excitation (path (d)) [3-13].
The charges can also move from site to site with level inside the bandgap by the Frenkel-Poole emission, especially under the high electric field. The data loss paths mainly occur at the tunneling oxide due to the thinner physical thickness. For faster P/E speed, the tunneling oxide needs to be scaled down, but there’s a trade-off between the P/E speed and the data retention. Under this view point, the adoption of
high-κ materials may help, although it is not investigated in this study. As mentioned in previous section, the physical thickness of the gate dielectric of each split of devices is set the same on purpose for comparison.
Fig. 3.21 depicts the retention characteristics of the fabricated devices. The fresh memory window is all set at a 2-V window. The two nitride-based devices have a comparable predicted memory window after 10-years retention, while the TAHOS device has poorer retention performance. The possible reason for the poorer retention of the TAHOS device is the excessive charges trapped at the shallower traps at the HfO2/Al2O3 interface can easily tunnel through Al2O3 by trap-to-band tunneling. By the abovementioned TEM image, the interface of HfO2/Al2O3 is a little rough, and the crystalline nature of Al2O3 also provides trap sites for leaking out of the stored charges. So the electron can migrate to the shallower trap and tunnel through blocking oxide by trap-assisted tunneling.
Endurance is another important characteristic in NVM applications. Ideally, the program and erase states can stay unchanged after the P/E cycles. Since high voltage is applied during each program/erase operation, the energetic carriers would degrade the tunneling oxide and generate additional oxide and interface traps, resulting in the degeneration of the device performance. These traps can also become the charge loss paths. Fortunately, today the endurance requirement is relaxed from 106 P/E cycles for 128MB density to 104 P/E cycles for 2GB density [3-14]. The endurance characteristics of the TONOS and TAHOS devices are shown in Fig. 3.22. The transfer curves of the two devices recorded at the first and 100th cycles are also provided in Figs. 3.23 (a) and (b), respectively. We can find out that the S.S. of both devices is gravely degraded after the P/E cycles. This is due to the interface state generation during the P/E stress. As the TEM images shown in Fig. 3.4, the NW is
rectangular in shape, so the electric field distribution is non-uniform around the NW.
The electric field is dramatically larger at the corner of NW. This can cause a large amount of interface state generation wherein and increase the S.S. Another phenomenon that should be pointed out is the trend of the window closure found in the TAHOS device, but not in the TONOS devices. The upward shift of the erase state in the TAHOS device can be explained by the accumulation of electrons in deep traps which cannot be easily removed, resulting in an increase in Vth.
3-6 Summary
In this chapter, the applications of high-κ materials, such as HfO2 and Al2O3, to the SONOS-type NVM have been investigated. We studied their electrical properties through simple MOS capacitor and GAA-NW structures. The trap sites in HfO2 are higher than those in Si3N4. The adoption of high-κ layers can also help enhance the P/E efficiency owing to the EOT reduction. Therefore, a lower operation voltage can be achieved to reduce the power consumption of commercial products. We also assessed the reliability properties such as retention and endurance characteristics. It is shown that the replacement of nitride with HfO2 as a storage layer would degrade the reliability performance. Nonetheless, such an issue should be resolvable if the physical thickness of the high-κ materials is further optimized.
Tables
Table 3.1. Film composition of different splits of the MOS capacitors.
Block Oxide Trapping Layer Tunnel Oxide
Table 3.2. Measured accumulation capacitance, CET, and estimated CET.
Cacc CET Estimated CET
Table 3.3. Hysteresis window of the MOS capacitors with different sweeping voltage ranges.
±10 V Hysteresis ±15 V Hysteresis MONOS 1.79 V 1.65 V
Table 3.4. Memory window and the extracted charge density from the results shown in Fig. 3.7.
Window Ncharge MONOS 1.8 V 2.32E+12 cm-2 MANOS 5.3 V 8.56E+12 cm-2 MAHOS-A 8.2 V 1.49E+13 cm-2 MAHOS-B 7.6 V 1.43E+13 cm-2 MAHOS-C 7.2 V 1.39E+13 cm-2 MAHOS-D 6.1 V 1.20E+13 cm-2
Chapter 4 Conclusion and Future Work
4-1 Conclusion
This thesis focuses on the study of properties of high-κ materials and their applications to nonvolatile memory devices with poly-Si NW channels. We utilize the fabrication of top-down NW method without involving advanced lithography technology. In former studies [4-1, 4-2], NW SONOS devices with GAA configuration have been demonstrated to exhibit greatly enhanced P/E efficiency. In this study, we have investigated the properties of high-κ materials such as Al2O3 and HfO2. These materials are further implemented in the NW SONOS-like NVM to enhance the P/E efficiency. For gate dielectric stacks with same physical thickness, the results show that the utilization of the high-κ materials can improve the drive current and S.S. of the devices because of lower EOT. The experimental results also show that the adoption of Al2O3 as the blocking oxide can enhance the electric field across the tunneling oxide and thus fasten the P/E speed. Furthermore, the adoption of HfO2 as the trapping layer can also enhance the P/E efficiency and widen the memory window. The use of high-work-function metal gates suppresses gate electron injection from the gate during erasing. By these results, the NW-TAHOS device can operate at lower voltage and therefore with reduced power consumption. For retention test, the
NW-TAHOS device shows poorer but acceptable memory window at the 10 years prediction. For the endurance test, all devices depict degraded S.S. after some P/E cycles. This is attributed to the rectangular form of the NW. The electric field is stronger at the corners during P/E operation, causing a large amount of interface states generation wherein. For this reason, the degradation in S.S. is not surprising.