Thermally grown SiO2 is usually treated as an ideal dielectric when contacting with the silicon substrate. Actually, the measured electrical characteristics are affected by some positive charges near the silicon/SiO2 interface or trap charges in the bulk oxide. Other types of charges are either positive or negative ones trapped by interface states and mobile ionic charges which are generated during the fabrication process [2-14]. The electrical properties of devices are very sensitive to the interface state density ( D ). The interface states are located at or very close to the it semiconductor/oxide interface with energy distributed along the bandgap of the
semiconductor. These states may trap electrons or holes at the interface and then become charged. All the charged states can be taken as interface charges (Qit). When a high-κ material is used as the gate dielectric, the concern of interface state becomes more important. Moreover, formation of the interfacial layers is usually inevitable when using high-κ materials in semiconductor fabrication because of the existence of high temperature process step in the following manufacturing procedure. When high-κ materials are first introduced, people simply accept such interfacial layer that grows naturally after the deposition of high-κ materials. But in recent years, it has been recognized that high Dit associated with such interfacial layer will seriously aggravate the electrical properties. In line of this, nowadays people are apt to intentionally deposit an interfacial layer with desirable quality before the high-κ film deposition [2-15]. In our experiment, a RTO oxide layer was formed prior to the high-κ film deposition. The forming condition was conducted in O2 (with 10 % N2) atmosphere at 500 oC for 10 s. And then the Dit was extracted by the conductance method with single frequency approximation [2-5]. Just like many data proposed before, the Ditof as-deposited HfO2 is in the order of 1E12 to 1E13 (eV-1cm-2) [2-16].
After the PDA treatment, the Dit decreases significantly [Fig. 2.10]. Although the major gas is N2 during PDA, there still exists approximately 5 % O2 presenting in the chamber. It is possible that the oxygen can diffuse to the interface to improve the interface quality. When the temperature rises from 500 oC to 800 oC, the Dit increases slightly. This may result from the fact that the coefficient of thermal expansion (CTE) of HfO2 (6.5 10 K× −6 −1) [2-17] is much larger than that of SiO2 (0.5 10 K× −6 −1) [2-18]
or Si (2.6 10 K× −6 −1) [2-18]. And another possibility is the diffusion of impurities or defects to this interface [2-19]. Furthermore, the oxygen compensating phenomenon is more obvious for the 5 nm-HfO2 sample annealed at 900 oC for 30 sec, in which the
lowest Ditcan be achieved (6×1011 ev-1cm-2) among all the samples.
As abovementioned, there are many kinds of charges in the oxide or oxide/silicon surface. Owing to the innate high defect density, a transistor with high-κ materials tends to have flat-band voltage shift after forward and backward gate voltage sweeping, which is usually called the hysteresis [2-20]. This phenomenon is undesirable for fundamental logic devices but can be exploited for nonvolatile memory applications because of its capability of trapping charges. Therefore, in order to use HfO2 as the charge trapping layer, we preliminarily investigate the hysteresis characteristics of the HfO2 capacitor samples with three different thicknesses. In the measurement, all the samples were operated with the gate bias sweeping from inversion to accumulation and then backward. The sweeping voltage range is ±3 V.
We found that the hysteresis increases with increasing film thickness, implying that the number of trapping sites increases with film thickness. Next, the influence of PDA will be discussed. From the XRD data, the HfO2 films have shown signs of crystallization even with the low annealing temperature of 500 oC. The hysteresis of the 5 nm and 10 nm as-deposited samples are 132 mV and 518 mV, respectively.
After 500 oC-30 sec PDA treatment, the values increase to 270 mV and 840 mV, respectively [Fig 2.11]. This might be due to the incomplete film crystallization during the PDA process and thus more trapping sites generated at intra/inter grains.
Another interesting thing is that the hysteresis decreases when we further raise the annealing temperature. From the XRD data, some grain orientations disappear as the annealing temperature is higher. This means the grains became larger at the higher annealing temperature. Therefore, some crystalline defects could be significantly repaired during high temperature annealing.
2-5 Summary
In this chapter, fundamental material and electrical characteristics of high–κ materials are studied. We have successfully fabricated and characterized MOS capacitors with HfO2 or Al2O3 dielectric of different thicknesses. The crystallization of HfO2 after high temperature annealing was confirmed by XRD data. For Al2O3 samples, the crystallization-free annealing temperature could be as high as 800 oC without causing a high gate leakage. When the annealing time is extended to 60 sec, the dielectric constant can reach a higher value, suggesting the improved film quality.
On the other hand, the HfO2 samples seem to be more vulnerable to the PDA treatment. Annealing at 500 oC and higher temperatures could reduce the gate leakage significantly owing to more pronounced interfacial layer re-growth for 5 nm-HfO2
samples. But the HfO2 thin films also become crystallized during the annealing and the gate leakage is closely affected by the annealing, especially for the thicker HfO2 samples. Dit and hysteresis effects were also probed to discuss the influence of annealing temperature. Based on these results, we opt for 600 oC/30 sec annealing condition for the high-κ based memory devices and the device characteristics are presented and discussed in Chapter 3.
Tables
Table 2.1. Potential candidates for gate dielectric of future CMOS technology.
κ Band Gap (eV) CB offset (eV)
Table 2.2. Split table for MOS capacitors.
HfO2 Al2O3