The proposed scheme uses memory block concept to design multiple scan chain. By using two-dimensional scan shift control as location indicator, each sub-scan-chain can operate independently in scan-in mode. Figure 4.1 shows the proposed two-dimensional scheme. Combined with the proposed methodology, this test scheme can achieve low test power, small test data volume, and short test time with very little area overhead. Scan control 1 and 2 indicate the sub-scan-chain location.
When the location of the sub-scan-chain is determined, the specific test pattern is shifted from the scan input. While the scan-in operation is performed, the scan-out data are shifted out from the scan output.
Since we need the scan-out data to check the correctness of the chip fabrication, we consider the scan-in test stimulus and the scan-out patterns simultaneously when we encode these test patterns. Because there are many X bits sequences inside the test pattern, we can use scan control to skip the scan-in and scan-out operations.
With the help of scan control, the proposed scheme saves test power, test data volume, and test time simultaneously.
Figure 4.2: The design diagram of the proposed test architecture with routing con-nection details.
Figure 4.2 shows the design details of the proposed scheme. The scan control 1 applies control signals to the control circuit of each sub-scan-chain in each column.
The scan control 2 provides the row bank control signal. Figure 4.3 reveals the control circuit design by logic gates. Scan control 1i in Figure 4.3 (a) connects to the flip-flop signal 1i in Figure 4.3 (b). Scan control 2 uses the same principle to connect to the control signals. From Figure 4.2 and 4.3, we can perceive that the scan input signals will be masked if the control signal does not enable the sub-scan-chain.
4.2.1 Two test modes of the proposed scheme
This scheme has two scan modes: regular scan mode and skipping scan mode. The regular scan mode does not have compression effect. With the skipping scan mode, we can reduce the test data size. The regular scan mode shifts the test pattern from the first sub-scan-chain to the last sub-scan-chain in order. The skipping scan mode shifts the required sub-scan-chain patterns only. Figure 4.4 shows the waveform of the behaviors of the control signals in regular scan mode. Figure 4.5 shows the
Figure 4.3: Circuit design of the proposed architecture. (a) is part of the sub-scan-chain design. (b) presents the details for one scan control sub-scan-chain.
Figure 4.4: Regular scan mode waveform. In regular scan mode, the test patterns are shifted segment-by-segment.
waveform of the behaviors of the control signals in skipping mode. 1 We also reduce many unnecessary shifting operations in skipping scan mode.
The working behavior of the regular scan mode
The first cycle of the regular scan mode and skipping scan mode is the same. Both of the first flip-flop values in the scan control 1 and 2 are reset to 1 to indicate the scan-in data location. From Figure 4.4, test data are shifted into the sub-scan-chain from the scan input during the next 6 cycles and the data inside the sub-scan-chain flip-flops are shifted out from the scan output. The scan control 1 shifts the value
1We need to add 2 bits of control data to deliver the test patterns to the correct sub-scan-chains.
Figure 4.5: Skipping scan mode waveform. The test patterns in skipping mode contain signal control codes which skip the segments with all X bits. In this figure, the 15th cycle and the 16th cycle skip two segments of sub-scan-chains, which can reduce the test cost.
1 from the first flip-flop to the second flip-flop to refer the next sub-scan-chain at the 8th cycle. At the 29th cycle, the first flip-flop value of scan control 1 is set to 1 again and the first flip-flop value of scan control 2 is shifted to the second flip-flop.
These regular operations shift the test patterns into each of the sub-scan-chain.
The working behavior of the skipping scan mode
The skipping mode operation is shown in Figure 4.5. The first flip-flop value of the scan control 1 and 2 is reset to 1. The operations of 15th and 16th cycles shift the flip-flop value of scan control 1 from the second flip-flop to the 4th flip-flop. Due to the five successive skipping control codes, this scheme skips 5 sub-scan-chains from the 23rd cycle to the 27th cycle. The first flip-flop of scan control 1 sets value to 1 and shifts the flip-flop value of scan control 2 from the first flip-flop to the second flip-flop at the 23rd cycle. The flip-flop value of scan control 1 shifts from the first flip-flop to the fourth flip-flop at the 24th, the 25th, and the 26th cycles.
The first flip-flop of scan control 1 value sets to 1 and shifts the flip-flop value of scan control 2 from the second flip-flop to the third flip-flop at the 27th cycle. With these operations, the proposed architecture can skip a lot of unnecessary scan in data.