This section will introduce the optimization methodology on test data and power in VIFO scheme. The methodology consists of scan chain partition and three stages.
Scan chain partition is to divide the original single scan chain to multiple scan chains. The test patterns in the same partition will be processed via the following three stages. The first stage is pattern selection: it sets the X bit omit ratio in order to select the pattern for the CSC. The second stage is pattern compression: it merges the test patterns in the same segment of test sets. The third stage is power optimization stage: it uses shorter pattern length and applies greedy search to find
Figure 2.3: Pattern selection stage. After we get the partitioned test data set, we use X bit omit ratio to determine which test pattern should be put into CSC data set and which test pattern should be put into NSC data set.
the smaller power consumption code in the CSC segment by segment.
2.2.1 Pattern selection stage
This stage separates the test patterns into two groups by the X bit omit ratio. If the test pattern’s X bit ratio is smaller than the given X bit omit ratio, this test pattern will belong to the NSC group, or it will belong to the CSC, as shown in Figure 2.3. SP Lnew is the CSC test data length that comes from compressed scan unit (Figure 2.2). Total original test size in equation (2.1) and total new test size in equation (2.2) are used to calculate the test data volume in Chapter 2 and 3.
Original test sizetotal
= P attern numberorg× SP Lorg...(2.1) N ew test sizetotal
= N SC pattern number × SP Lorg
+CSC pattern number × SP Lnew...(2.2)
Figure 2.4: Pattern selection stage example. This case uses 0.3 as X-bit omit ratio to select the test pattern. (a) is original test pattern set which has 17 test patterns.
(b) is selected patterns for NSC. (c) is selected patterns for CSC.
The example is shown in Figure 2.4. There are 17 patterns in the original test pattern set (Figure 2.4 (a)). If we set the X bit omit ratio as 0.3, we can get 3 patterns in the NSC test data set (Figure 2.4 (b)) and 14 patterns in the CSC test data set (Figure 2.4 (c)).
2.2.2 Pattern compression stage
When the test patterns for the CSC are determined, we use these patterns in the compression stage. In this stage, we attempt to shrink coding size as small as possible. As we explain the process, we use 4 bits as fixed output size. If the original test data length is 21 bits, we divide it into 6 segments. The first step is to compress test patterns from the first segment to the sixth segment. The next step merges patterns in each segment. For instance, this step will merge pattern XX11 and 1XX1 to pattern 1X11. Figure 2.5 shows a simple example. In this example, we use two test patterns to explain the merge process. The first segment of these
Figure 2.5: Pattern compression.
two test patterns can not be merged but the second segment can be merged to 1011.
When the merging procedure is done in each column, we can get the results in Figure 2.6 (a) by replacing all of the Xs with 0.
We define TNC as the total number of compression results. If T N C ≤ 2, the number of cells in compressed scan unit (CSU) is set to 1. This means we can use 1 input bit to control all of the test patterns in the output. If 2 < T N C ≤ 4, the number of cells in CSU is set to 2. When we get a TNC bigger than 8, we will not encode the segment. Figure 2.6 (a) is the compression result and the patterns that come from the CSC test data set in Figure 2.4 (c). Figure 2.6 (a) shows the compression result and all Xs are replaced by 0 on compressed data after the compression process. Each compressed pattern is given a number as an index.
Through the compression procedure, the first and second segment of the compressed test data in Figure 2.6 (a) both need 2 bits to encode the whole segment. The third segment needs 3 bits to encode since the TNC in this segment is 8.
2.2.3 Power optimization stage
After the pattern compression stage, this subsection introduces the power optimiza-tion method to minimize the shift-in power in the CSC. We set the bit before first bit of each pattern to 0 and we apply greedy search method to find the lower power coding. This stage maps new encoded data to the compressed pattern index. We
Figure 2.6: VIFO scheme case in pattern compression and power optimization stages.
We use a 4-bit encoding example to illustrate this approach. This figure shows the results of the merging procedure and all Xs are replaced by 0 after the merging procedure. (a) is the compressed test pattern. (b) shows the index number of each segment. (c) shows the new test data results and the mapping code comes from (b).
(d) shows one test pattern transformation from original test data to new test data.
use the example in Figure 2.6 (b) to explain this mapping. The first segment of Fig-ure 2.6 (b) has 3 different compressed codes. The mapping code and index number can be found in Figure 2.6 (a). By finding all of the possible codes from the first segment to the last segment, we can get the final encoding result for the CSC. The result is shown in Figure 2.6 (c). This stage can finds out the mapping result which has the smallest transition counts. The permutation of 3 bits, with 8 new encoded data, is 40320(8!). The permutation of 2 bits, with 4 new encoded data, is 24(4!).
The optimization method tries to find all the permutations from the first segment to the last segment and decides the minimal switch power encodings. The encoding result becomes new encoded data.
The first pattern in Figure 2.6 (b) shows that 030311 is the index number of the test pattern. This pattern maps to test result 000010100000110001010 and new test
pattern 01000101010. The first 4 bits of the test result is 0000. It comes from the mapping number 0 in Figure 2.6 (b) and first segment of pattern 0000 in Figure 2.6 (a). The 5th to 8th bits of the test result are 1010. It comes from the mapping number 3 in the second column of Figure 2.6 (b) and the second column of pattern 1010 in Figure 2.6 (a). At last, we can get the test result 000010100000110001010.
The new test result for the CSC is shown in Figure 2.6 (c). The new test result comes from the power optimization process. Each row in Figure 2.6 (c) will be shifted into the CSC. Figure 2.6 (d) integrates a pattern result of aforementioned stages.