This section will introduce the FIVO scheme optimization methodology. The method-ology is similar to the previous VIFO scheme. If we apply the multiple scan chain technique, it consists of a scan chain partition and three stages, and the different partitions go through these three steps independently. Otherwise it consists of three stages. The three stages are pattern selection, pattern compression, and power op-timization. Pattern selection is the same with the previous scheme (Section 2.2.1).
Techniques in pattern compression and power optimization are different. We will focus on these two stages in this section. Similarly, all of the test patterns in the same partition go through these three stages.
The first stage is pattern selection, it sets the X bit omit ratio in order to select the pattern for CSC. The second stage is pattern compression, it merges variable length of test patterns in the same segment of test sets. The third stage is power optimization stage, it uses shorter pattern length and applies greedy search to find the smallest power consumption code in the CSC segment by segment.
3.2.1 Pattern compression stage
Figure 3.2: FIVO scheme merge procedure.
Since pattern selection method of the FIVO scheme is the same as the VIFO scheme, we introduce the pattern compression stage in this subsection. This stage contains merging, extending, and maximizing steps as follows.
We use an example of n = 3 to illustrate the procedure in this stage. The first step is to compress test patterns with 3-bit segments from the first bit of the CSC test pattern set. Each 3-bit decoder provides 8 different codes. Each code represents one compressed pattern which is merged from the original test data. For instance, this step will merge pattern X11 and XX1 to pattern X11. Moreover, XX11, X111, 0111 will be merged to code 0111 in the same segment. If the total number of compression results is smaller than 8, it extends the segment to 4 bits.
Until the total number of compression results (TCRS) is maximum but T CRS ≤ 8, the results are encoded to 3 bits in the CSC. The details is shown in Figure 3.2.
The test pattern comes from Figure 2.4 (c). The first step is trying to merge 3 bits and we found that 1 bit is enough. We try to merge 4 bits and the results need 2 bits to encode. If we merge 5 bits, we also needs 2 bits to encode. Finally, we can
merge 11 bits and the results need 3 bits to encode.
Next, we encode another 3 bits. At last, it may have 2 bits or 1 bit decoder at the end. If the number of compression results is 3 or 4, the results will be encoded to 2 bits. If the compression results equal to 1 or 2, the results will be encoded to 1 bit. We also restrict the maximum number of one decoder output to 256. If the output number of a decoder approaches 256, we will finish processing this segment and the input number of this segment’s encoder may be fewer than 3. Finally, we can use a 4-bit or 5-bit decoder that provides 16 or 32 different codes.
To be more specific, a realistic case is provided here. This example shows 14 test patterns in the CSC. The compression pattern number will equal or be smaller than the original pattern number after the merging step. Figure 3.3 (a) shows the compression results and all Xs after the compression are replaced by 0. Each compressed pattern is given a number as index. Through the compression procedure, the first segment of compressed test data in Figure 3.3 (a) applies 3 bits (6 codes) to encode 11 bits data.
3.2.2 Power optimization stage
In order to minimize the shift-in power with n-bit based encoding, the greedy search method are applied in each segment to find the lower power coding. Assuming the initial state of the scan chain is 0, it will obtain the optimal solution (n = 3) and a heuristically good solution (n > 3) after pattern selection and pattern compression stages. This stage maps new encoded data to the compressed pattern. The first column of Figure 3.3 (a) needs 6 different compressed codes to map. In Figure 3.3 (a) (b) (c), the test result 00001000000 maps to 0, and 0 maps to the new test pattern 110 in the first row first column of Figure 3.3 (b) (c). The CSC shift-in data will be 110 and the decoder will produce 00001000000 to the NSC.
In this stage, we try to get the mapping result with the smallest transition counts.
The permutation of 3 bits, with 8 new encoded data, is 40320(8!). The optimization
Figure 3.3: FIVO scheme case in pattern compression and power optimization stage.
We use a 3-bit encoding example to illustrate our approach. This table shows the results after the merging process and all Xs are replaced by 0 after the merging process. (a) is the compressed test pattern of each segment. (b) shows the index number of each segment. (c) shows the new test data results and the mapping codes come from (b). (d) shows one test pattern transformation from original test data to new test data.
method tries to find all the permutations from the first segment to the last segment, and decides the minimal switch power encoding. The encoding results become new encoded data. Since the permutations of 4 and 5 bits of encoded data are very large, the computation time of the optimization stage will be very long. Only to optimizing the partial encoded data is recommended.
The first row in Figure 3.3 (b) shows that 04 is the index number of the test pattern. This pattern maps to test result 000010000000100000001 and new test pattern 110001. The test result can be obtained from Figure 3.3 (a) by index.
In this example, the index code 0 in the first column of Figure 3.3 (a) maps to 0000100000 and maps to 110 in Figure 3.3 (c). The index code 4 in the second column of Figure 3.3 (a) maps to 0100000001 and maps to 001 in Figure 3.3 (c). We can also perceive that all of the index codes 0 in the first column of Figure 3.3 (b)
Figure 3.4: Circuit design of the FIVO scan chain architecture.
map to 110.
With the mapping method, we can get the CSC shift-in codes. Each row in Figure 3.3 (c) will be shifted into the CSC. Figure 3.3 (c) is the power optimization result codes. We can observe that the compressed patterns are encoded to fewer bits of data. Figure 3.3 (d) shows a new test pattern (on the bottom), which is generated from original test pattern, to the compressed data mapping index, then to the compressed data in the CSC.