There are several environmental factors which would have effects on the nanostructure, for example, reaction temperature and reaction time. These effects should be optimized.
Accordingly, some experiments to affirm the optimum reaction conditions for the nanodevices to fabricate were executed first.
As a matter of fact, to construct the nanostructure is like to build the building. The base of the nanostructure should have higher density. Therefore the first layer, Au NPs, plays an important role in self-assembly process. If the density and quality of the first Au NPs thin film is high, the second and subsequent layers would also get high.
Hence, two experiments were executed. One is to observe the reaction time effect on the nanostructure construction. The other is to investigate the reaction temperature effect. And then SEM photograph of the nanodevices helps us to determine which conditions are suitable.
In previous work, an experiment was to investigate the temperature effect on the nanostructure construction. Hence, two pieces of p-type silicon wafer was prepared. One was to be coated with Au NPs and PDDA-capped CdSe/ZnS QDs as a 2-layer basic nanostructure in the room temperature environment. The other was to be coated in the same way, but in the 4°C reaction environment. Figure 2.16 shows the experiment outcomes. As the Figure 2.14(a) shown, the nanostructure which was constructed on condition of the room temperature got lower density.
The other experiment is to observe if the different reaction time influence the nanostructure. Therefore, two pieces of quartz glasses were prepared. One was to be coated with Au NPs and PDDA-capped CdSe/ZnS QDs as a 4-layer basic nanostructure for 4 hours per layer. The other was to be coated in the same way, but 12 hours per layer reaction period.
The result is shown as Figure 2.15. Figure 2.15(a) is the nanostructure that was fabricated with 4 hours reaction time per layer. Figure 2.15(b) is the nanostructure that was constructed with 12 hours reaction time per layer. As a result, the 12-hour-reaction-time one got high particle density. It benefits the nanodevice construction.
In conclusion, lower temperature and longer reaction period would benefit nanostructure.
Therefore, these two factors would be adopted in the nanodevice fabrication technology.
Table 2.1 The dimensions of all horizontal electrodes fabricated in NDL are list in this table.
(unit:μm)
Pad Description
Pad_7 Pad_8 Pad_10 Pad_11 5x30 0.5x30 1x30 2.5x30
Figure 2.1 The flow diagram for preparing the citrate-capped Au NPs solution
Figure 2.2 (a) The close photographs of 100 μL of approximately 15 nm diameter Au NPs solution + 100 μL DI water (left) and 100 μL of approximately 5 nm diameter AET-CdSe/ZnS NPs solution + 100 μL DI water (right). The Au NPs solution was in deep red while the AET-modified CdSe/ZnS NPs solution was in yellow. (b) The close photographs of the mixture of 100 μL Au NPs solution and 100 μL AET-modified CdSe/ZnS NPs solution just after mixing (right), the mixture after standing 6 hrs (middle) in room temperature, and the mixture after standing 5 days in room temperature (left). As we can see, the color of mixture just after mixing was like that of Au NPs solution. However, after 6 hrs, it became dark purplish red. After 5 days, there was obvious precipitate at the bottom and the supernatant became pale yellow.
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Figure 2.3 (a) The TEM image of Citrate-capped approximately 15 nm diameter Au NPs and the TEM image of AET-capped approximately 5 nm diameter CdSe/ZnS QDs. (b) The UV-visible spectrum of Au NPs solution. (c) The UV-visible and PL intensity spectrum of AET-CdSe/ZnS QDs solution.
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Figure 2.4 (a) The band gap and surface structure diagram of CdSe/ZnS QD. (b) The PL intensity spectrum of different kind of surface capping method of CdSe QD
Figure 2.5 The flow diagram for preparing the AET-capped CdSe/ZnS QDs solution.
Figure 2.6 Density of states in metal (A) and semiconductor (B). In each case, the density of states is discrete at the band edges. The Fermi level is in the center of a band in a metal, and so kT will exceed the level spacing even at low temperature and small size. In semiconductor, the Fermi level lies between two bands, so that there is large level spacing even at large size.
The HOMO-LUMO gap increases as the size of semiconductor nanocrystal decreases (bellow 10 nm). [11].
Figure 2.7 The cross-section view of the electrode structure and the PR is photoresistor for lift-off process.
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Figure 2.8 (a) The cross section figure of the electrodes structure corresponds to SEM image of the nanodevice-modified silicon chip. (b) The current flow trend of the nanodevice structure, and the electrodes dominated the source of the generated current. In the worse case, the whole chip area is considered, not the area of the electrodes. (The twill line means the thin film structure composed of NPs and QDs.).
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(c) (d)
(e) (f)
(g) (h)
(h) (j)
(k) (l)
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Figure 2.9 Fabrication flow of the proposed nanodevice (top-view and cross-section view).
From (a) to (j) is the electrode fabrication process, and (k) to (n) is the nanostructure self-assembly (SAM) process.
Figure 2.10 The corresponding mask layout view. There are six masks in this work, and all details are list in Table 2.1.
Figure 2.11 The cross-section view of modified nanostructure with Au NPs and three different-sized PDDA-capped CdSe/ZnS quantum dots. The bottom layer is composed of larger-sized QDs (smaller band gap, absorb smaller wavelength), and the top layer is composed of smaller-sized QDs (larger band gap, absorb longer wavelength). This is because light with longer wavelengths (ref region) is transmitted through initial layer.
oxide
oxide
Al Al
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Figure 2.14 The fabrication process of the nanostructure by coulombic force system after lift-off process. (a) The modification of TMSPED on the silicon oxide surface and the protonation of amino (-NH3+) groups, (b) The assembly of ~ 15 nm diameter Au NPs on silicon oxide substrate by ionic interaction, (d) The assembly of ~ 5 nm diameter AET-CdSe/ZnS NPs on the silicon oxide substrate by ionic interaction, and (e) The formation of the photo-sensing nanodevice structures after repeated assembly process. (Not to scale)
Figure 2.15 SEM photograph of nanodevice with lift-off process, the black part is the place where Au NPs and CdSe QDs deposit.
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Figure 2.16 The temperature effect on the nanostructure (SEM photograph). (a) the nanostructure constructed at room temperature (b) the nanostructure constructed at 4°C environment.[11]
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Figure 2.17 The reaction time effect on the nanostructure (SEM photograph). (a) the nanostructure with 4-hour-reaction time per layer (b) the nanostructure with 12-hour-reactime per layer