3.4 Nanoparticle Solar Cell Efficiency Estimation and Nanodevice Model Construction
Figure 3.14(a) depicts the traditional p-n junction solar cell, and its I-V curve is shown in Figure 3.14(b). According to this I-V characteristic, an effective circuit model of p-n junction solar cell model is illustrated in Figure 3.14(c), where Rs is a small seris resistor and Rp is a very large parallel resistor. In this work, a resistive load is connected to the solar cell.
Therefore, an operation point is obtained as shown in Figure 3.15. And the parameter, fill factor is defined.
where Voc is the open circuit voltage of the solar cell. Isc is the short current of the solar cell.
Vm and Im is the voltage and the current when the product of the voltage and current (power) is maximum. Then, the efficiency can be defined as
factor
where Pin is the power of the incident light source. Now, we could define the formula of I-V curve and estimate its maximum power.
sc
Based on the conventional p-n junction equivalent circuit model, the proposed Au NPs/
PDDA-capped CdSe/ZnS QDs nanodevice model could be constructed. An Au NP and a PDDA-capped CdSe/ZnS QD could be considered as a micro p-n junction solar cell or nano-schottky diode. As shown in Figure 3.16(a), there is a unit cell of the nanodevice between Au NPs and PDDA-capped CdSe/ZnS QD. Figure 3.17 depicts the 1-demensionan nanodevice model. It is a symmetrical structure. And Rs1 and Rs2 are small series resistors, Rp1
and Rp2 are very large parallel resistors. I1 and I2 are the photocurrent after illumination.
For HSPICE simulation, the metal-insulator-semiconductor diode model is employed.
And then 2-dimension and 3-dimension nanodevice models could also be constructed in similar way. Figure 3.18 and 3.19 illustrate the 2-dimension and 3-dimension nanodevice equivalent circuit model respectively.
It is worth mentioning that 3-dimension nanodevice model is more complicated than 1-D and 2-D model. Figure 3.19 depicts the ideal 3-dimension nanostructure. The unit cells connect two of the 2-D nanodevice model to form a 3-D nanodevice model. The simulation parameters illustrate in Figure 3.20. First, for HSPICE simulation, Metal-Insulator-Semiconductor diode model was employed. X-dimension unit cell : Rs=15kΩ, Rp=7MΩ, I=2.1nA; Y-dimension unit cell : Rs=0.918MΩ, Rp=289MΩ, I=2.1nA,
Z-dimension unit cell: Rs=3060Ω, Rp=25M, I=2.1nA. A 30 μm / 0.1 μm (width / length) 6-layered PDDA-capped CdSe/ZnS nanodevice is utilized as a unit cell. And then the length effect is discussed and simulated. The photocurrent decreases as the length increase (fixed width = 30 μm, and fixed number of layer = 6) as shown in Figure 3.21(a). The open-circuit voltage also decreases as the length increase as shown in Figure 3.21(b). Hence, PVD and power volume density both decrease as the length increase as shown in Figure 3.21(c) and (d) respectively. And the efficiency is shown in Figure 3.21(e).
In summary, decreasing the length will benefit the performance of the proposed nanodevice. On the basis of the ideal inference, the linear approximation is applied to optimize the dimension of the proposed nanodevice structure. However, the thickness of the nanostructure is not uniform. If the nanoparticles close together, the thickness might less then 60 nm; otherwise, the thickness might be more then 60 nm. Hence, we assume the thickness of the nanostructure is from 50 to 80 nm. And Figure 3.22 shows the efficiency simulation results as the length of the proposed nanodevice shrinks to 100, 50, 40, 30 and 20 nm. As a result, the 36.87 % efficiency solar cell can be realized when the nanodevice is 30 μm in width and 40 nm in length. Moreover, when the length is scaled down to 30 and 20 nm, the solar cell efficiency is up to 51.17 % and 80.18% respectively. Table 3.3 lists the simulation results with linear estimation approximately.
Table 3.1 The experimental and measurement results of the proposed 6-layered PDDA-capped CdSe/ZnS nanodevices. (PVD: photocurrent volume density, Power VD: power volume density)
Table 3.2 Performance comparison table
Previous work [19]* Previous work [11]** This work Light Source 2.5 mW/cm2
** Lift-off area was not exactly the same as the illuminated area.
*** Calibrated efficiency.
W/L (mm/mm) 30/5 30/2.5 30/1 30/0.5
Vbias -100mV~100mV
Isc (pA) 178.10 382.10 406.66 664.62
Voc (mA) 0.34 0.52 0.77 2.31
Isc*Voc (pW) 0.061 0.199 0.313 1.535
Req (dark) 2.79MW 2.43MW 3.30MW 7.81MW
Req (light) 1.93MW 1.36MW 1.88MW 3.45MW
PVD (A/ nm3) 1.979×10-22 8.491×10-20 2.259×10-19 7.385×10-19 Power VD (W/nm3) 1.702×10-24 1.111×10-23 4.349×10-23 4.256×10-22
Efficiency (%) 0.007% 0.043% 0.163% 1.600%
Table 3.3 The simulation results with linear estimation of the proposed 6-layered PDDA-capped CdSe/ZnS nanodevices.
Length (nm) Estimated Efficiency (%)
Min. Max.
100 10.90 12.19
50 25.56 28.40
40 33.45 36.87
30 46.94 51.17
20 74.60 80.18
(a) (b)
Figure 3.1 (a) Photographic of the electrodes of the proposed nanodevices. Pad 7: 30 μm / 5 μm, Pad 8: 30 μm / 0.5 μm, Pad 10: 30 μm / 1 μm, Pad 11: 30 μm / 2.5 μm (width / length). (b) Enlarged view. The nanoparticles or quantum dots deposit on the gap of two electrodes.
(a) (b)
(c) (d)
Figure 3.2 The environment setup for I-V characteristics measurement, (a) probe station (b) HP4156 (c) the spectrum of the daylight lamp (d) Solar Spectrum.
300 400 500 600 700 800 900 1000 1100
0
Figure 3.3 The environment setup for UV-visible absorbance spectrum measurement.
Figure 3.4 The environment setup for PL intensity spectrum measurement.
(a) (b)
(c) (d)
(e)
Figure 3.5 SEM images of the surface of SiO2 quartz fragments after repeated self-assembly process. (a) SiO2/quartz only, (b) Au + SiO2/quartz, (c) PDDA-capped CdSe + Au + SiO2/quartz, (d) Au + PDDA-capped CdSe + Au + SiO2/quartz, (e) PDDA-capped CdSe + Au + PDDA-capped CdSe + Au + SiO2/quartz
Figure 3.6 Lateral SEM images of the surface of wafer fragments after repeated self-assembly process. The surface of the nanostructure is not smooth, since PDDA is capped the surface of CdSe/ZnS QD.
400 500 600 700 800
Absorbance (AU)
Wavelength (nm)
red yellow green
Figure 3.7 UV-VIS absorption spectra of different-sized PDDA-capped CdSE/ZnS QDs. From the absorption spectrum, we can see that the peak of absorbance was about 500nm ~ 600nm.
Figure 3.8 PL intensity spectra of different-sized PDDA-capped CdSE/ZnS QDs. Using 365 nm wavelength excitation light, we can observe three peaks.
Figure 3.9 Photography of three different-sized PDDA-capped CdSe/ZnS QDs.
(a) (b)
(c) (d)
Figure 3.10 The I-V characteristics of the proposed 6-layered PDDA-capped CdSe/ZnS QDs and Au NPs nanodevices. (a) 30 μm / 5 μm, (b) 30 μm / 2.5 μm, (c) 30 μm / 1 μm, (d) 30 μm / 0.5 μm. (width / length)
Figure 3.11 The I-V characteristics of the proposed 6-layered PDDA-capped CdSe/ZnS QDs and Au NPs nanodevices with different lengths.
(a)
(b)
(c)
(d)
(e)
Figure 3.12 The relation between the main specifications and the length of the proposed 6-layered PDDA-capped CdSe/ZnS QDs / Au NPs nanodevices. (a) photocurrent, (b) open-circuit voltage, (c) PVD, (d) power volume density, and (e) power conversion efficiency.
(a)
(b)
Figure 3.13 After 24 days, the performance of the nanodevice decayed. (a) photocurrent, and (b) power conversion efficiency. And after 26 days, the decay tended to saturate.
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
(a)
(b)
(c)
Figure 3.14 (a) The p-n junction solar cell structure, (b) the I-V curve of the p-n junction solar cell, (c) the equivalent circuit model of the p-n junction solar cell.
Figure 3.15 I-V characteristic of solar cell (including load line)
Figure 3.16 (a) A unit cell of the nanodevice model, (b) Symmetrical structure
Figure 3.17 1-D nanodevice model, where Rs1 and Rs2 are small series resistors, Rp1 and Rp2 are very large parallel resistors. I1 and I2 are the photocurrent after illumination.
Au NP
CdSe QD
(a)
(b)
Figure 3.18 2-D nanodevice model. (a) 2-D nanostructure, (b) 2-D nanodevice equivalent circuit model.
Figure 3.19 3-D nanodevice model. And the dash line parts are substituted for the unit cells.
Figure 3.20 The 3-D nanodevice model. The line parts are substituted for the unit cells. For HSPICE simulation, Metal-Insulator-Semiconductor diode model was employed.
X-dimension unit cell : Rs=15kΩ, Rp=7MΩ, I=2.1nA, Y-dimension unit cell : Rs=0.918MΩ, Rp=289MΩ, I=2.1nA, Z-dimension unit cell : Rs=3060Ω, Rp=25M, I=2.1nA.
(a)
(b)
(c)
(d)
(e)
Figure 3.21 (Length effect) Comparison of the 3-D nanodevice model simulation results and measurement results of the proposed 6-layered PDDA-capped CdSe/ZnS QDs / Au NPs nanodevices. (a) photocurrent, (b) open-circuit voltage, (c) PVD, (d) power volume density, and (e) solar cell efficiency.
Figure 3.22 On the basis of the ideal inference, the linear approximation is applied to optimize the dimension of the proposed nanodevice structure. The length shrinks to 100, 50, 40, 30, and 20 nm. However, the thickness of the nanostructure is not uniform. If the nanoparticles close together, the thickness might less then 60 nm; otherwise, the thickness might be more then 60 nm. Hence, we assume the thickness of the nanostructure is from 50 to 80 nm.
C HAPTER 4
A PPLICATION OF L INEAR R EGULATOR ON
N ANOPARTICLE S OLAR C ELL
Solar cells have been promising candidate for next generation alternative energy source.
Therefore using solar cell to provide the power of portable devices has been considered as one of the potential architecture in the future. Regulators are an essential part of electrically powered system, which includes the growing family of applications of portable battery operated products. The widespread use of battery-powered devices in today’s world has increased the demand for low-voltage, low drop-out linear regulator (LDO) [20].
The basic function of the regulators is to reduce the large voltage variation of battery cell and provide a reliable, constant output voltage to drive small sub-circuits. Absence of these power supplies can prove to be catastrophic in most high frequency and high performance circuit designs. As a result, regulators and other power supply circuits are always in high demand. Generally, linear regulators and switching regulators are widely used in the commercial electronic applications. Linear regulators are purely analog circuits. The operation of the circuits is based on feeding back an amplified error signal to control the output current flow of the power transistor driving the load. So the output can be adjusted to the desired voltage immediately. According to the configuration of the linear regulators, the magnitude of the respective output voltage is less than the input supply voltage. On other hand, switching regulators are essentially mixed-mode circuits which feed back an analog error signal and digitally gate it to provide bursts of current to the output. Furthermore, switching regulators can provide a wide range of output voltage including values that lower or
greater than the input supply voltage depending on the circuit configuration, buck or boost.
In this work, the linear regulator is adopted. There are some reasons why this configuration is chosen. First of all, the power consumption can be very low while in light load condition. This reason makes it appropriate for use in solar cell application. Second, this configuration dose not suffer form the switching noise generated by digital signals or clock.
Finally the circuits are implemented without using any inductors, so the footprint area is also very small. And the linear regulator is inherently less complex and costly than the switching regulator.
In this chapter, a low voltage, low quiescent current, low drop-out regulator system is designed to target the low power operation and integrated with the proposed nanoparticle solar cell. The relevant analysis is introduced to design the system. The proposed regulator system was successfully fabricated in TSMC 1P6M 0.18-μm CMOS process.