effect is discussed and simulated. The photocurrent decreases as the length increase (fixed width = 30 μm, and fixed number of layer = 6) as shown in Figure 3.21(a). The open-circuit voltage also decreases as the length increase as shown in Figure 3.21(b). Hence, PVD and power volume density both decrease as the length increase as shown in Figure 3.21(c) and (d) respectively. And the efficiency is shown in Figure 3.21(e).
In summary, decreasing the length will benefit the performance of the proposed nanodevice. On the basis of the ideal inference, the linear approximation is applied to optimize the dimension of the proposed nanodevice structure. However, the thickness of the nanostructure is not uniform. If the nanoparticles close together, the thickness might less then 60 nm; otherwise, the thickness might be more then 60 nm. Hence, we assume the thickness of the nanostructure is from 50 to 80 nm. And Figure 3.22 shows the efficiency simulation results as the length of the proposed nanodevice shrinks to 100, 50, 40, 30 and 20 nm. As a result, the 36.87 % efficiency solar cell can be realized when the nanodevice is 30 μm in width and 40 nm in length. Moreover, when the length is scaled down to 30 and 20 nm, the solar cell efficiency is up to 51.17 % and 80.18% respectively. Table 3.3 lists the simulation results with linear estimation approximately.
Table 3.1 The experimental and measurement results of the proposed 6-layered PDDA-capped CdSe/ZnS nanodevices. (PVD: photocurrent volume density, Power VD: power volume density)
Table 3.2 Performance comparison table
Previous work [19]* Previous work [11]** This work Light Source 2.5 mW/cm2
** Lift-off area was not exactly the same as the illuminated area.
*** Calibrated efficiency.
W/L (mm/mm) 30/5 30/2.5 30/1 30/0.5
Vbias -100mV~100mV
Isc (pA) 178.10 382.10 406.66 664.62
Voc (mA) 0.34 0.52 0.77 2.31
Isc*Voc (pW) 0.061 0.199 0.313 1.535
Req (dark) 2.79MW 2.43MW 3.30MW 7.81MW
Req (light) 1.93MW 1.36MW 1.88MW 3.45MW
PVD (A/ nm3) 1.979×10-22 8.491×10-20 2.259×10-19 7.385×10-19 Power VD (W/nm3) 1.702×10-24 1.111×10-23 4.349×10-23 4.256×10-22
Efficiency (%) 0.007% 0.043% 0.163% 1.600%
Table 3.3 The simulation results with linear estimation of the proposed 6-layered PDDA-capped CdSe/ZnS nanodevices.
Length (nm) Estimated Efficiency (%)
Min. Max.
100 10.90 12.19
50 25.56 28.40
40 33.45 36.87
30 46.94 51.17
20 74.60 80.18
(a) (b)
Figure 3.1 (a) Photographic of the electrodes of the proposed nanodevices. Pad 7: 30 μm / 5 μm, Pad 8: 30 μm / 0.5 μm, Pad 10: 30 μm / 1 μm, Pad 11: 30 μm / 2.5 μm (width / length). (b) Enlarged view. The nanoparticles or quantum dots deposit on the gap of two electrodes.
(a) (b)
(c) (d)
Figure 3.2 The environment setup for I-V characteristics measurement, (a) probe station (b) HP4156 (c) the spectrum of the daylight lamp (d) Solar Spectrum.
300 400 500 600 700 800 900 1000 1100
0
Figure 3.3 The environment setup for UV-visible absorbance spectrum measurement.
Figure 3.4 The environment setup for PL intensity spectrum measurement.
(a) (b)
(c) (d)
(e)
Figure 3.5 SEM images of the surface of SiO2 quartz fragments after repeated self-assembly process. (a) SiO2/quartz only, (b) Au + SiO2/quartz, (c) PDDA-capped CdSe + Au + SiO2/quartz, (d) Au + PDDA-capped CdSe + Au + SiO2/quartz, (e) PDDA-capped CdSe + Au + PDDA-capped CdSe + Au + SiO2/quartz
Figure 3.6 Lateral SEM images of the surface of wafer fragments after repeated self-assembly process. The surface of the nanostructure is not smooth, since PDDA is capped the surface of CdSe/ZnS QD.
400 500 600 700 800
Absorbance (AU)
Wavelength (nm)
red yellow green
Figure 3.7 UV-VIS absorption spectra of different-sized PDDA-capped CdSE/ZnS QDs. From the absorption spectrum, we can see that the peak of absorbance was about 500nm ~ 600nm.
Figure 3.8 PL intensity spectra of different-sized PDDA-capped CdSE/ZnS QDs. Using 365 nm wavelength excitation light, we can observe three peaks.
Figure 3.9 Photography of three different-sized PDDA-capped CdSe/ZnS QDs.
(a) (b)
(c) (d)
Figure 3.10 The I-V characteristics of the proposed 6-layered PDDA-capped CdSe/ZnS QDs and Au NPs nanodevices. (a) 30 μm / 5 μm, (b) 30 μm / 2.5 μm, (c) 30 μm / 1 μm, (d) 30 μm / 0.5 μm. (width / length)
Figure 3.11 The I-V characteristics of the proposed 6-layered PDDA-capped CdSe/ZnS QDs and Au NPs nanodevices with different lengths.
(a)
(b)
(c)
(d)
(e)
Figure 3.12 The relation between the main specifications and the length of the proposed 6-layered PDDA-capped CdSe/ZnS QDs / Au NPs nanodevices. (a) photocurrent, (b) open-circuit voltage, (c) PVD, (d) power volume density, and (e) power conversion efficiency.
(a)
(b)
Figure 3.13 After 24 days, the performance of the nanodevice decayed. (a) photocurrent, and (b) power conversion efficiency. And after 26 days, the decay tended to saturate.
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
(a)
(b)
(c)
Figure 3.14 (a) The p-n junction solar cell structure, (b) the I-V curve of the p-n junction solar cell, (c) the equivalent circuit model of the p-n junction solar cell.
Figure 3.15 I-V characteristic of solar cell (including load line)
Figure 3.16 (a) A unit cell of the nanodevice model, (b) Symmetrical structure
Figure 3.17 1-D nanodevice model, where Rs1 and Rs2 are small series resistors, Rp1 and Rp2 are very large parallel resistors. I1 and I2 are the photocurrent after illumination.
Au NP
CdSe QD
(a)
(b)
Figure 3.18 2-D nanodevice model. (a) 2-D nanostructure, (b) 2-D nanodevice equivalent circuit model.
Figure 3.19 3-D nanodevice model. And the dash line parts are substituted for the unit cells.
Figure 3.20 The 3-D nanodevice model. The line parts are substituted for the unit cells. For HSPICE simulation, Metal-Insulator-Semiconductor diode model was employed.
X-dimension unit cell : Rs=15kΩ, Rp=7MΩ, I=2.1nA, Y-dimension unit cell : Rs=0.918MΩ, Rp=289MΩ, I=2.1nA, Z-dimension unit cell : Rs=3060Ω, Rp=25M, I=2.1nA.
(a)
(b)
(c)
(d)
(e)
Figure 3.21 (Length effect) Comparison of the 3-D nanodevice model simulation results and measurement results of the proposed 6-layered PDDA-capped CdSe/ZnS QDs / Au NPs nanodevices. (a) photocurrent, (b) open-circuit voltage, (c) PVD, (d) power volume density, and (e) solar cell efficiency.
Figure 3.22 On the basis of the ideal inference, the linear approximation is applied to optimize the dimension of the proposed nanodevice structure. The length shrinks to 100, 50, 40, 30, and 20 nm. However, the thickness of the nanostructure is not uniform. If the nanoparticles close together, the thickness might less then 60 nm; otherwise, the thickness might be more then 60 nm. Hence, we assume the thickness of the nanostructure is from 50 to 80 nm.
C HAPTER 4
A PPLICATION OF L INEAR R EGULATOR ON
N ANOPARTICLE S OLAR C ELL
Solar cells have been promising candidate for next generation alternative energy source.
Therefore using solar cell to provide the power of portable devices has been considered as one of the potential architecture in the future. Regulators are an essential part of electrically powered system, which includes the growing family of applications of portable battery operated products. The widespread use of battery-powered devices in today’s world has increased the demand for low-voltage, low drop-out linear regulator (LDO) [20].
The basic function of the regulators is to reduce the large voltage variation of battery cell and provide a reliable, constant output voltage to drive small sub-circuits. Absence of these power supplies can prove to be catastrophic in most high frequency and high performance circuit designs. As a result, regulators and other power supply circuits are always in high demand. Generally, linear regulators and switching regulators are widely used in the commercial electronic applications. Linear regulators are purely analog circuits. The operation of the circuits is based on feeding back an amplified error signal to control the output current flow of the power transistor driving the load. So the output can be adjusted to the desired voltage immediately. According to the configuration of the linear regulators, the magnitude of the respective output voltage is less than the input supply voltage. On other hand, switching regulators are essentially mixed-mode circuits which feed back an analog error signal and digitally gate it to provide bursts of current to the output. Furthermore, switching regulators can provide a wide range of output voltage including values that lower or
greater than the input supply voltage depending on the circuit configuration, buck or boost.
In this work, the linear regulator is adopted. There are some reasons why this configuration is chosen. First of all, the power consumption can be very low while in light load condition. This reason makes it appropriate for use in solar cell application. Second, this configuration dose not suffer form the switching noise generated by digital signals or clock.
Finally the circuits are implemented without using any inductors, so the footprint area is also very small. And the linear regulator is inherently less complex and costly than the switching regulator.
In this chapter, a low voltage, low quiescent current, low drop-out regulator system is designed to target the low power operation and integrated with the proposed nanoparticle solar cell. The relevant analysis is introduced to design the system. The proposed regulator system was successfully fabricated in TSMC 1P6M 0.18-μm CMOS process.
4.1. System Design Considerations
Proper design of a low drop-out (LDO) regulator involves intricate knowledge of the system and its load. The task of maximizing load regulation, maintaining stability, and minimizing transient output voltage variations prove to be challenging and often conflicting.
The system also has to target the low power consumption and integrate with the proposed solar cell device.
4.1.1. Architecture
As the Figure 4.1 shown, the system architecture is utilized in this work. The system is composed of an error amplifier, a pass element, feedback resistor network, bandgap voltage reference, off-chip compensating capacitor and associated electrical series resistor (ESR), and bypass capacitor.
4.1.2. AC Analysis
Because the low drop-out regulator is a feedback system, the stability issue should be concerned. Figure 4.2 illustrates the intrinsic factors that determine the stability of the system.
The ESR of the by pass capacitors can typically neglected due to high frequency capacitor; in other words, the ESR value is low. The pass device is modeled as a circuit element exhibiting a transconductance of gmp and an output impendance of Ro-pass. The value of R1 is designed to define the quiescent current flowing through resistors R1 and R2, which is typically large to minimize the quiescent current consumption. And the value of R2 is dependent on the desired value of the output voltage, i.e. the voltage of the output and Vref determines the resistor ratio of R1 and R2.
z Frequency Response
For the purpose of analysis, the feedback loop can be broken at node “A” in Figure 4.2.
The system must be unity gain stable, considering Vref and Vfb to be the input and the output voltages respectively. So the open-loop gain can be described as
[ ]
1 2where gma and gmp refer to the transconductance of the error amplifier and the pass element respectively, Roa is the output resistance of the amplifier, Cpar is refer to the parasitic capacitor introduced by the pass element, and Z is the impedance seen at node Vout,
[ ]
where CO and Resr are the capacitance and ESR of the output capacitor, Cb represents the bypass capacitors and Rx is the resistance seen from Vout back into the regulator defined as
(
1 2)
pass o
X R || R R
R = − + (4.3)
where Ro-pass is the output resistance of the pass element. The output resistance of the load (RL) is commonly neglected because its value is considerably large than Rx. If Co is assumed to be reasonably larger than Cb (typical condition), then Z approximates to
[ ]
It can be observed from equation (4.1) to (4.4) that the overall transfer function of the system consists of three poles and one zero, a potentially unstable system. Since R1+R2 is greater in magnitude (especially at high current), Rx simplifies to Ro-pass. The poles and zero can thus be approximated to be the following:
O
and Figure 4.3 illustrates the typical frequency response of the system under two different loading current assuming that the output capacitor (CO) is larger than the bypass capacitor (Cb).
z Worst-case Stability
The following step is to analysis the stability issue introduced from the low frequency poles. The worst case arises when the phase margin is at its lowest point, which occurs when the unity gain frequency is pushed out to higher frequency where the parasitic poles reside.
This happens when the load-current is at its peak values. This is because the dominant pole (P1) usually increases at a faster rate (Ro-pass decreases linearly with increasing current, I/λIo ,where λ is the channel length modulation parameter of MOS devices) than the gain of
the system decreases (gmp Ro-pass decreases with the square roots of the increasing current for an MOS device) as showen in Figure 4.3. The type and value of the output capacitor determine the location of P1, P2, and Z1. Therefore, the permissible range of values of ESR for a stable circuit is a function load-current and circuit characteristics.
z Parasitic Pole Requirements
The parasitic pole of the system can be identified as P3 and the internal poles of the error amplifier. These poles are required to be at high frequency, at least greater than the unit gain frequency. The phase margin for the case where only one parasitic pole was at the vicinity of the unit gain frequency is at approximately 45。. Ensuring that P3 is at high frequencies is an especially difficult task to undertake in a low current environment. The pole is defined by the large parasitic capacitance (Cpar) resulting from a large pass element and the output resistance of the amplifier (Roa). The output impedance of an amplifier is always a function of the circuit topology and he bias current of its output stage. As a result, low quiescent current and frequency design issue have conflicting requirements that necessitate compromises [19].
z Load Regulation
Load regulation performance (output resistance of the regulator, Ro) is a function of the open-loop gain (Aol) of the system and can be expressed as
β
where ΔVLDR is the output voltage variation arising from a load current variation of ΔIO, Ro-pass is the output resistance of the pass device, and β is the feedback factor. Consequently, the regulator yields better load regulation performance as the open-loop gain increase.
However, the gain is limited by the close-loop bandwidth of the system, equivalent to the open-loop unit gain frequency (UGF). The minimum unit gain frequency is limited by the
response time required by the system during transient load current variations. Furthermore, the UGF is also bounded at the high frequency range by the parasitic poles of the system, i.e., the internal poles of the amplifier and pole P3. In particular, the worst case condition occurs when Z1 is at low frequencies and P2 is at high frequencies, which corresponds to the maximum value of ESR and the lowest bypass capacitance (Cb). Moreover, the pass element associated input capacitance is significantly large. This places a ceiling on the value of the amplifier output resistance (Roa). The pass element usually needs to be a large size device to yield low drop-out voltages and high output current characteristics with limited voltage drive in a low voltage and low power environment. Overall, load regulation is limited by the constrained open-loop gain of the system.
4.1.3 Transient Analysis
An important specification is the maximum allowable output voltage change for a full range transient load current step. Figure 4.4 shows transient response of the LDO under a sudden load current step change.
The worst case time required for the loop to respond is specified by the maximum permissible output voltage variation (ΔVtr), which is a function of the output capacitor (Co), the electrical series resistance (ESR) of the output capacitor, the bypass capacitors (Cb), and the maximum load current (ILoad-max),
esr
where ΔVesr is the voltage variation resulting from the presence of the ESR of the output capacitor. The effects of ESR are reduced by the bypass capacitors (Cb), which are typically high frequency thereby exhibiting low ESR values. The duration Δt1 is a function of bandwidth, internal slew-rate associated with the parasitic capacitance Cpar of the pass
element. The resulting time can be approximated to be
where BWcl is the closed-loop bandwidth of the system, tsr is the slew-rate associated with Cpar, ΔV is the voltage variation at Cpar, and Islew is the slew-rate limited current. If the Islew is large enough, the bandwidth of the close-loop will dominate Δt1.
Once the slew-rate condition is terminated, the output voltage recovers and settles to its final value, ΔV2 below the ideal value,
max
where Ro-reg is the closed-loop output resistance of the regulator. This is essentially the effect of load regulation performance. And the settling time (Δt2) is dependent on the time required for the pass device to fully charge the load capacitors and the phase margin of the open-loop frequency.
In fact, the slew rate condition should be concerned. It typically occurs when load current steps from zero to full scale. The condition is dependent on the configuration of the output stage of the error amplifier and the output pass device. The output voltage variation (ΔV3), whose magnitude is defined by the voltage charged on the capacitors and the voltage generated across the ESR of the output capacitor. This results because the momentary current supplied by the power device flows to Co and Cb. Consequently, the capacitors are charged and a temporary voltage drop is created across Resr. The transient voltage variation can be approximately expressed as
Finally when the output transistor is shut off (afterΔt3) the variation settles down to ΔV4, the voltage charged on the capacitors (ΔV4≒ΔV3-ΔVesr). At this point, the output voltage takes time Δt4 to discharge to its final ideal value,
[ ]
As a result, the additional off-chip bypass capacitors (low ESR capacitors) reduce the peak value of ΔVtr-max and ΔV3. This results because the current supplied by the output capacitor (Co) during transient condition is decreased as Cb is increased thereby exhibiting a lower voltage drop across Resr. The remaining current is supplied by the bypass capacitors, which have negligible ESR voltage drops [20].
4.2 Circuit Blocks
As the Figure 4.1 shown, LDO system is composed of an error amplifier, a pass element, feedback resistor network, bandgap voltage reference, off-chip compensating capacitor, associated electrical series resistor (ESR), and bypass capacitor. Based on the theoretical analysis, the circuit structure and schematic of each part in the system is introduced in this section. And then, the system can be separated into two parts, LDO core and bandgap voltage reference respectively.
First, the LDO core schematic is illustrated in Figure 4.5. The error amplifier plays an important role in LDO design. The specifications of the error amplifier that are relevant to the regulator as inferred from the previous discussions are: output resistance, gain, bandwidth, output slew-rate current, output voltage swing and quiescent current. The output impedance must be low enough to place the parasitic pole P3 at a frequency greater than the unity-gain frequency. Due to the low voltage application, the number of stacked transistors should be minimized. Therefore the telescopic or cascade topology is not suitable for this work. The performance of the LDO is dominated by the loop-gain, which could be contributed from a single-stage operational amplifier and a PMOS pass device. Thus, the single-stage topology is chosen to satisfy low voltage and quiescent current as well.
On other hand, the pass element is also an issue in LDO system. Designing in a low voltage and low current environment provides difficult challenges that contradict performance and stability. The pass device should provide large amount of current while displaying low-drop characteristics. So the size of the transistor as the pass device must be large under low voltage condition. A large device is further demanded because voltage drive is reduced as a result of decreased input voltages. The phenomenon causes the parasitic pole P3 to move to lower frequencies effectively deteriorating phase margin and compromising the stability of the system. In summary, the size of the pass device must be large for increased current capabilities but restrained by stability and slew rate requirements in a low quiescent current and low voltage environment. In this work, the PMOS is used because the drop-out voltage between the input voltage and the output voltage should be minimized.
Second, the bandgap voltage reference structure and schematic are illustrated in Figure 4.6 and Figure 4.7 [21]. The amplifier enforces nodes N1 and N2 to have equal potential. As a result, nodes N3 and N4 also have equal potential when R2A1=R2B1 and R2A2=R2B2. Therefore, voltage is described as follows:
⎥⎦
A scaled-down bandgap reference voltage can be obtained by an appropriate resistor ratio of R3 and R2. Moreover, this circuitry takes advantage of resistor ratio (ratio of R2 and R1) not only to achieve a good temperature coefficient but also reduce the supply voltage. The
A scaled-down bandgap reference voltage can be obtained by an appropriate resistor ratio of R3 and R2. Moreover, this circuitry takes advantage of resistor ratio (ratio of R2 and R1) not only to achieve a good temperature coefficient but also reduce the supply voltage. The