Flexible and vertically stacked 1S1R array

Figure 5.9 shows reproducible nonlinear bipolar RS curves in the stacked Ni/TiO₂/Ni/HO₂/Pt cell, where high nonlinearity at low voltage regime was dominated by the bipolar selector, and resistive-switching at high voltage regime was dominated by the memory element. VSET/VRESET below ±4 V, IRESET less than 150



A, and

 of 10

³ at 1.2 V

V

_read were realized. As we have discussed in Chapter 4 (Fig. 4.3), this reported

 is sufficient

to implement a high-density array of 10 Mb, the largest ever reported for a 1D1R or 1S1R crossbar array. A gigabit memory chip partitioned into 16 banks would require a single array (bank) size of 64 Mb [76]. In order to evaluate the 8 × 8 1S1R crossbar array, all unselected cells were firstly programmed to LRS except the selected cell as shown in the equivalent circuit in Fig. 5. 10. To read the selected bit (as marked in red square), a voltage V_pu was applied between the selected top electrode and bottom electrode, while all unselected top/bottom lines were floating. As displayed in Fig. 5. 10, the read current with respect to the LRS/HRS of the selected cell in 8 × 8 crossbar arrays can be compared. With an Rpu load line was plotted, we can estimate the voltage swing (V) between the 1S1R and 1R only crossbar arrays. Though device uniformity has not yet been optimized in the 8 × 8 1S1R array, successfully read margin of 0.82 V can be performed even when all unselected bits were at LRS, in sharp contrast to the collapsed read margin in an 8×8 1R array.

Moreover, program disturb in crossbar arrays is also a serious issue. To reduce disturbs to neighboring cells in the 1S1R array, the Vdd/2 write scheme, a much severe condition as compared to the V_dd/3 scheme, was used to evaluate the 1S1R write operation as illustrated in Fig. 5.11(a). In this scheme, a full VSET or VRESET was applied to the selected cell, but only those unselected cells along the selected word line or bit line endured one half of V_SET or

V

RESET. Figure 5.11(b) shows the excellent immunity of both LRS and HRS to program disturb at 1/2 V_SET and 1/2 V_RESET. In this case, stress voltages of +2 V for HRS and –2 V for LRS were applied to perform the immunity of SET/RESET disturbance of stacked

Ni/TiO₂/Ni/HfO₂/Pt. Finally, we conclude three possible architectures, 1S1R, 1D1R and CRS in Fig. 5.12. Based on the analytical calculation used in Chapter 4, the maximum allowed array number with the corresponding architectures as a function of nonlinear factor (



) can be plotted. Note that we redefined the R_HRS/R_LRS ratio of memory elements in CRS from the reported data [39] as the nonlinear factor. From the best reported CRS data [41], nonlinearity ~10² can only be utilized up to 16K-bit for CRS array. In comparison with our reported data, 512K-bit for 1D1R and 10M-bit for 1S1R have been demonstrated and realized on flexible substrates, showing their potential applications for future flexible electronics.

5.4 Summary

In this chapter, we demonstrate the bipolar I–V characteristics of flexible Ni/TiO₂/Ni selector with high nonlinearity and the stable RS characteristics of Ni/HfO2/Pt. The flexible Ni/TiO₂/Ni and Ni/HfO₂/Pt elements also had excellent mechanical stability upon harsh bending. Furthermore, a vertically stacked 8 × 8 1S1R array with superior read margin, endurance, immunity to read/program disturbs and retention has been realized. The simple cell structure and room-temperature process are particularly attractive for implementing high-density NVM in future low-cost flexible electronics and three-dimensional integrated circuits.

Fig. 5.1 (a) Polyimide (PI) substrates were prepared and ultrasonically cleaned in acetone. (b) Pt/Ti bottom electrodes deposition through mask 1.

Fig. 5.1 (c) HfO₂ deposition through mask 2 and (d) Ni metal layer deposition through mask 3.

Fig. 5.1 (e) TiO₂ deposition through mask 4 and (f) Ni top electrode deposition through mask 5.

Fig. 5.2 (a) Cross-sectional view and (b) photograph of a flexible 8×8 1S1R memory array with a curly bending, and (c) optical microscope image of a vertically stacked Ni/TiO2/Ni/HfO2/Pt cell.

Fig. 5.3 Photograph of a flexible device with a bending radius of 10 mm under electrical testing.

-4 -2 0 2 4

Fig. 5.4 Highly nonlinear and reproducible I-V curves of Ni/TiO2/Ni bipolar selector (1000 successive cycles) by Schottky emission over Ni/TiO₂ barriers.

10

³

10

⁴

10

⁵

10

⁶

10

⁷

10

⁸

Fig. 5.5 (a) Endurance of the flat and bending Ni/TiO₂/Ni bipolar selectors under ±3 V DC cycling and (b) measured resistance of Ni/TiO2/Ni bipolar selector at alternate flat and bending states.

(a)

(b)

-3 -2 -1 0 1 2 3

Fig. 5.6 (a) 100 successive bipolar RS I-V curves and (b) cumulative distribution of SET voltage and RESET voltage for both flat and bending Ni/HfO2/Pt memory elements.

(a)

(b)

10

⁰

10

¹

10

²

10

³

Fig. 5.7 (a) Read disturbance measurement stressed at 0.2 V and (b) retention measurement of flat and bending Ni/HfO₂/Pt memory elements.

(a)

(b)

0.0 0.5 1.0 1.5 2.0 2.5

-4 -3 -2 -1 0 1 2 3 4 10 ^-9

10 ^-7 10 ^-5 10 ^-3

Current (A)

Voltage (V)

2

V

read ^read

V

~ 10 ³

Fig. 5.9 Bipolar I-V RS cycles of vertically stacked Ni/TiO2/Ni/HfO2/Pt with



of 10³ at Vread of 1.2 V.

Fig. 5.10 Read margin between LRS and HRS in an 8 × 8 1R array and 1S1R array where all unselected bits were at LRS (See equivalent circuits in Fig. 4.1 & 4.2).

V

Fig. 5.11 (a) Vdd/2 SET/RESET scheme where only the unselected bits on the activated WL and BL are subjected to disturb voltage of V/2 and (b) SET/RESET disturbance measurement at 1/2 VSET/VRESET on vertically stacked Ni/TiO2/Ni/HfO2/Pt. HRS was stressed at +2 V while LRS was stressed at -2 V.

(a)

(b)

10

¹

10

²

10

³

10

⁴

10

⁵

10

⁶

10

⁷

Fig. 5.12 Comparison of the maximum allowed array number based on the reported 1S1R [77, 79], 1D1R [73] and CRS [41, 78] architectures.

Chapter 6

Conclusion and Further Recommendation

6.1 Conclusion

Two TiO2-based selection devices were proposed to reduce the sneak current in this dissertation. The unipolar Ti/TiO₂/Pt diode shows superior capability of conducting unipolar 1D1R switching by externally connecting a Ni/HfO2/Pt memory element. Meanwhile, a bipolar Ni/TiO₂/Ni selector was investigated to perform the stable bipolar 1S1R switching with a bipolar RS element connected. Finally, an 8 × 8 1S1R array on the flexible substrate was successfully realized. The main results of these studies are summarized below.

In Chapter 2, we report the transition of stable rectification to resistive-switching behaviors in a Ti/TiO₂/Pt MIM. The oxygen migration and localized conductive filaments play important roles in not only the resistive-switching of RRAM devices but also the rectification of oxide diodes. When the current flows through the oxygen-deficient TiO₂ filaments, current behaviors were limited by the interfaces of Schottky barrier, resulting in the diode rectifying properties. After forming at higher voltage, much stronger filaments destroy the interface Schottky barrier, giving rise to the reproducible resistive-switching. The rectification properties are stable up to 125 °C and 10³ cycles under ±3 V sweep without interference with the resistive-switching. Moreover, the current density of TiO2 MIM diodes more than 10⁴ A/cm² can be achieved, showing the satisfactory requirement of TiO₂ MIM diodes for future 1D1R RRAM applications.

In Chapter 3, a rectifying Ti/TiO₂/Pt oxide diode and a unipolar Ni/HfO₂/Pt memory element have been fabricated on flexible PI substrates using only room-temperature

processes. No significant device degradation was found at bending states. Additionally, the impact of IRESET on the programming margin of unipolar RS has been discussed. The heterogeneous TiO₂-HfO₂ 1D1R cell not only demonstrates more stable unipolar RS compared to the monolithic TiO2 1D1R cell because of the lower IRESET of the HfO2 memory element, but also effectively suppresses the sneak current. The maximum allowed array size with at least 10% read margin was predicted to exceed 512 Kb based on a simple equivalent circuit model.

In Chapter 4, a Ni/TiO₂/Ni MIM with highly nonlinear I-V characteristics has been proposed by a very simple low-temperature process. Excellent bipolar nonlinear characteristics, including current difference of 6 orders of magnitude for a voltage swing from 0 to ±2 V and a breakdown voltage larger than 4 V are demonstrated. The nonlinearity was attributed to the Schottky emission over the Ni/TiO₂ barriers. By connecting the bipolar selector and a HfO2 memory element, 1S1R exhibits robust and stable bipolar RS, and can effectively suppress the sneak current. In addition, the trade-off between the maximum array size and the power consumption is also discussed.

In Chapter 5, we used a low-temperature and simple sputtering process to fabricate a flexible Ni/TiO₂/Ni selector and Ni/HfO₂/Pt memory element. The flexible Ni/TiO₂/Ni and Ni/HfO2/Pt elements also had excellent mechanical stability upon harsh bending.

Furthermore, by a simple 5-mask process, we report for the first time a vertically stacked Ni/TiO2/Ni/HfO2/Pt 8×8 1S1R array fabricated completely at room temperature on a plastic substrate. This stacked 8×8 1S1R array with superior read margin, endurance, immunity to read/write disturbs and retention were examined. The simple cell structure and room-temperature process are particularly attractive for implementing high-density NVM in

6.2 Further Recommendation

It is necessary to further pursue the selection devices with high turn-on current density and high nonlinearity for the 1D1R or 1S1R architectures. Meanwhile, the improvement of process integration of selection devices and RS elements is an important research direction for 3D stackable crossbar arrays as well. There are some interesting topics related to this dissertation that are worthy to be further investigated:

(1) As described in Chapters 1, 2 and 3, a unipolar diode with high turn-on current density and high rectifying ratio is considerably required to build high-density crossbar memory arrays. Although the Ti/TiO2/Pt oxide diode with current density of ~10⁴ A/cm² and rectifying ratio of ~10⁵ have been achieved in this dissertation, current density and rectifying ratio of oxide diodes should be further improved to 10⁷ and 10⁹, respectively, in order to implement 1 G-bit memory size at the technology node of 100 nm (Fig. 1.4).

To modulate interface barriers with other various materials considered is a key direction to increase the current density and rectifying ratio. Furthermore, the process integration of 1D1R structure also dominates the electrical properties. As shown in Fig. 3. 10(a), surface roughness at the 2^nd Pt layer may cause unstable operation of the Ti/TiO₂/Pt diode.

Hence, a smooth interface is needed to be investigated carefully.

(2) In Chapters 4 and 5, we proposed a nonlinear Ni/TiO2/Ni bipolar selector for implementing 1S1R architectures. It is highly required that if the nonlinearity can be further enlarged to 10⁴, 1 G-bit of memory size will be available in our 1S1R architecture.

The nonlinearity of Ni/TiO₂/Ni may be improved by introducing the bandgap engineering, i.e. using MIIIM structure to replace MIM structure. This has been reported in FLASH

memory technologies to improve the tunneling efficiency of tunneling oxide. Here, we believe that this tri-layer structure can increase the required nonlinearity for high-density crossbar memory applications. Furthermore, it is worthy to use NEGF simulation to predict and examine the current transportations and discuss the effects of barrier heights and thicknesses of tri-layer structures.

(3) By a first approximation, we discuss the prediction model using the simplified One-BLPU read scheme. For simplicity, we ignored the voltage drop on RI and RIII for 1D1R configuration, and R_II for 1S1R configuration, respectively. The proper way to predict the read margin as a function of array size is by using HSPICE, where the lines resistance, voltage drop on each node could be included in the HSPICE calculation. In addition, as we have discussed in Chapter 1, there are nine possible voltage configurations to conduct a read process, so it is recommended that each read configuration must be carefully investigated based on the three architectures, 1S1R, 1D1R, CRS.

References

[1] H. Sungjoo, "Memory technology trend and future challenges," in IEDM Tech. Dig., 2010, pp. 292-295.

[2] K. Yohwan, "NAND flash scaling beyond 20nm," in Proc. Int. Memory Workshop, 2009, pp. 3–5.

[3] X. Yuan, "Modeling, architecture, and applications for emerging memory technologies," IEEE Design & Test Comput., vol. 28, no. 1, pp. 44-50, 2011.

[4] S. Lai, "Current status of the phase change memory and its future," in IEDM Tech.

Dig., 2003, pp. 255-258.

[5] C. J. Lin, Y. J. Wang, K. Lee, X. Zhu, W. C. Chen, X. Li, W. N. Hsu, Y. C. Kao, M. T.

Liu, W. C. Chen, Y. C. Lin, M. Nowak, and N. Yu, and L. Tran, "45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell," in IEDM Tech. Dig., 2009, pp. 279-282.

[6] R. Waser and M. Aono, "Nanoionics-based resistive switching memories," Nat.

Mater., vol. 6, pp. 833-840, 2007.

[7] J. A. Rogers, T. Someya, and Y. Huang, "Materials and mechanics for stretchable electronics," Science, vol. 327, no. 5973, pp. 1603-1607, 2010.

[8] T. Tsutsui and K. Fujita, "The shift from “hard” to “soft” electronics," Adv. Mater., vol. 14, no. 13-14, pp. 949-952, 2002.

[9] R. H. Reuss, B. R. Chalamala, A. Moussessian, M. G. Kane, A. Kumar, D. C. Zhang, J. A. Rogers, M. Hatalis, D. Temple, G. Moddel, B. J. Eliasson, M. J. Estes, J. Kunze, E. S. Handy, E. S. Harmon, D. B. Salzman, J. M. Woodall, M. A. Alam, J. Y. Murthy, S. C. Jacobsen, M. Olivier, D. Markus, P. M. Campbell, and E. Snow,

"Macroelectronics: perspectives on technology and applications," Proc. IEEE, vol. 93,

no. 7, pp. 1239-1256, 2005.

[10] http://www.epapercentral.com/lg-debuts-flexible-epaper.htm

[11] E. Abad, S. Zampolli, S. Marco, A. Scorzoni, B. Mazzolai, A. Juarros, D. Gómez, I.

Elmi, G. C. Cardinali, J. M. Gómez, F. Palacio, M. Cicioni, A. Mondini, T. Becker, and I. Sayhan, "Flexible tag microlab development: Gas sensors integration in RFID flexible tags for food logistic," Sens. Actuators B, Chem., vol. 127, no. 1, pp. 2–7, 2007.

[12] http://inhabitat.com/samsung-to-launch-flexible-oled-cell-phone-next-year/

[13] T. W. Hickmott, "Low-frequency negative resistance in thin anodic oxide films," J.

Appl. Phys., vol. 33, no. 9, pp. 2669-2682, 1962.

[14] R. Waser, R. Dittmann, G. Staikov, and K. Szot, "Redox-based resistive switching memories–nanoionic mechanisms, prospects, and challenges," Adv. Mater., vol. 21, no. 25-26, pp. 2632-2663, 2009.

[15] K. L. Lin, T. H. Hou, J. Shieh, J. H. Lin, C. T. Chou, and Y. J. Lee, "Electrode dependence of filament formation in HfO₂ resistive-switching memory," J. Appl.

Phys., vol. 109, no 8, 084104, 2011.

[16] T. H. Hou, K. L. Lin, J. Shieh, J. H. Lin, C. T. Chou, and Y. J. Lee, "Evolution of RESET current and filament morphology in low-power HfO2 unipolar resistive switching memory," Appl. Phys. Lett., vol. 98, no. 10, 103511, 2011.

[17] S. Seo, M. J. Lee, D. H. Seo, E. J. Jeoung, D. S. Suh, Y. S. Joung, I. K. Yoo, I. R.

Hwang, S. H. Kim, I. S. Byun, J. S. Kim, J. S. Choi, and B. H. Park, "Reproducible resistance switching in polycrystalline NiO films," Appl. Phys. Lett., vol. 85, no. 23, pp. 5655-5657, 2004.

[18] J. J. Yang, M. D. Pickett, X. Li, D. A. A. Ohlberg, D. R. Stewart, and R. S. Williams,

"Memristive switching mechanism for metal/oxide/metal nanodevices," Nat.

[19] Z. Wei, Y. Kanzawa, K. Arita, Y. Katoh, K. Kawai, S. Muraoka, S. Mitani, S. Fujii, K.

Katayama, M. Iijima, T. Mikawa, T. Ninomiya, R. Miyanaga, Y. Kawashima, K. Tsuji, A. Himeno, T. Okada, R. Azuma, K. Shimakawa, H. Sugaya, T. Takagi, R. Yasuhara, K. Horiba, H. Kumigashira, and M. Oshima, "Highly reliable TaOx ReRAM and direct evidence of redox reaction mechanism," in IEDM Tech. Dig., 2008, pp.

293-296.

[20] P. Gonon, M. Mougenot, C. Vallee, C. Jorel, V. Jousseaume, H. Grampeix, and F. El Kamel, "Resistance switching in HfO2 metal-insulator-metal devices," J. Appl. Phys., vol. 107, no. 7, pp. 074507, 2010.

[21] A. Flocke and T. G. Noll, "Fundamental analysis of resistive nanocrossbars for the use in hybrid nano/CMOS-memory," in Proc. 33rd ESSCIRC, 2007, pp. 328–331.

[22] J. Liang and H. S. P. Wong, "Cross-point memory array without cell selectors-device characteristics and data storage pattern dependencies," IEEE Transactions Electron

Devices, vol. 57, no. 10, pp. 2531-2538, 2010.

[23] A. Flocke, T. G. Noll, C. Kugeler, C. Nauenheim, and R. Waser, "A fundamental analysis of nano-Crossbars with non-linear switching materials and its impact on TiO₂ as a resistive layer," in Proc. 8th Conf. IEEE-NANO, 2008, pp. 319-322.

[24] F. Nardi, D. Ielmini, C. Cagli, S. Spiga, M. Fanciulli, L. Goux, and D. J. Wouters,

"Sub-10 A reset in NiO-based resistive switching memory (RRAM) cells," in Proc.

Int. Memory Workshop, 2010, pp. 1–4.

[25] K. Kinoshita, K. Tsunoda, Y. Sato, H. Noshiro, S. Yagaki, M. Aoki, and Y. Sugiyama,

"Reduction in the reset current in a resistive random access memory consisting of NiO_x brought about by reducing a parasitic capacitance," Appl. Phys. Lett., vol. 93, no. 3, pp. 033506, 2008.

[26] I. G. Baek, D. C. Kim, M. J. Lee, H. J. Kim, E. K. Yim, M. S. Lee, J. E. Lee, S. E.

Ahn, S. Seo, J. H. Lee, J. C. Park, Y. K. Cha, S. O. Park, H. S. Kim, I. K. Yoo, U. I.

Chung, J. T. Moon, and B. I. Ryu, "Multi-layer cross-point binary oxide resistive memory (OxRRAM) for post-NAND storage application," in IEDM Tech. Dig., 2005, pp. 750-753.

[27] Y. Sasago, M. Kinoshita, T. Morikawa, K. Kurotsuchi, S. Hanzawa, T. Mine, A.

Shima, Y. Fujisaki, H. Kume, H. Moriya, N. Takaura, and K. Torii, "Cross-point phase change memory with 4F² cell size driven by low-contact-resistivity poly-Si diode," in VLSI Symp. Tech. Dig., 2009, pp. 24-25.

[28] T. W. Kim, D. F. Zeigler, O. Acton, H. L. Yip, H. Ma, and A. K. Y. Jen, "All-organic photopatterned one diode-one resistor cell array for advanced organic nonvolatile memory applications," Adv. Mater., vol. 24, no. 6, pp. 828-833, 2012.

[29] Y. Hosoi, Y. Tamai, T. Ohnishi, K. Ishihara, T. Shibuya, Y. Inoue, S. Yamazaki, T.

Nakano, S. Ohnishi, N. Awaya, H. Inoue, H. Shima, H. Akinaga, H. Takagi, H. Akoh, and Y. Tokura, "High speed unipolar switching resistance RAM (RRAM) technology," in IEDM Tech. Dig., 2006, 547-550.

[30] M. Kinoshita, Y. Sasago, H. Minemura, Y. Anzai, M. Tai, Y. Fujisaki, S. Kusaba, T.

Morimoto, T. Takahama, T. Mine, A. Shima, Y. Yonamoto, and T. Kobayashi,

"Scalable 3-D vertical chain-cell-type phase-change memory with 4F² poly-Si diodes," in VLSI Symp. Tech. Dig., 2012, pp. 35-36.

[31] M. J. Lee, S. Seo, D. C. Kim, S. E. Ahn, D. H. Seo, I. K. Yoo, I. G. Baek, D. S. Kim, I.

S. Byun, S. H. Kim, I. R. Hwang, J. S. Kim, S. H. Jeon, and B. H. Park, "A low-temperature-grown oxide diode as a new switch element for high-density, nonvolatile memories," Adv. Mater., vol. 19, no. 1, pp. 73-76, 2007.

[32] M. J. Lee, Y. Park, B. S. Kang, S. E. Ahn, C. Lee, K. Kim, W. Xianyu, G. Stefanovich, J. H. Lee, S. J. Chung, Y, H, Kim, C. S Lee, J. B. Park, I. G. Baek and I. K. Yoo,

"2-stack 1D-1R cross-point structure with oxide Diodes as switch elements for high

[33] S. E. Ahn, B. S. Kang, K. H. Kim, M. J. Lee, C. B. Lee, G. Stefanovich, C. J. Kim, and Y. Park, "Stackable all-oxide-based nonvolatile memory with Al2O3 antifuse and p-CuO_x/n-InZnO_x diode," IEEE Electron Device Letters, , vol. 30, no. 5, pp. 550-552, 2009.

[34] E. Katsia, N. Huby, G. Tallarida, B. Kutrzeba-Kotowska, M. Perego, S. Ferrari, F. C.

Krebs, E. Guziewicz, M. Godlewski, V. Osinniy, and G. Luka,

"Poly(3-hexylthiophene)/ZnO hybrid pn junctions for microelectronics applications,"

Appl. Phys. Lett., vol. 94, no. 14, 143501, 2009.

[35] H. Shima, F. Takano, H. Muramatsu, H. Akinaga, I. H. Inoue, and H. Takagi,

"Control of resistance switching voltages in rectifying Pt/TiOx/Pt trilayer," Appl.

Phys. Lett., vol. 92, no. 4, 043510, 2008.

[36] H. Shima, N. Zhong, and H. Akinaga, "Switchable rectifier built with Pt/TiOx/Pt trilayer," Appl. Phys. Lett., vol. 94, no. 8, 082905, 2009.

[37] Y. C. Shin, J. Song, K. M. Kim, B. J. Choi, S. Choi, H. J. Lee, G. H. Kim, T. Eom, and C. S. Hwang, "(In,Sn)₂O₃/TiO₂/Pt Schottky-type diode switch foe the TiO₂ resistive switching memory array," Appl. Phys. Lett., vol. 92, no. 16, 162904, 2008.

[38] N. Zhong, H. Shima, and H. Akinaga, "Rectifying characteristic of Pt/TiO_x/metal/Pt controlled by electronegativity," Appl. Phys. Lett., vol. 96, no. 4, 042107, 2010.

[39] E. Linn, R. Rosezin, C. Kugeler, and R. Waser, "Complementary resistive switches for passive nanocrossbar memories," Nat. Mater., vol. 9, no. 5, pp. 403-406, 2010.

[40] M. J. Lee, C. B. Lee, D. Lee, S. R. Lee, M. Chang, J. H. Hur, Y. B. Kim, C. J. Kim, D.

H. Seo, S. Seo, U. I. Chung, I. K. Yoo, and K. Kim, "A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta₂O_5-x/TaO_2-x bilayer structures," Nat. Mater., vol. 10, no. 8, pp. 625-630, 2011.

[41] J. Lee, J. Shin, D. Lee, W. Lee, S. Jung, M. Jo, J. Park, K. P. Biju, S. Kim, S. Park, and H. Hwang, "Diode-less nano-scale ZrO /HfO RRAM device with excellent

switching uniformity and reliability for high density cross-point memory applications," in IEDM Tech. Dig., 2010, pp. 452–455.

[42] S. M. Yu, J. L. Liang, Y. Wu, and H. S. P. Wong, "Read/write schemes analysis for novel complementary resistive switches in passive crossbar memory arrays,"

Nanotechnology, vol. 21, no. 46, 465202, 2010.

[43] J. Shin, I. Kim, K. P. Biju, M. Jo, J. Park, J. Lee, S. Jung, W. Lee, S. Kim, S. Park, and H. Hwang, "TiO₂-based metal-insulator-metal selection device for bipolar resistive random access memory cross-point application," J. Appl. Phys., vol. 109, no.

3, 033712, 2011.

[44] J. Shin, G. Choi, J. Woo, J. Park, S. Park, W. Lee, S. Kim, M. Son, and H. Hwang,

"MIM-type cell selector for high-density and low-power cross-point memory application," Microelectron. Eng., vol. 93, pp. 81-84, 2012.

[45] Y. C. Chen, C. F. Chen, C. T. Chen, J. Y. Yu, S. Wu, S. L. Lung, R. Liu, C. Y. Lu, "An access-transistor-free (0T/1R) non-volatile resistance random access memory (RRAM) using a novel threshold switching, self-rectifying chalcogenide device," in

IEDM Tech. Dig., 2003, pp. 905-908.

[46] C. An, "Accessibility of nano-crossbar arrays of resistive switching devices," in Proc.

11th Conf. IEEE-NANO, 2011, pp. 1767-1771.

[47] N. Gergel-Hackett, B. Hamadani, B. Dunlap, J. Suehle, C. Richter, C. Hacker, and D.

Gundlach, "A flexible solution-processed memristor," IEEE Electron Device Letters, vol. 30, no. 7, pp. 706-708, 2009.

[48] H. Y. Jeong, Y. I. Kim, J. Y. Lee, and S. Y. Choi, "A low-temperature-grown TiO₂-based device for the flexible stacked RRAM application," Nanotechnology, vol.

21, no. 11, 115203, 2010.

[49] S. Kim, H. Y. Jeong, S. K. Kim, S. Y. Choi, and K. J. Lee, "Flexible memristive

2011.

[50] W. Y. Lee, D. Mauri, and C. Hwang, "High-current-density ITOx/NiOx thin-film diodes," Appl. Phys. Lett., vol. 72, no. 13, pp. 1584-1586, 1998.

[51] J. J. Huang, G. L. Lin, C. W. Kuo, W. C. Chang, and T. H. Hou, "Room-temperature TiO_x oxide diode for 1D1R resistance-switching memory," in International

Semiconductor Device Research Symposium (ISDRS), College Park, MA, USA, Dec.

9-11, 2009.

[52] B. J. Choi, D. S. Jeong, S. K. Kim, C. Rohde, S. Choi, J. H. Oh, H. J. Kim, C. S.

Hwang, K. Szot, R. Waser, B. Reichenberg, and S. Tiedke, "Resistive switching mechanism of TiO2 thin films grown by atomic-layer deposition," J. Appl. Phys., vol.

98, no. 3, 033715, 2005.

[53] J. J. Yang, M. Feng, D. P. Matthew, A. A. O. Douglas, R. S. Duncan, L. Chun Ning, and R. S. Williams, "The mechanism of electroforming of metal oxide memristive switches," Nanotechnology, vol. 20, no. 21, 215201, 2009.

[54] D. H. Kwon, K. M. Kim, J. H. Jang, J. M. Jeon, M. H. Lee, G. H. Kim, X. S. Li, G. S.

Park, B. Lee, S. Han, M. Kim, and C. S. Hwang, "Atomic structure of conducting nanofilaments in TiO2 resistive switching memory," Nat. Nanotechnology, vol. 5, no.

2, pp. 148-153, 2010.

[55] C. Cagli, F. Nardi, and D. Ielmini, "Modeling of set/reset operations in NiO-based resistive-switching memory devices," IEEE Trans. Electron Devices, vol. 56, no. 8, pp. 1712-1720, 2009.

[56] C. W. Wang, S. F. Chen, and G. T. Chen, "Gamma-ray-irradiation effects on the leakage current and reliability of sputtered TiO₂ gate oxide in metal-oxide-semiconductor capacitors," J. Appl. Phys., vol. 91, no. 11, pp. 9198-9203, 2002.

[57] J. McPherson, J. Y. Kim, A. Shanware, and H. Mogul, "Thermochemical description of dielectric breakdown in high dielectric constant materials," Appl. Phys. Lett., vol.

在文檔中 應用於高密度資料儲存與軟性電子之交錯電阻式記憶體 (頁 99-0)